i965: Fill in Sample Mask in Haswell's 3DSTATE_PS.

We only need one sample, since we don't support multisampling yet.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e7326c6..2d47ef8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1395,6 +1395,8 @@ enum brw_wm_barycentric_interp_mode {
 /* DW4 */
 # define IVB_PS_MAX_THREADS_SHIFT                      24
 # define HSW_PS_MAX_THREADS_SHIFT                      23
+# define HSW_PS_SAMPLE_MASK_SHIFT                      12
+# define HSW_PS_SAMPLE_MASK_MASK                       INTEL_MASK(19, 12)
 # define GEN7_PS_PUSH_CONSTANT_ENABLE                  (1 << 11)
 # define GEN7_PS_ATTRIBUTE_ENABLE                      (1 << 10)
 # define GEN7_PS_OMASK_TO_RENDER_TARGET                        (1 << 9)

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 773598f..024c855 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -155,6 +155,9 @@ upload_ps_state(struct brw_context *brw)
    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
+   if (intel->is_haswell)
+      dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
+
    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 
    /* CACHE_NEW_WM_PROG */