},
{
"chips": ["gfx10"],
+ "map": {"at": 165712, "to": "mm"},
+ "name": "SX_PS_DOWNCONVERT_CONTROL_GFX103",
+ "type_ref": "SX_PS_DOWNCONVERT_CONTROL"
+ },
+ {
+ "chips": ["gfx10"],
"map": {"at": 165716, "to": "mm"},
"name": "SX_PS_DOWNCONVERT",
"type_ref": "SX_PS_DOWNCONVERT"
{"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
{"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
{"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
- {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}
+ {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"},
+ {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO_GFX103"},
+ {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE_GFX103"}
]
},
"CB_COLOR0_INFO": {
{"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
{"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
{"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
- {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
+ {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
+ {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE_GFX103"}
]
},
"DB_RMI_L2_CACHE_CONTROL": {
"PA_CL_NGG_CNTL": {
"fields": [
{"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
- {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
+ {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
+ {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH_GFX103"}
]
},
"PA_CL_OBJPRIM_ID_CNTL": {
{"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
{"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
{"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
- {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"},
- {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}
+ {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
+ {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER_GFX103"},
+ {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER_GFX103"}
]
},
"PA_CL_VTE_CNTL": {
{"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
{"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
{"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
- {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
+ {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
+ {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING_GFX103"},
+ {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER_GFX103"}
]
},
"PA_SC_AA_MASK_X0Y0_X1Y0": {
{"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
]
},
+ "SX_PS_DOWNCONVERT_CONTROL": {
+ "fields": [
+ {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
+ {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
+ {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
+ {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
+ {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
+ {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
+ {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
+ {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
+ ]
+ },
"SX_PS_DOWNCONVERT": {
"fields": [
{"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
"VGT_HS_OFFCHIP_PARAM_UMD": {
"fields": [
{"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
- {"bits": [9, 10], "name": "OFFCHIP_GRANULARITY"}
+ {"bits": [9, 10], "name": "OFFCHIP_GRANULARITY"},
+ {"bits": [0, 9], "name": "OFFCHIP_BUFFERING_GFX103"},
+ {"bits": [10, 11], "name": "OFFCHIP_GRANULARITY_GFX103"}
]
},
"VGT_INSTANCE_BASE_ID": {
unsigned initial_cdw = sctx->gfx_cs->current.cdw;
unsigned pa_cl_cntl = S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
- S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) | clipdist_mask |
- (culldist_mask << 8);
+ S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
+ S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(sctx->chip_class >= GFX10_3) |
+ clipdist_mask | (culldist_mask << 8);
if (sctx->chip_class >= GFX10) {
radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
radeon_opt_set_context_reg(
sctx, R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
- S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
- S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
+ S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
+ S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
+ S_028010_CENTROID_COMPUTATION_MODE_GFX103(sctx->chip_class >= GFX10_3 ? 2 : 0));
db_shader_control = sctx->ps_db_shader_control;
sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
- S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
+ S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) |
+ S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(sctx->chip_class >= GFX10_3);
if (sctx->framebuffer.nr_samples > 1) {
db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
* a single primitive shader subgroup.
*/
si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
+ /* Reuse for legacy (non-NGG) only. */
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
if (!has_clear_state) {
S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
}
+ if (sctx->chip_class >= GFX10_3) {
+ si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
+ }
if (sctx->chip_class >= GFX9) {
si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,