: m_out_stream(colors), m_err_stream(colors) {}
void CommandReturnObject::AppendErrorWithFormat(const char *format, ...) {
+ SetStatus(eReturnStatusFailed);
+
if (!format)
return;
va_list args;
void CommandReturnObject::AppendError(llvm::StringRef in_string) {
if (in_string.empty())
return;
+ SetStatus(eReturnStatusFailed);
error(GetErrorStream()) << in_string.rtrim() << '\n';
}
return;
AppendError(error_str);
- SetStatus(eReturnStatusFailed);
}
// Similar to AppendError, but do not prepend 'Status: ' to message, and don't
if (in_string.empty())
return;
GetErrorStream() << in_string;
+ SetStatus(eReturnStatusFailed);
}
void CommandReturnObject::SetStatus(ReturnStatus status) { m_status = status; }
self.expect("register read -a", MISSING_EXPECTED_REGISTERS,
substrs=['registers were unavailable'], matching=False)
+ all_registers = self.res.GetOutput()
+
if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
self.runCmd("register read xmm0")
- self.runCmd("register read ymm15") # may be available
- self.runCmd("register read bnd0") # may be available
+ if "ymm15 = " in all_registers:
+ self.runCmd("register read ymm15") # may be available
+ if "bnd0 = " in all_registers:
+ self.runCmd("register read bnd0") # may be available
elif self.getArchitecture() in ['arm', 'armv7', 'armv7k', 'arm64', 'arm64e', 'arm64_32']:
self.runCmd("register read s0")
- self.runCmd("register read q15") # may be available
+ if "q15 = " in all_registers:
+ self.runCmd("register read q15") # may be available
self.expect(
"register read -s 4",
self.write_and_read(currentFrame, "ymm7", new_value)
self.expect("expr $ymm0", substrs=['vector_type'])
else:
- self.runCmd("register read ymm0")
+ self.expect("register read ymm0", substrs=["Invalid register name 'ymm0'"],
+ error=True)
if has_mpx:
# Test write and read for bnd0.
self.write_and_read(currentFrame, "bndstatus", new_value)
self.expect("expr $bndstatus", substrs = ['vector_type'])
else:
- self.runCmd("register read bnd0")
+ self.expect("register read bnd0", substrs=["Invalid register name 'bnd0'"],
+ error=True)
def convenience_registers(self):
"""Test convenience registers."""
# Now write rax with a unique bit pattern and test that eax indeed
# represents the lower half of rax.
self.runCmd("register write rax 0x1234567887654321")
- self.expect("register read rax 0x1234567887654321",
+ self.expect("register read rax",
substrs=['0x1234567887654321'])
def convenience_registers_with_process_attach(self, test_16bit_regs):
-# Check basic functionality of command bt.
# RUN: %lldb -s %s 2>&1 | FileCheck %s
# Make sure this is not rejected by the parser as invalid syntax.
-# Blank characters after the '1' are important, as we're testing the parser.
-bt 1
-# CHECK: error: invalid target
-
-# Make sure this is not rejected by the parser as invalid syntax.
# Blank characters after the 'all' are important, as we're testing the parser.
bt all
# CHECK: error: invalid target