intel: Add the defines for the kernel overlay support landing in 2.6.33.

diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h
index b214600..0132e55 100644 (file)
--- a/shared-core/i915_drm.h
+++ b/shared-core/i915_drm.h
@@ -207,6 +207,8 @@ typedef struct drm_i915_sarea {
 #define DRM_I915_GEM_MMAP_GTT  0x24
 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
 #define DRM_I915_GEM_MADVISE   0x26
+#define DRM_I915_OVERLAY_PUT_IMAGE     0x27
+#define DRM_I915_OVERLAY_ATTRS 0x28
 
 #define DRM_IOCTL_I915_INIT            DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH           DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -246,6 +248,8 @@ typedef struct drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_GET_APERTURE        DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 #define DRM_IOCTL_I915_GEM_MADVISE     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
+#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE       DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
+#define DRM_IOCTL_I915_OVERLAY_ATTRS   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 
 /* Asynchronous page flipping:
  */
@@ -301,6 +305,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_CHIPSET_ID            4
 #define I915_PARAM_HAS_GEM               5
 #define I915_PARAM_NUM_FENCES_AVAIL      6
+#define I915_PARAM_HAS_OVERLAY           7
 
 typedef struct drm_i915_getparam {
        int param;
@@ -743,4 +748,70 @@ struct drm_i915_gem_madvise {
        uint32_t retained;
 };
 
+/* flags */
+#define I915_OVERLAY_TYPE_MASK                 0xff
+#define I915_OVERLAY_YUV_PLANAR        0x01
+#define I915_OVERLAY_YUV_PACKED        0x02
+#define I915_OVERLAY_RGB               0x03
+
+#define I915_OVERLAY_DEPTH_MASK                0xff00
+#define I915_OVERLAY_RGB24             0x1000
+#define I915_OVERLAY_RGB16             0x2000
+#define I915_OVERLAY_RGB15             0x3000
+#define I915_OVERLAY_YUV422            0x0100
+#define I915_OVERLAY_YUV411            0x0200
+#define I915_OVERLAY_YUV420            0x0300
+#define I915_OVERLAY_YUV410            0x0400
+
+#define I915_OVERLAY_SWAP_MASK         0xff0000
+#define I915_OVERLAY_NO_SWAP           0x000000
+#define I915_OVERLAY_UV_SWAP           0x010000
+#define I915_OVERLAY_Y_SWAP            0x020000
+#define I915_OVERLAY_Y_AND_UV_SWAP     0x030000
+
+#define I915_OVERLAY_FLAGS_MASK                0xff000000
+#define I915_OVERLAY_ENABLE            0x01000000
+
+struct drm_intel_overlay_put_image {
+       /* various flags and src format description */
+       uint32_t flags;
+       /* source picture description */
+       uint32_t bo_handle;
+       /* stride values and offsets are in bytes, buffer relative */
+       uint16_t stride_Y; /* stride for packed formats */
+       uint16_t stride_UV;
+       uint32_t offset_Y; /* offset for packet formats */
+       uint32_t offset_U;
+       uint32_t offset_V;
+       /* in pixels */
+       uint16_t src_width;
+       uint16_t src_height;
+       /* to compensate the scaling factors for partially covered surfaces */
+       uint16_t src_scan_width;
+       uint16_t src_scan_height;
+       /* output crtc description */
+       uint32_t crtc_id;
+       uint16_t dst_x;
+       uint16_t dst_y;
+       uint16_t dst_width;
+       uint16_t dst_height;
+};
+
+/* flags */
+#define I915_OVERLAY_UPDATE_ATTRS      (1<<0)
+#define I915_OVERLAY_UPDATE_GAMMA      (1<<1)
+struct drm_intel_overlay_attrs {
+       uint32_t flags;
+       uint32_t color_key;
+       int32_t brightness;
+       uint32_t contrast;
+       uint32_t saturation;
+       uint32_t gamma0;
+       uint32_t gamma1;
+       uint32_t gamma2;
+       uint32_t gamma3;
+       uint32_t gamma4;
+       uint32_t gamma5;
+};
+
 #endif                         /* _I915_DRM_H_ */