backend/gen_program.cpp
backend/gen_program.hpp
backend/gen_program.h
- backend/gen/brw_disasm.c
- backend/gen/brw_eu_emit.c
- backend/gen/brw_eu.c)
+ backend/gen/brw_eu_emit.cpp
+ backend/gen/brw_eu.cpp)
if (GBE_COMPILE_UTESTS)
set (GBE_SRC
+++ /dev/null
-/*
- * Copyright © 2012 Intel Corporation
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library. If not, see <http://www.gnu.org/licenses/>.
- *
- * Author: Benjamin Segovia <benjamin.segovia@intel.com>
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <getopt.h>
-#include <unistd.h>
-#include <stdarg.h>
-
-//#include "main/mtypes.h"
-//#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_structs.h"
-
-#include <stdint.h>
-
-static struct {
- char *name;
- int nsrc;
- int ndst;
-} opcode[128] = {
- [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
-
- [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
- [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
-
- [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
-
- [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
- [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
- [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
- [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
- [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
- [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
- [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
- [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
-};
-
-static char *conditional_modifier[16] = {
- [BRW_CONDITIONAL_NONE] = "",
- [BRW_CONDITIONAL_Z] = ".e",
- [BRW_CONDITIONAL_NZ] = ".ne",
- [BRW_CONDITIONAL_G] = ".g",
- [BRW_CONDITIONAL_GE] = ".ge",
- [BRW_CONDITIONAL_L] = ".l",
- [BRW_CONDITIONAL_LE] = ".le",
- [BRW_CONDITIONAL_R] = ".r",
- [BRW_CONDITIONAL_O] = ".o",
- [BRW_CONDITIONAL_U] = ".u",
-};
-
-static char *negate[2] = {
- [0] = "",
- [1] = "-",
-};
-
-static char *_abs[2] = {
- [0] = "",
- [1] = "(abs)",
-};
-
-static char *vert_stride[16] = {
- [0] = "0",
- [1] = "1",
- [2] = "2",
- [3] = "4",
- [4] = "8",
- [5] = "16",
- [6] = "32",
- [15] = "VxH",
-};
-
-static char *width[8] = {
- [0] = "1",
- [1] = "2",
- [2] = "4",
- [3] = "8",
- [4] = "16",
-};
-
-static char *horiz_stride[4] = {
- [0] = "0",
- [1] = "1",
- [2] = "2",
- [3] = "4"
-};
-
-static char *chan_sel[4] = {
- [0] = "x",
- [1] = "y",
- [2] = "z",
- [3] = "w",
-};
-
-static char *debug_ctrl[2] = {
- [0] = "",
- [1] = ".breakpoint"
-};
-
-static char *saturate[2] = {
- [0] = "",
- [1] = ".sat"
-};
-
-static char *accwr[2] = {
- [0] = "",
- [1] = "AccWrEnable"
-};
-
-static char *wectrl[2] = {
- [0] = "WE_normal",
- [1] = "WE_all"
-};
-
-static char *exec_size[8] = {
- [0] = "1",
- [1] = "2",
- [2] = "4",
- [3] = "8",
- [4] = "16",
- [5] = "32"
-};
-
-static char *pred_inv[2] = {
- [0] = "+",
- [1] = "-"
-};
-
-static char *pred_ctrl_align16[16] = {
- [1] = "",
- [2] = ".x",
- [3] = ".y",
- [4] = ".z",
- [5] = ".w",
- [6] = ".any4h",
- [7] = ".all4h",
-};
-
-static char *pred_ctrl_align1[16] = {
- [1] = "",
- [2] = ".anyv",
- [3] = ".allv",
- [4] = ".any2h",
- [5] = ".all2h",
- [6] = ".any4h",
- [7] = ".all4h",
- [8] = ".any8h",
- [9] = ".all8h",
- [10] = ".any16h",
- [11] = ".all16h",
-};
-
-static char *thread_ctrl[4] = {
- [0] = "",
- [2] = "switch"
-};
-
-static char *compr_ctrl[4] = {
- [0] = "",
- [1] = "sechalf",
- [2] = "compr",
- [3] = "compr4",
-};
-
-static char *dep_ctrl[4] = {
- [0] = "",
- [1] = "NoDDClr",
- [2] = "NoDDChk",
- [3] = "NoDDClr,NoDDChk",
-};
-
-static char *mask_ctrl[4] = {
- [0] = "",
- [1] = "nomask",
-};
-
-static char *access_mode[2] = {
- [0] = "align1",
- [1] = "align16",
-};
-
-static char *reg_encoding[8] = {
- [0] = "UD",
- [1] = "D",
- [2] = "UW",
- [3] = "W",
- [4] = "UB",
- [5] = "B",
- [7] = "F"
-};
-
-const int reg_type_size[8] = {
- [0] = 4,
- [1] = 4,
- [2] = 2,
- [3] = 2,
- [4] = 1,
- [5] = 1,
- [7] = 4
-};
-
-static char *reg_file[4] = {
- [0] = "A",
- [1] = "g",
- [2] = "m",
- [3] = "imm",
-};
-
-static char *writemask[16] = {
- [0x0] = ".",
- [0x1] = ".x",
- [0x2] = ".y",
- [0x3] = ".xy",
- [0x4] = ".z",
- [0x5] = ".xz",
- [0x6] = ".yz",
- [0x7] = ".xyz",
- [0x8] = ".w",
- [0x9] = ".xw",
- [0xa] = ".yw",
- [0xb] = ".xyw",
- [0xc] = ".zw",
- [0xd] = ".xzw",
- [0xe] = ".yzw",
- [0xf] = "",
-};
-
-static char *end_of_thread[2] = {
- [0] = "",
- [1] = "EOT"
-};
-
-static char *target_function[16] = {
- [BRW_SFID_NULL] = "null",
- [BRW_SFID_MATH] = "math",
- [BRW_SFID_SAMPLER] = "sampler",
- [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
- [BRW_SFID_DATAPORT_READ] = "read",
- [BRW_SFID_DATAPORT_WRITE] = "write",
- [BRW_SFID_URB] = "urb",
- [BRW_SFID_THREAD_SPAWNER] = "thread_spawner"
-};
-
-static char *target_function_gen6[16] = {
- [BRW_SFID_NULL] = "null",
- [BRW_SFID_MATH] = "math",
- [BRW_SFID_SAMPLER] = "sampler",
- [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
- [BRW_SFID_URB] = "urb",
- [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
- [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
- [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
- [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
- [GEN7_SFID_DATAPORT_DATA_CACHE] = "data"
-};
-
-static char *dp_rc_msg_type_gen6[16] = {
- [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
- [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
- [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
- [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
- [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
- [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
- [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
- [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
- [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
- [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
- [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
- [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
- [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
- [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
-};
-
-static char *math_function[16] = {
- [BRW_MATH_FUNCTION_INV] = "inv",
- [BRW_MATH_FUNCTION_LOG] = "log",
- [BRW_MATH_FUNCTION_EXP] = "exp",
- [BRW_MATH_FUNCTION_SQRT] = "sqrt",
- [BRW_MATH_FUNCTION_RSQ] = "rsq",
- [BRW_MATH_FUNCTION_SIN] = "sin",
- [BRW_MATH_FUNCTION_COS] = "cos",
- [BRW_MATH_FUNCTION_SINCOS] = "sincos",
- [BRW_MATH_FUNCTION_TAN] = "tan",
- [BRW_MATH_FUNCTION_POW] = "pow",
- [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
- [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
- [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
-};
-
-static char *math_saturate[2] = {
- [0] = "",
- [1] = "sat"
-};
-
-static char *math_signed[2] = {
- [0] = "",
- [1] = "signed"
-};
-
-static char *math_scalar[2] = {
- [0] = "",
- [1] = "scalar"
-};
-
-static char *math_precision[2] = {
- [0] = "",
- [1] = "partial_precision"
-};
-
-static char *urb_opcode[2] = {
- [0] = "urb_write",
- [1] = "ff_sync",
-};
-
-static char *urb_swizzle[4] = {
- [BRW_URB_SWIZZLE_NONE] = "",
- [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
- [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
-};
-
-static char *urb_allocate[2] = {
- [0] = "",
- [1] = "allocate"
-};
-
-static char *urb_used[2] = {
- [0] = "",
- [1] = "used"
-};
-
-static char *urb_complete[2] = {
- [0] = "",
- [1] = "complete"
-};
-
-static char *sampler_target_format[4] = {
- [0] = "F",
- [2] = "UD",
- [3] = "D"
-};
-
-
-static int column;
-
-static int string (FILE *file, char *string)
-{
- fputs (string, file);
- column += strlen (string);
- return 0;
-}
-
-static int format (FILE *f, char *format, ...)
-{
- char buf[1024];
- va_list args;
- va_start (args, format);
-
- vsnprintf (buf, sizeof (buf) - 1, format, args);
- va_end (args);
- string (f, buf);
- return 0;
-}
-
-static int newline (FILE *f)
-{
- putc ('\n', f);
- column = 0;
- return 0;
-}
-
-static int pad (FILE *f, int c)
-{
- do
- string (f, " ");
- while (column < c);
- return 0;
-}
-
-static int control (FILE *file, char *name, char *ctrl[], uint32_t id, int *space)
-{
- if (!ctrl[id]) {
- fprintf (file, "*** invalid %s value %d ",
- name, id);
- return 1;
- }
- if (ctrl[id][0])
- {
- if (space && *space)
- string (file, " ");
- string (file, ctrl[id]);
- if (space)
- *space = 1;
- }
- return 0;
-}
-
-static int print_opcode (FILE *file, int id)
-{
- if (!opcode[id].name) {
- format (file, "*** invalid opcode value %d ", id);
- return 1;
- }
- string (file, opcode[id].name);
- return 0;
-}
-
-static int reg (FILE *file, uint32_t _reg_file, uint32_t _reg_nr)
-{
- int err = 0;
-
- if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (_reg_nr & 0xf0) {
- case BRW_ARF_NULL:
- string (file, "null");
- return -1;
- case BRW_ARF_ADDRESS:
- format (file, "a%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_ACCUMULATOR:
- format (file, "acc%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_FLAG:
- format (file, "f%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_MASK:
- format (file, "mask%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_MASK_STACK:
- format (file, "msd%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_STATE:
- format (file, "sr%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_CONTROL:
- format (file, "cr%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_NOTIFICATION_COUNT:
- format (file, "n%d", _reg_nr & 0x0f);
- break;
- case BRW_ARF_IP:
- string (file, "ip");
- return -1;
- break;
- default:
- format (file, "ARF%d", _reg_nr);
- break;
- }
- } else {
- err |= control (file, "src reg file", reg_file, _reg_file, NULL);
- format (file, "%d", _reg_nr);
- }
- return err;
-}
-
-static int dest (FILE *file, struct brw_instruction *inst)
-{
- int err = 0;
-
- if (inst->header.access_mode == BRW_ALIGN_1)
- {
- if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
- {
- err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
- if (err == -1)
- return 0;
- if (inst->bits1.da1.dest_subreg_nr)
- format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
- reg_type_size[inst->bits1.da1.dest_reg_type]);
- format (file, "<%d>", inst->bits1.da1.dest_horiz_stride);
- err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
- }
- else
- {
- string (file, "g[a0");
- if (inst->bits1.ia1.dest_subreg_nr)
- format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
- reg_type_size[inst->bits1.ia1.dest_reg_type]);
- if (inst->bits1.ia1.dest_indirect_offset)
- format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
- string (file, "]");
- format (file, "<%d>", inst->bits1.ia1.dest_horiz_stride);
- err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL);
- }
- }
- else
- {
- if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
- {
- err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
- if (err == -1)
- return 0;
- if (inst->bits1.da16.dest_subreg_nr)
- format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
- reg_type_size[inst->bits1.da16.dest_reg_type]);
- string (file, "<1>");
- err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
- err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
- }
- else
- {
- err = 1;
- string (file, "Indirect align16 address mode not supported");
- }
- }
-
- return 0;
-}
-
-static int dest_3src (FILE *file, struct brw_instruction *inst)
-{
- int err = 0;
- uint32_t reg_file;
-
- reg_file = BRW_GENERAL_REGISTER_FILE;
-
- err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr);
- if (err == -1)
- return 0;
- if (inst->bits1.da3src.dest_subreg_nr)
- format (file, ".%d", inst->bits1.da3src.dest_subreg_nr);
- string (file, "<1>");
- err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
- err |= control (file, "dest reg encoding", reg_encoding, BRW_REGISTER_TYPE_F, NULL);
-
- return 0;
-}
-
-static int src_align1_region (FILE *file,
- uint32_t _vert_stride, uint32_t _width, uint32_t _horiz_stride)
-{
- int err = 0;
- string (file, "<");
- err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
- string (file, ",");
- err |= control (file, "width", width, _width, NULL);
- string (file, ",");
- err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
- string (file, ">");
- return err;
-}
-
-static int src_da1 (FILE *file, uint32_t type, uint32_t _reg_file,
- uint32_t _vert_stride, uint32_t _width, uint32_t _horiz_stride,
- uint32_t reg_num, uint32_t sub_reg_num, uint32_t __abs, uint32_t _negate)
-{
- int err = 0;
- err |= control (file, "negate", negate, _negate, NULL);
- err |= control (file, "abs", _abs, __abs, NULL);
-
- err |= reg (file, _reg_file, reg_num);
- if (err == -1)
- return 0;
- if (sub_reg_num)
- format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
- src_align1_region (file, _vert_stride, _width, _horiz_stride);
- err |= control (file, "src reg encoding", reg_encoding, type, NULL);
- return err;
-}
-
-static int src_ia1 (FILE *file,
- uint32_t type,
- uint32_t _reg_file,
- int _addr_imm,
- uint32_t _addr_subreg_nr,
- uint32_t _negate,
- uint32_t __abs,
- uint32_t _addr_mode,
- uint32_t _horiz_stride,
- uint32_t _width,
- uint32_t _vert_stride)
-{
- int err = 0;
- err |= control (file, "negate", negate, _negate, NULL);
- err |= control (file, "abs", _abs, __abs, NULL);
-
- string (file, "g[a0");
- if (_addr_subreg_nr)
- format (file, ".%d", _addr_subreg_nr);
- if (_addr_imm)
- format (file, " %d", _addr_imm);
- string (file, "]");
- src_align1_region (file, _vert_stride, _width, _horiz_stride);
- err |= control (file, "src reg encoding", reg_encoding, type, NULL);
- return err;
-}
-
-static int src_da16 (FILE *file,
- uint32_t _reg_type,
- uint32_t _reg_file,
- uint32_t _vert_stride,
- uint32_t _reg_nr,
- uint32_t _subreg_nr,
- uint32_t __abs,
- uint32_t _negate,
- uint32_t swz_x,
- uint32_t swz_y,
- uint32_t swz_z,
- uint32_t swz_w)
-{
- int err = 0;
- err |= control (file, "negate", negate, _negate, NULL);
- err |= control (file, "abs", _abs, __abs, NULL);
-
- err |= reg (file, _reg_file, _reg_nr);
- if (err == -1)
- return 0;
- if (_subreg_nr)
- /* bit4 for subreg number byte addressing. Make this same meaning as
- in da1 case, so output looks consistent. */
- format (file, ".%d", 16 / reg_type_size[_reg_type]);
- string (file, "<");
- err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
- string (file, ",4,1>");
- /*
- * Three kinds of swizzle display:
- * identity - nothing printed
- * 1->all - print the single channel
- * 1->1 - print the mapping
- */
- if (swz_x == BRW_CHANNEL_X &&
- swz_y == BRW_CHANNEL_Y &&
- swz_z == BRW_CHANNEL_Z &&
- swz_w == BRW_CHANNEL_W)
- {
- ;
- }
- else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- }
- else
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- err |= control (file, "channel select", chan_sel, swz_y, NULL);
- err |= control (file, "channel select", chan_sel, swz_z, NULL);
- err |= control (file, "channel select", chan_sel, swz_w, NULL);
- }
- err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
- return err;
-}
-
-static int src0_3src (FILE *file, struct brw_instruction *inst)
-{
- int err = 0;
- uint32_t swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
- uint32_t swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
- uint32_t swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
- uint32_t swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
-
- err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
- err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
-
- err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
- if (err == -1)
- return 0;
- if (inst->bits2.da3src.src0_subreg_nr)
- format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
- string (file, "<4,1,1>");
- err |= control (file, "src da16 reg type", reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
- /*
- * Three kinds of swizzle display:
- * identity - nothing printed
- * 1->all - print the single channel
- * 1->1 - print the mapping
- */
- if (swz_x == BRW_CHANNEL_X &&
- swz_y == BRW_CHANNEL_Y &&
- swz_z == BRW_CHANNEL_Z &&
- swz_w == BRW_CHANNEL_W)
- {
- ;
- }
- else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- }
- else
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- err |= control (file, "channel select", chan_sel, swz_y, NULL);
- err |= control (file, "channel select", chan_sel, swz_z, NULL);
- err |= control (file, "channel select", chan_sel, swz_w, NULL);
- }
- return err;
-}
-
-static int src1_3src (FILE *file, struct brw_instruction *inst)
-{
- int err = 0;
- uint32_t swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
- uint32_t swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
- uint32_t swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
- uint32_t swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
- uint32_t src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
- (inst->bits3.da3src.src1_subreg_nr_high << 2));
-
- err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
- NULL);
- err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL);
-
- err |= reg (file, BRW_GENERAL_REGISTER_FILE,
- inst->bits3.da3src.src1_reg_nr);
- if (err == -1)
- return 0;
- if (src1_subreg_nr)
- format (file, ".%d", src1_subreg_nr);
- string (file, "<4,1,1>");
- err |= control (file, "src da16 reg type", reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
- /*
- * Three kinds of swizzle display:
- * identity - nothing printed
- * 1->all - print the single channel
- * 1->1 - print the mapping
- */
- if (swz_x == BRW_CHANNEL_X &&
- swz_y == BRW_CHANNEL_Y &&
- swz_z == BRW_CHANNEL_Z &&
- swz_w == BRW_CHANNEL_W)
- {
- ;
- }
- else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- }
- else
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- err |= control (file, "channel select", chan_sel, swz_y, NULL);
- err |= control (file, "channel select", chan_sel, swz_z, NULL);
- err |= control (file, "channel select", chan_sel, swz_w, NULL);
- }
- return err;
-}
-
-
-static int src2_3src (FILE *file, struct brw_instruction *inst)
-{
- int err = 0;
- uint32_t swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
- uint32_t swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
- uint32_t swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
- uint32_t swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
-
- err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
- NULL);
- err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL);
-
- err |= reg (file, BRW_GENERAL_REGISTER_FILE,
- inst->bits3.da3src.src2_reg_nr);
- if (err == -1)
- return 0;
- if (inst->bits3.da3src.src2_subreg_nr)
- format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
- string (file, "<4,1,1>");
- err |= control (file, "src da16 reg type", reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
- /*
- * Three kinds of swizzle display:
- * identity - nothing printed
- * 1->all - print the single channel
- * 1->1 - print the mapping
- */
- if (swz_x == BRW_CHANNEL_X &&
- swz_y == BRW_CHANNEL_Y &&
- swz_z == BRW_CHANNEL_Z &&
- swz_w == BRW_CHANNEL_W)
- {
- ;
- }
- else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- }
- else
- {
- string (file, ".");
- err |= control (file, "channel select", chan_sel, swz_x, NULL);
- err |= control (file, "channel select", chan_sel, swz_y, NULL);
- err |= control (file, "channel select", chan_sel, swz_z, NULL);
- err |= control (file, "channel select", chan_sel, swz_w, NULL);
- }
- return err;
-}
-
-static int imm (FILE *file, uint32_t type, struct brw_instruction *inst) {
- switch (type) {
- case BRW_REGISTER_TYPE_UD:
- format (file, "0x%08xUD", inst->bits3.ud);
- break;
- case BRW_REGISTER_TYPE_D:
- format (file, "%dD", inst->bits3.d);
- break;
- case BRW_REGISTER_TYPE_UW:
- format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
- break;
- case BRW_REGISTER_TYPE_W:
- format (file, "%dW", (int16_t) inst->bits3.d);
- break;
- case BRW_REGISTER_TYPE_UB:
- format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
- break;
- case BRW_REGISTER_TYPE_VF:
- format (file, "Vector Float");
- break;
- case BRW_REGISTER_TYPE_V:
- format (file, "0x%08xV", inst->bits3.ud);
- break;
- case BRW_REGISTER_TYPE_F:
- format (file, "%-gF", inst->bits3.f);
- }
- return 0;
-}
-
-static int src0 (FILE *file, struct brw_instruction *inst)
-{
- if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
- return imm (file, inst->bits1.da1.src0_reg_type,
- inst);
- else if (inst->header.access_mode == BRW_ALIGN_1)
- {
- if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
- {
- return src_da1 (file,
- inst->bits1.da1.src0_reg_type,
- inst->bits1.da1.src0_reg_file,
- inst->bits2.da1.src0_vert_stride,
- inst->bits2.da1.src0_width,
- inst->bits2.da1.src0_horiz_stride,
- inst->bits2.da1.src0_reg_nr,
- inst->bits2.da1.src0_subreg_nr,
- inst->bits2.da1.src0_abs,
- inst->bits2.da1.src0_negate);
- }
- else
- {
- return src_ia1 (file,
- inst->bits1.ia1.src0_reg_type,
- inst->bits1.ia1.src0_reg_file,
- inst->bits2.ia1.src0_indirect_offset,
- inst->bits2.ia1.src0_subreg_nr,
- inst->bits2.ia1.src0_negate,
- inst->bits2.ia1.src0_abs,
- inst->bits2.ia1.src0_address_mode,
- inst->bits2.ia1.src0_horiz_stride,
- inst->bits2.ia1.src0_width,
- inst->bits2.ia1.src0_vert_stride);
- }
- }
- else
- {
- if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
- {
- return src_da16 (file,
- inst->bits1.da16.src0_reg_type,
- inst->bits1.da16.src0_reg_file,
- inst->bits2.da16.src0_vert_stride,
- inst->bits2.da16.src0_reg_nr,
- inst->bits2.da16.src0_subreg_nr,
- inst->bits2.da16.src0_abs,
- inst->bits2.da16.src0_negate,
- inst->bits2.da16.src0_swz_x,
- inst->bits2.da16.src0_swz_y,
- inst->bits2.da16.src0_swz_z,
- inst->bits2.da16.src0_swz_w);
- }
- else
- {
- string (file, "Indirect align16 address mode not supported");
- return 1;
- }
- }
-}
-
-static int src1 (FILE *file, struct brw_instruction *inst)
-{
- if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
- return imm (file, inst->bits1.da1.src1_reg_type,
- inst);
- else if (inst->header.access_mode == BRW_ALIGN_1)
- {
- if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
- {
- return src_da1 (file,
- inst->bits1.da1.src1_reg_type,
- inst->bits1.da1.src1_reg_file,
- inst->bits3.da1.src1_vert_stride,
- inst->bits3.da1.src1_width,
- inst->bits3.da1.src1_horiz_stride,
- inst->bits3.da1.src1_reg_nr,
- inst->bits3.da1.src1_subreg_nr,
- inst->bits3.da1.src1_abs,
- inst->bits3.da1.src1_negate);
- }
- else
- {
- return src_ia1 (file,
- inst->bits1.ia1.src1_reg_type,
- inst->bits1.ia1.src1_reg_file,
- inst->bits3.ia1.src1_indirect_offset,
- inst->bits3.ia1.src1_subreg_nr,
- inst->bits3.ia1.src1_negate,
- inst->bits3.ia1.src1_abs,
- inst->bits3.ia1.src1_address_mode,
- inst->bits3.ia1.src1_horiz_stride,
- inst->bits3.ia1.src1_width,
- inst->bits3.ia1.src1_vert_stride);
- }
- }
- else
- {
- if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
- {
- return src_da16 (file,
- inst->bits1.da16.src1_reg_type,
- inst->bits1.da16.src1_reg_file,
- inst->bits3.da16.src1_vert_stride,
- inst->bits3.da16.src1_reg_nr,
- inst->bits3.da16.src1_subreg_nr,
- inst->bits3.da16.src1_abs,
- inst->bits3.da16.src1_negate,
- inst->bits3.da16.src1_swz_x,
- inst->bits3.da16.src1_swz_y,
- inst->bits3.da16.src1_swz_z,
- inst->bits3.da16.src1_swz_w);
- }
- else
- {
- string (file, "Indirect align16 address mode not supported");
- return 1;
- }
- }
-}
-
-int esize[6] = {
- [0] = 1,
- [1] = 2,
- [2] = 4,
- [3] = 8,
- [4] = 16,
- [5] = 32,
-};
-
-static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
-{
- int qtr_ctl = inst->header.compression_control;
- int exec_size = esize[inst->header.execution_size];
-
- if (exec_size == 8) {
- switch (qtr_ctl) {
- case 0:
- string (file, " 1Q");
- break;
- case 1:
- string (file, " 2Q");
- break;
- case 2:
- string (file, " 3Q");
- break;
- case 3:
- string (file, " 4Q");
- break;
- }
- } else if (exec_size == 16){
- if (qtr_ctl < 2)
- string (file, " 1H");
- else
- string (file, " 2H");
- }
- return 0;
-}
-
-int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
-{
- int err = 0;
- int space = 0;
-
- if (inst->header.predicate_control) {
- string (file, "(");
- err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
- string (file, "f0");
- if (inst->bits2.da1.flag_reg_nr)
- format (file, ".%d", inst->bits2.da1.flag_reg_nr);
- if (inst->header.access_mode == BRW_ALIGN_1)
- err |= control (file, "predicate control align1", pred_ctrl_align1,
- inst->header.predicate_control, NULL);
- else
- err |= control (file, "predicate control align16", pred_ctrl_align16,
- inst->header.predicate_control, NULL);
- string (file, ") ");
- }
-
- err |= print_opcode (file, inst->header.opcode);
- err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
- err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
-
- if (inst->header.opcode == BRW_OPCODE_MATH) {
- string (file, " ");
- err |= control (file, "function", math_function,
- inst->header.destreg__conditionalmod, NULL);
- } else if (inst->header.opcode != BRW_OPCODE_SEND &&
- inst->header.opcode != BRW_OPCODE_SENDC)
- err |= control (file, "conditional modifier", conditional_modifier,
- inst->header.destreg__conditionalmod, NULL);
-
- if (inst->header.opcode != BRW_OPCODE_NOP) {
- string (file, "(");
- err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
- string (file, ")");
- }
-
- if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
- format (file, " %d", inst->header.destreg__conditionalmod);
-
- if (opcode[inst->header.opcode].nsrc == 3) {
- pad (file, 16);
- err |= dest_3src (file, inst);
-
- pad (file, 32);
- err |= src0_3src (file, inst);
-
- pad (file, 48);
- err |= src1_3src (file, inst);
-
- pad (file, 64);
- err |= src2_3src (file, inst);
- } else {
- if (opcode[inst->header.opcode].ndst > 0) {
- pad (file, 16);
- err |= dest (file, inst);
- } else if (gen >= 6 && (inst->header.opcode == BRW_OPCODE_IF ||
- inst->header.opcode == BRW_OPCODE_ELSE ||
- inst->header.opcode == BRW_OPCODE_ENDIF ||
- inst->header.opcode == BRW_OPCODE_WHILE)) {
- format (file, " %d", inst->bits1.branch_gen6.jump_count);
- } else if (gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
- inst->header.opcode == BRW_OPCODE_CONTINUE ||
- inst->header.opcode == BRW_OPCODE_HALT)) {
- format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip);
- } else if (inst->header.opcode == BRW_OPCODE_JMPI) {
- format (file, " %d", inst->bits3.d);
- }
-
- if (opcode[inst->header.opcode].nsrc > 0) {
- pad (file, 32);
- err |= src0 (file, inst);
- }
- if (opcode[inst->header.opcode].nsrc > 1) {
- pad (file, 48);
- err |= src1 (file, inst);
- }
- }
-
- if (inst->header.opcode == BRW_OPCODE_SEND ||
- inst->header.opcode == BRW_OPCODE_SENDC) {
- enum brw_message_target target;
-
- if (gen >= 6)
- target = inst->header.destreg__conditionalmod;
- else if (gen == 5)
- target = inst->bits2.send_gen5.sfid;
- else
- target = inst->bits3.generic.msg_target;
-
- newline (file);
- pad (file, 16);
- space = 0;
-
- if (gen >= 6) {
- err |= control (file, "target function", target_function_gen6,
- target, &space);
- } else {
- err |= control (file, "target function", target_function,
- target, &space);
- }
-
- switch (target) {
- case BRW_SFID_MATH:
- err |= control (file, "math function", math_function,
- inst->bits3.math.function, &space);
- err |= control (file, "math saturate", math_saturate,
- inst->bits3.math.saturate, &space);
- err |= control (file, "math signed", math_signed,
- inst->bits3.math.int_type, &space);
- err |= control (file, "math scalar", math_scalar,
- inst->bits3.math.data_type, &space);
- err |= control (file, "math precision", math_precision,
- inst->bits3.math.precision, &space);
- break;
- case BRW_SFID_SAMPLER:
- if (gen >= 7) {
- format (file, " (%d, %d, %d, %d)",
- inst->bits3.sampler_gen7.binding_table_index,
- inst->bits3.sampler_gen7.sampler,
- inst->bits3.sampler_gen7.msg_type,
- inst->bits3.sampler_gen7.simd_mode);
- } else if (gen >= 5) {
- format (file, " (%d, %d, %d, %d)",
- inst->bits3.sampler_gen5.binding_table_index,
- inst->bits3.sampler_gen5.sampler,
- inst->bits3.sampler_gen5.msg_type,
- inst->bits3.sampler_gen5.simd_mode);
- } else if (0 /* FINISHME: is_g4x */) {
- format (file, " (%d, %d)",
- inst->bits3.sampler_g4x.binding_table_index,
- inst->bits3.sampler_g4x.sampler);
- } else {
- format (file, " (%d, %d, ",
- inst->bits3.sampler.binding_table_index,
- inst->bits3.sampler.sampler);
- err |= control (file, "sampler target format",
- sampler_target_format,
- inst->bits3.sampler.return_format, NULL);
- string (file, ")");
- }
- break;
- case BRW_SFID_DATAPORT_READ:
- if (gen >= 6) {
- format (file, " (%d, %d, %d, %d)",
- inst->bits3.gen6_dp.binding_table_index,
- inst->bits3.gen6_dp.msg_control,
- inst->bits3.gen6_dp.msg_type,
- inst->bits3.gen6_dp.send_commit_msg);
- } else if (gen >= 5 /* FINISHME: || is_g4x */) {
- format (file, " (%d, %d, %d)",
- inst->bits3.dp_read_gen5.binding_table_index,
- inst->bits3.dp_read_gen5.msg_control,
- inst->bits3.dp_read_gen5.msg_type);
- } else {
- format (file, " (%d, %d, %d)",
- inst->bits3.dp_read.binding_table_index,
- inst->bits3.dp_read.msg_control,
- inst->bits3.dp_read.msg_type);
- }
- break;
-
- case BRW_SFID_DATAPORT_WRITE:
- if (gen >= 7) {
- format (file, " (");
-
- err |= control (file, "DP rc message type",
- dp_rc_msg_type_gen6,
- inst->bits3.gen7_dp.msg_type, &space);
-
- format (file, ", %d, %d, %d)",
- inst->bits3.gen7_dp.binding_table_index,
- inst->bits3.gen7_dp.msg_control,
- inst->bits3.gen7_dp.msg_type);
- } else if (gen == 6) {
- format (file, " (");
-
- err |= control (file, "DP rc message type",
- dp_rc_msg_type_gen6,
- inst->bits3.gen6_dp.msg_type, &space);
-
- format (file, ", %d, %d, %d, %d)",
- inst->bits3.gen6_dp.binding_table_index,
- inst->bits3.gen6_dp.msg_control,
- inst->bits3.gen6_dp.msg_type,
- inst->bits3.gen6_dp.send_commit_msg);
- } else {
- format (file, " (%d, %d, %d, %d)",
- inst->bits3.dp_write.binding_table_index,
- (inst->bits3.dp_write.last_render_target << 3) |
- inst->bits3.dp_write.msg_control,
- inst->bits3.dp_write.msg_type,
- inst->bits3.dp_write.send_commit_msg);
- }
- break;
-
- case BRW_SFID_URB:
- if (gen >= 5) {
- format (file, " %d", inst->bits3.urb_gen5.offset);
- } else {
- format (file, " %d", inst->bits3.urb.offset);
- }
-
- space = 1;
- if (gen >= 5) {
- err |= control (file, "urb opcode", urb_opcode,
- inst->bits3.urb_gen5.opcode, &space);
- }
- err |= control (file, "urb swizzle", urb_swizzle,
- inst->bits3.urb.swizzle_control, &space);
- err |= control (file, "urb allocate", urb_allocate,
- inst->bits3.urb.allocate, &space);
- err |= control (file, "urb used", urb_used,
- inst->bits3.urb.used, &space);
- err |= control (file, "urb complete", urb_complete,
- inst->bits3.urb.complete, &space);
- break;
- case BRW_SFID_THREAD_SPAWNER:
- break;
- case GEN7_SFID_DATAPORT_DATA_CACHE:
- format (file, " (%d, %d, %d)",
- inst->bits3.gen7_dp.binding_table_index,
- inst->bits3.gen7_dp.msg_control,
- inst->bits3.gen7_dp.msg_type);
- break;
-
-
- default:
- format (file, "unsupported target %d", target);
- break;
- }
- if (space)
- string (file, " ");
- if (gen >= 5) {
- format (file, "mlen %d",
- inst->bits3.generic_gen5.msg_length);
- format (file, " rlen %d",
- inst->bits3.generic_gen5.response_length);
- } else {
- format (file, "mlen %d",
- inst->bits3.generic.msg_length);
- format (file, " rlen %d",
- inst->bits3.generic.response_length);
- }
- }
- pad (file, 64);
- if (inst->header.opcode != BRW_OPCODE_NOP) {
- string (file, "{");
- space = 1;
- err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
- if (gen >= 6)
- err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
- else
- err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
- err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
-
- if (gen >= 6)
- err |= qtr_ctrl (file, inst);
- else {
- err |= control (file, "compression control", compr_ctrl,
- inst->header.compression_control, &space);
- }
-
- err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
- if (gen >= 6)
- err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
- if (inst->header.opcode == BRW_OPCODE_SEND ||
- inst->header.opcode == BRW_OPCODE_SENDC)
- err |= control (file, "end of thread", end_of_thread,
- inst->bits3.generic.end_of_thread, &space);
- if (space)
- string (file, " ");
- string (file, "}");
- }
- string (file, ";");
- newline (file);
- return err;
-}
+++ /dev/null
-/*
- * Copyright © 2012 Intel Corporation
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library. If not, see <http://www.gnu.org/licenses/>.
- *
- * Author: Benjamin Segovia <benjamin.segovia@intel.com>
- */
-
- /*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-
-// #include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_eu.h"
-
-#include <stdlib.h>
-#include <assert.h>
-#include <string.h>
-
-// #include "glsl/ralloc.h"
-
-/* Returns the corresponding conditional mod for swapping src0 and
- * src1 in e.g. CMP.
- */
-uint32_t
-brw_swap_cmod(uint32_t cmod)
-{
- switch (cmod) {
- case BRW_CONDITIONAL_Z:
- case BRW_CONDITIONAL_NZ:
- return cmod;
- case BRW_CONDITIONAL_G:
- return BRW_CONDITIONAL_LE;
- case BRW_CONDITIONAL_GE:
- return BRW_CONDITIONAL_L;
- case BRW_CONDITIONAL_L:
- return BRW_CONDITIONAL_GE;
- case BRW_CONDITIONAL_LE:
- return BRW_CONDITIONAL_G;
- default:
- return ~0;
- }
-}
-
-
-/* How does predicate control work when execution_size != 8? Do I
- * need to test/set for 0xffff when execution_size is 16?
- */
-void brw_set_predicate_control_flag_value(struct brw_compile *p, uint32_t value)
-{
-// p->current->header.predicate_control = BRW_PREDICATE_NONE;
-
- if (value != 0xff) {
- if (value != p->flag_value) {
- brw_push_insn_state(p);
- brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
- p->flag_value = value;
- brw_pop_insn_state(p);
- }
-
-// p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
- }
-}
-
-void brw_set_predicate_control(struct brw_compile *p, uint32_t pc)
-{
- // p->current->header.predicate_control = pc;
-}
-
-void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
-{
- // p->current->header.predicate_inverse = predicate_inverse;
-}
-
-void brw_set_conditionalmod(struct brw_compile *p, uint32_t conditional)
-{
- // p->current->header.destreg__conditionalmod = conditional;
-}
-
-void brw_set_access_mode(struct brw_compile *p, uint32_t access_mode)
-{
- // p->current->header.access_mode = access_mode;
-}
-
-void
-brw_set_compression_control(struct brw_compile *p,
- enum brw_compression compression_control)
-{
-#if 0
- p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
-
- if (p->gen >= 6) {
- /* Since we don't use the 32-wide support in gen6, we translate
- * the pre-gen6 compression control here.
- */
- switch (compression_control) {
- case BRW_COMPRESSION_NONE:
- /* This is the "use the first set of bits of dmask/vmask/arf
- * according to execsize" option.
- */
- p->current->header.compression_control = GEN6_COMPRESSION_1Q;
- break;
- case BRW_COMPRESSION_2NDHALF:
- /* For 8-wide, this is "use the second set of 8 bits." */
- p->current->header.compression_control = GEN6_COMPRESSION_2Q;
- break;
- case BRW_COMPRESSION_COMPRESSED:
- /* For 16-wide instruction compression, use the first set of 16 bits
- * since we don't do 32-wide dispatch.
- */
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
- break;
- default:
- assert(!"not reached");
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
- break;
- }
- } else {
- p->current->header.compression_control = compression_control;
- }
-#endif
-}
-
--- /dev/null
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Benjamin Segovia <benjamin.segovia@intel.com>
+ */
+
+ /*
+ * Authors:
+ * Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+
+// #include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_eu.h"
+
+#include <stdlib.h>
+#include <assert.h>
+#include <string.h>
+
+// #include "glsl/ralloc.h"
+
} dw1;
};
-
struct brw_indirect {
uint32_t addr_subnr:4;
int addr_offset:10;
#define BRW_MAX_INSTRUCTION_NUM 8192
struct brw_compile {
int gen;
- struct brw_instruction store[8192];
+ brw_instruction store[8192];
int store_size;
uint32_t nr_insn;
/* Allow clients to push/pop instruction state */
- struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
+ brw_instruction stack[BRW_EU_MAX_INSN_STACK];
bool compressed_stack[BRW_EU_MAX_INSN_STACK];
uint32_t flag_value;
bool single_program_flow;
bool compressed;
struct brw_context *brw;
-};
-void
-brw_save_label(struct brw_compile *c, const char *name, uint32_t position);
+ inline brw_instruction *current_insn(void) { return &this->store[this->nr_insn]; }
+
+ void guess_execution_size(brw_instruction *insn, brw_reg reg);
+ void brw_set_mask_control(uint32_t value);
+ void brw_set_saturate(uint32_t value);
+ void brw_set_access_mode(uint32_t access_mode);
+ void brw_set_compression_control(enum brw_compression c);
+ void brw_set_predicate_control_flag_value(uint32_t value);
+ void brw_set_predicate_control(uint32_t pc);
+ void brw_set_predicate_inverse(bool predicate_inverse);
+ void brw_set_conditionalmod(uint32_t conditional);
+ void brw_set_acc_write_control(uint32_t value);
+
+ void brw_init_compile(struct brw_context *, void *mem_ctx);
+ const uint32_t *brw_get_program(uint32_t *sz);
+
+ brw_instruction *brw_next_insn(uint32_t opcode);
+ void brw_set_dest(brw_instruction *insn, brw_reg dest);
+ void brw_set_src0(brw_instruction *insn, brw_reg reg);
+ void gen6_resolve_implied_move(brw_reg *src, uint32_t msg_reg_nr);
+
+#define ALU1(OP) \
+ brw_instruction *brw_##OP(brw_reg dest, brw_reg src0);
+
+#define ALU2(OP) \
+ brw_instruction *brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1);
+
+#define ALU3(OP) \
+ brw_instruction *brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1, brw_reg src2);
+
+#define ROUND(OP) \
+ void brw_##OP(brw_reg dest, brw_reg src0);
+
+ ALU1(MOV)
+ ALU2(SEL)
+ ALU1(NOT)
+ ALU2(AND)
+ ALU2(OR)
+ ALU2(XOR)
+ ALU2(SHR)
+ ALU2(SHL)
+ ALU2(RSR)
+ ALU2(RSL)
+ ALU2(ASR)
+ ALU2(JMPI)
+ ALU2(ADD)
+ ALU2(MUL)
+ ALU1(FRC)
+ ALU1(RNDD)
+ ALU2(MAC)
+ ALU2(MACH)
+ ALU1(LZD)
+ ALU2(DP4)
+ ALU2(DPH)
+ ALU2(DP3)
+ ALU2(DP2)
+ ALU2(LINE)
+ ALU2(PLN)
+ ALU3(MAD)
+
+ ROUND(RNDZ)
+ ROUND(RNDE)
+
+#undef ALU1
+#undef ALU2
+#undef ALU3
+#undef ROUND
+
+ /* Helpers for SEND instruction */
+ void brw_set_sampler_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t sampler,
+ uint32_t msg_type,
+ uint32_t response_length,
+ uint32_t msg_length,
+ uint32_t header_present,
+ uint32_t simd_mode,
+ uint32_t return_format);
+
+ void brw_set_dp_read_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t msg_control,
+ uint32_t msg_type,
+ uint32_t target_cache,
+ uint32_t msg_length,
+ uint32_t response_length);
+
+ void brw_set_dp_write_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t msg_control,
+ uint32_t msg_type,
+ uint32_t msg_length,
+ bool header_present,
+ uint32_t last_render_target,
+ uint32_t response_length,
+ uint32_t end_of_thread,
+ uint32_t send_commit_msg);
+
+ void brw_SAMPLE(brw_reg dest,
+ uint32_t msg_reg_nr,
+ brw_reg src0,
+ uint32_t binding_table_index,
+ uint32_t sampler,
+ uint32_t writemask,
+ uint32_t msg_type,
+ uint32_t response_length,
+ uint32_t msg_length,
+ uint32_t header_present,
+ uint32_t simd_mode,
+ uint32_t return_format);
+
+ void brw_math_16(brw_reg dest,
+ uint32_t function,
+ uint32_t saturate,
+ uint32_t msg_reg_nr,
+ brw_reg src,
+ uint32_t precision);
+
+ void brw_math(brw_reg dest,
+ uint32_t function,
+ uint32_t saturate,
+ uint32_t msg_reg_nr,
+ brw_reg src,
+ uint32_t data_type,
+ uint32_t precision);
+
+ void brw_math2(brw_reg dest, uint32_t function, brw_reg src0, brw_reg src1);
+ void brw_EOT(uint32_t msg_nr);
-void
-brw_save_call(struct brw_compile *c, const char *name, uint32_t call_pos);
+ void brw_dword_scattered_read(brw_reg dest, brw_reg mrf, uint32_t bind_table_index);
-void
-brw_resolve_cals(struct brw_compile *c);
+ void brw_land_fwd_jump(int jmp_insn_idx);
+ void brw_NOP(void);
+ void brw_WAIT(void);
+
+ void brw_CMP(brw_reg dest, uint32_t conditional, brw_reg src0, brw_reg src1);
+ void brw_copy_indirect_to_indirect(brw_indirect dst_ptr, brw_indirect src_ptr, uint32_t count);
+ void brw_copy_from_indirect(brw_reg dst, brw_indirect ptr, uint32_t count);
+ void brw_copy4(brw_reg dst, brw_reg src, uint32_t count);
+ void brw_copy8(brw_reg dst, brw_reg src, uint32_t count);
+ void brw_math_invert(brw_reg dst, brw_reg src);
+ void brw_set_src1(brw_instruction *insn, brw_reg reg);
+ void brw_set_uip_jip(void);
+};
+
+void brw_print_reg(brw_reg reg);
static inline int type_sz(uint32_t type)
{
* \param swizzle one of BRW_SWIZZLE_x
* \param writemask WRITEMASK_X/Y/Z/W bitfield
*/
-static inline struct brw_reg brw_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr,
- uint32_t type,
- uint32_t vstride,
- uint32_t width,
- uint32_t hstride,
- uint32_t swizzle,
- uint32_t writemask)
+static inline brw_reg make_brw_reg(uint32_t file,
+ uint32_t nr,
+ uint32_t subnr,
+ uint32_t type,
+ uint32_t vstride,
+ uint32_t width,
+ uint32_t hstride,
+ uint32_t swizzle,
+ uint32_t writemask)
{
struct brw_reg reg;
if (file == BRW_GENERAL_REGISTER_FILE)
}
/** Construct float[16] register */
-static inline struct brw_reg brw_vec16_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static inline brw_reg brw_vec16_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return brw_reg(file,
- nr,
- subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_16,
- BRW_WIDTH_16,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
- WRITEMASK_XYZW);
+ return make_brw_reg(file,
+ nr,
+ subnr,
+ BRW_REGISTER_TYPE_F,
+ BRW_VERTICAL_STRIDE_16,
+ BRW_WIDTH_16,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
}
/** Construct float[8] register */
-static inline struct brw_reg brw_vec8_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static inline brw_reg brw_vec8_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return brw_reg(file,
- nr,
- subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_8,
- BRW_WIDTH_8,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
- WRITEMASK_XYZW);
+ return make_brw_reg(file,
+ nr,
+ subnr,
+ BRW_REGISTER_TYPE_F,
+ BRW_VERTICAL_STRIDE_8,
+ BRW_WIDTH_8,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
}
/** Construct float[4] register */
-static inline struct brw_reg brw_vec4_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static inline brw_reg brw_vec4_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return brw_reg(file,
- nr,
- subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_4,
- BRW_WIDTH_4,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
- WRITEMASK_XYZW);
+ return make_brw_reg(file,
+ nr,
+ subnr,
+ BRW_REGISTER_TYPE_F,
+ BRW_VERTICAL_STRIDE_4,
+ BRW_WIDTH_4,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
}
/** Construct float[2] register */
-static inline struct brw_reg brw_vec2_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static inline brw_reg brw_vec2_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return brw_reg(file,
- nr,
- subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_2,
- BRW_WIDTH_2,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYXY,
- WRITEMASK_XY);
+ return make_brw_reg(file,
+ nr,
+ subnr,
+ BRW_REGISTER_TYPE_F,
+ BRW_VERTICAL_STRIDE_2,
+ BRW_WIDTH_2,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYXY,
+ WRITEMASK_XY);
}
/** Construct float[1] register */
-static inline struct brw_reg brw_vec1_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static inline brw_reg brw_vec1_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return brw_reg(file,
- nr,
- subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XXXX,
- WRITEMASK_X);
+ return make_brw_reg(file,
+ nr,
+ subnr,
+ BRW_REGISTER_TYPE_F,
+ BRW_VERTICAL_STRIDE_0,
+ BRW_WIDTH_1,
+ BRW_HORIZONTAL_STRIDE_0,
+ BRW_SWIZZLE_XXXX,
+ WRITEMASK_X);
}
-static inline struct brw_reg retype(struct brw_reg reg, uint32_t type)
+static inline brw_reg retype(brw_reg reg, uint32_t type)
{
reg.type = type;
return reg;
}
-static inline struct brw_reg sechalf(struct brw_reg reg)
+static inline brw_reg sechalf(brw_reg reg)
{
if (reg.vstride)
reg.nr++;
return reg;
}
-static inline struct brw_reg suboffset(struct brw_reg reg, uint32_t delta)
+static inline brw_reg suboffset(brw_reg reg, uint32_t delta)
{
reg.subnr += delta * type_sz(reg.type);
return reg;
}
-static inline struct brw_reg offset(struct brw_reg reg, uint32_t delta)
+static inline brw_reg offset(brw_reg reg, uint32_t delta)
{
reg.nr += delta;
return reg;
}
-static inline struct brw_reg byte_offset(struct brw_reg reg, uint32_t bytes)
+static inline brw_reg byte_offset(brw_reg reg, uint32_t bytes)
{
uint32_t newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
reg.nr = newoffset / REG_SIZE;
/** Construct unsigned word[16] register */
-static inline struct brw_reg brw_uw16_reg(uint32_t file,
+static inline brw_reg brw_uw16_reg(uint32_t file,
uint32_t nr,
uint32_t subnr)
{
}
/** Construct unsigned word[8] register */
-static inline struct brw_reg brw_uw8_reg(uint32_t file,
+static inline brw_reg brw_uw8_reg(uint32_t file,
uint32_t nr,
uint32_t subnr)
{
}
/** Construct unsigned word[1] register */
-static inline struct brw_reg brw_uw1_reg(uint32_t file,
+static inline brw_reg brw_uw1_reg(uint32_t file,
uint32_t nr,
uint32_t subnr)
{
return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
}
-static inline struct brw_reg brw_imm_reg(uint32_t type)
+static inline brw_reg brw_imm_reg(uint32_t type)
{
- return brw_reg(BRW_IMMEDIATE_VALUE,
- 0,
- 0,
- type,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- 0,
- 0);
+ return make_brw_reg(BRW_IMMEDIATE_VALUE,
+ 0,
+ 0,
+ type,
+ BRW_VERTICAL_STRIDE_0,
+ BRW_WIDTH_1,
+ BRW_HORIZONTAL_STRIDE_0,
+ 0,
+ 0);
}
/** Construct float immediate register */
-static inline struct brw_reg brw_imm_f(float f)
+static inline brw_reg brw_imm_f(float f)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
imm.dw1.f = f;
return imm;
}
/** Construct integer immediate register */
-static inline struct brw_reg brw_imm_d(int d)
+static inline brw_reg brw_imm_d(int d)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
imm.dw1.d = d;
return imm;
}
/** Construct uint immediate register */
-static inline struct brw_reg brw_imm_ud(uint32_t ud)
+static inline brw_reg brw_imm_ud(uint32_t ud)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
imm.dw1.ud = ud;
return imm;
}
/** Construct ushort immediate register */
-static inline struct brw_reg brw_imm_uw(uint16_t uw)
+static inline brw_reg brw_imm_uw(uint16_t uw)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
imm.dw1.ud = uw | (uw << 16);
return imm;
}
/** Construct short immediate register */
-static inline struct brw_reg brw_imm_w(short w)
+static inline brw_reg brw_imm_w(short w)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
imm.dw1.d = w | (w << 16);
return imm;
}
*/
/** Construct vector of eight signed half-byte values */
-static inline struct brw_reg brw_imm_v(uint32_t v)
+static inline brw_reg brw_imm_v(uint32_t v)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_8;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
}
/** Construct vector of four 8-bit float values */
-static inline struct brw_reg brw_imm_vf(uint32_t v)
+static inline brw_reg brw_imm_vf(uint32_t v)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_4;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
#define VF_ONE 0x30
#define VF_NEG (1<<7)
-static inline struct brw_reg brw_imm_vf4(uint32_t v0,
+static inline brw_reg brw_imm_vf4(uint32_t v0,
uint32_t v1,
uint32_t v2,
uint32_t v3)
{
- struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
+ brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_4;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
return imm;
}
-
-static inline struct brw_reg brw_address(struct brw_reg reg)
+static inline brw_reg brw_address(brw_reg reg)
{
return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
}
/** Construct float[1] general-purpose register */
-static inline struct brw_reg brw_vec1_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_vec1_grf(uint32_t nr, uint32_t subnr)
{
return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[2] general-purpose register */
-static inline struct brw_reg brw_vec2_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_vec2_grf(uint32_t nr, uint32_t subnr)
{
return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[4] general-purpose register */
-static inline struct brw_reg brw_vec4_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_vec4_grf(uint32_t nr, uint32_t subnr)
{
return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[8] general-purpose register */
-static inline struct brw_reg brw_vec8_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_vec8_grf(uint32_t nr, uint32_t subnr)
{
return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
-
-static inline struct brw_reg brw_uw8_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_uw8_grf(uint32_t nr, uint32_t subnr)
{
return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
-static inline struct brw_reg brw_uw16_grf(uint32_t nr, uint32_t subnr)
+static inline brw_reg brw_uw16_grf(uint32_t nr, uint32_t subnr)
{
return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct null register (usually used for setting condition codes) */
-static inline struct brw_reg brw_null_reg(void)
+static inline brw_reg brw_null_reg(void)
{
return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_NULL,
0);
}
-static inline struct brw_reg brw_address_reg(uint32_t subnr)
+static inline brw_reg brw_address_reg(uint32_t subnr)
{
return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_ADDRESS,
* aren't xyzw. This goes against the convention for other scalar
* regs:
*/
-static inline struct brw_reg brw_ip_reg(void)
+static inline brw_reg brw_ip_reg(void)
{
- return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_IP,
- 0,
- BRW_REGISTER_TYPE_UD,
- BRW_VERTICAL_STRIDE_4, /* ? */
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XYZW, /* NOTE! */
- WRITEMASK_XYZW); /* NOTE! */
+ return make_brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
+ BRW_ARF_IP,
+ 0,
+ BRW_REGISTER_TYPE_UD,
+ BRW_VERTICAL_STRIDE_4, /* ? */
+ BRW_WIDTH_1,
+ BRW_HORIZONTAL_STRIDE_0,
+ BRW_SWIZZLE_XYZW, /* NOTE! */
+ WRITEMASK_XYZW); /* NOTE! */
}
-static inline struct brw_reg brw_acc_reg(void)
+static inline brw_reg brw_acc_reg(void)
{
return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_ACCUMULATOR,
0);
}
-static inline struct brw_reg brw_notification_1_reg(void)
+static inline brw_reg brw_notification_1_reg(void)
{
- return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_NOTIFICATION_COUNT,
- 1,
- BRW_REGISTER_TYPE_UD,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XXXX,
- WRITEMASK_X);
+ return make_brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
+ BRW_ARF_NOTIFICATION_COUNT,
+ 1,
+ BRW_REGISTER_TYPE_UD,
+ BRW_VERTICAL_STRIDE_0,
+ BRW_WIDTH_1,
+ BRW_HORIZONTAL_STRIDE_0,
+ BRW_SWIZZLE_XXXX,
+ WRITEMASK_X);
}
-static inline struct brw_reg brw_flag_reg(void)
+static inline brw_reg brw_flag_reg(void)
{
- return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_FLAG,
- 0);
+ return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_FLAG, 0);
}
-
-static inline struct brw_reg brw_mask_reg(uint32_t subnr)
+static inline brw_reg brw_mask_reg(uint32_t subnr)
{
- return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_MASK,
- subnr);
+ return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);
}
/* This is almost always called with a numeric constant argument, so
return 0;
}
-static inline struct brw_reg stride(struct brw_reg reg,
+static inline brw_reg stride(brw_reg reg,
uint32_t vstride,
uint32_t width,
uint32_t hstride)
}
-static inline struct brw_reg vec16(struct brw_reg reg)
+static inline brw_reg vec16(brw_reg reg)
{
return stride(reg, 16,16,1);
}
-static inline struct brw_reg vec8(struct brw_reg reg)
+static inline brw_reg vec8(brw_reg reg)
{
return stride(reg, 8,8,1);
}
-static inline struct brw_reg vec4(struct brw_reg reg)
+static inline brw_reg vec4(brw_reg reg)
{
return stride(reg, 4,4,1);
}
-static inline struct brw_reg vec2(struct brw_reg reg)
+static inline brw_reg vec2(brw_reg reg)
{
return stride(reg, 2,2,1);
}
-static inline struct brw_reg vec1(struct brw_reg reg)
+static inline brw_reg vec1(brw_reg reg)
{
return stride(reg, 0,1,0);
}
-static inline struct brw_reg get_element(struct brw_reg reg, uint32_t elt)
+static inline brw_reg get_element(brw_reg reg, uint32_t elt)
{
return vec1(suboffset(reg, elt));
}
-static inline struct brw_reg get_element_ud(struct brw_reg reg, uint32_t elt)
+static inline brw_reg get_element_ud(brw_reg reg, uint32_t elt)
{
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
}
-static inline struct brw_reg get_element_d(struct brw_reg reg, uint32_t elt)
+static inline brw_reg get_element_d(brw_reg reg, uint32_t elt)
{
return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
}
-static inline struct brw_reg brw_swizzle(struct brw_reg reg,
- uint32_t x,
- uint32_t y,
- uint32_t z,
- uint32_t w)
+static inline brw_reg brw_swizzle(brw_reg reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
-
reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
}
-static inline struct brw_reg brw_swizzle1(struct brw_reg reg,
- uint32_t x)
+static inline brw_reg brw_swizzle1(brw_reg reg, uint32_t x)
{
return brw_swizzle(reg, x, x, x, x);
}
-static inline struct brw_reg brw_writemask(struct brw_reg reg,
- uint32_t mask)
+static inline brw_reg brw_writemask(brw_reg reg, uint32_t mask)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
reg.dw1.bits.writemask &= mask;
return reg;
}
-static inline struct brw_reg brw_set_writemask(struct brw_reg reg, uint32_t mask)
+static inline brw_reg brw_set_writemask(brw_reg reg, uint32_t mask)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
reg.dw1.bits.writemask = mask;
return reg;
}
-static inline struct brw_reg negate(struct brw_reg reg)
+static inline brw_reg negate(brw_reg reg)
{
reg.negate ^= 1;
return reg;
}
-static inline struct brw_reg brw_abs(struct brw_reg reg)
+static inline brw_reg brw_abs(brw_reg reg)
{
reg.abs = 1;
reg.negate = 0;
return reg;
}
-static inline struct brw_reg brw_vec4_indirect(uint32_t subnr,
- int offset)
+static inline brw_reg brw_vec4_indirect(uint32_t subnr, int offset)
{
- struct brw_reg reg = brw_vec4_grf(0, 0);
+ brw_reg reg = brw_vec4_grf(0, 0);
reg.subnr = subnr;
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
return reg;
}
-static inline struct brw_reg brw_vec1_indirect(uint32_t subnr, int offset)
+static inline brw_reg brw_vec1_indirect(uint32_t subnr, int offset)
{
- struct brw_reg reg = brw_vec1_grf(0, 0);
+ brw_reg reg = brw_vec1_grf(0, 0);
reg.subnr = subnr;
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
return reg;
}
-static inline struct brw_reg deref_4f(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_4f(brw_indirect ptr, int offset)
{
return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
}
-static inline struct brw_reg deref_1f(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_1f(brw_indirect ptr, int offset)
{
return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
}
-static inline struct brw_reg deref_4b(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_4b(brw_indirect ptr, int offset)
{
return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
}
-static inline struct brw_reg deref_1uw(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_1uw(brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
}
-static inline struct brw_reg deref_1d(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_1d(brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
}
-static inline struct brw_reg deref_1ud(struct brw_indirect ptr, int offset)
+static inline brw_reg deref_1ud(brw_indirect ptr, int offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
}
-static inline struct brw_reg get_addr_reg(struct brw_indirect ptr)
+static inline brw_reg get_addr_reg(brw_indirect ptr)
{
return brw_address_reg(ptr.addr_subnr);
}
-static inline struct brw_indirect brw_indirect_offset(struct brw_indirect ptr, int offset)
+static inline brw_indirect brw_indirect_offset(brw_indirect ptr, int offset)
{
ptr.addr_offset += offset;
return ptr;
}
-static inline struct brw_indirect brw_indirect(uint32_t addr_subnr, int offset)
+static inline brw_indirect make_brw_indirect(uint32_t addr_subnr, int offset)
{
- struct brw_indirect ptr;
+ brw_indirect ptr;
ptr.addr_subnr = addr_subnr;
ptr.addr_offset = offset;
ptr.pad = 0;
return ptr;
}
-/** Do two brw_regs refer to the same register? */
static inline bool
-brw_same_reg(struct brw_reg r1, struct brw_reg r2)
+brw_same_reg(brw_reg r1, brw_reg r2)
{
return r1.file == r2.file && r1.nr == r2.nr;
}
-static inline struct brw_instruction *current_insn(struct brw_compile *p)
-{
- return &p->store[p->nr_insn];
-}
-
-void brw_pop_insn_state(struct brw_compile *p);
-void brw_push_insn_state(struct brw_compile *p);
-void brw_set_mask_control(struct brw_compile *p, uint32_t value);
-void brw_set_saturate(struct brw_compile *p, uint32_t value);
-void brw_set_access_mode(struct brw_compile *p, uint32_t access_mode);
-void brw_set_compression_control(struct brw_compile *p, enum brw_compression c);
-void brw_set_predicate_control_flag_value(struct brw_compile *p, uint32_t value);
-void brw_set_predicate_control(struct brw_compile *p, uint32_t pc);
-void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
-void brw_set_conditionalmod(struct brw_compile *p, uint32_t conditional);
-void brw_set_acc_write_control(struct brw_compile *p, uint32_t value);
-
-void brw_init_compile(struct brw_context *, struct brw_compile *p,
- void *mem_ctx);
-const uint32_t *brw_get_program(struct brw_compile *p, uint32_t *sz);
-
-struct brw_instruction *brw_next_insn(struct brw_compile *p, uint32_t opcode);
-void brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
- struct brw_reg dest);
-void brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
- struct brw_reg reg);
-
-void gen6_resolve_implied_move(struct brw_compile *p,
- struct brw_reg *src,
- uint32_t msg_reg_nr);
-
-/* Helpers for regular instructions:
- */
-#define ALU1(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0);
-
-#define ALU2(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0, \
- struct brw_reg src1);
-
-#define ALU3(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0, \
- struct brw_reg src1, \
- struct brw_reg src2);
-
-#define ROUND(OP) \
-void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
-
-ALU1(MOV)
-ALU2(SEL)
-ALU1(NOT)
-ALU2(AND)
-ALU2(OR)
-ALU2(XOR)
-ALU2(SHR)
-ALU2(SHL)
-ALU2(RSR)
-ALU2(RSL)
-ALU2(ASR)
-ALU2(JMPI)
-ALU2(ADD)
-ALU2(MUL)
-ALU1(FRC)
-ALU1(RNDD)
-ALU2(MAC)
-ALU2(MACH)
-ALU1(LZD)
-ALU2(DP4)
-ALU2(DPH)
-ALU2(DP3)
-ALU2(DP2)
-ALU2(LINE)
-ALU2(PLN)
-ALU3(MAD)
-
-ROUND(RNDZ)
-ROUND(RNDE)
-
-#undef ALU1
-#undef ALU2
-#undef ALU3
-#undef ROUND
-
-
-/* Helpers for SEND instruction */
-void brw_set_sampler_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t sampler,
- uint32_t msg_type,
- uint32_t response_length,
- uint32_t msg_length,
- uint32_t header_present,
- uint32_t simd_mode,
- uint32_t return_format);
-
-void brw_set_dp_read_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t msg_control,
- uint32_t msg_type,
- uint32_t target_cache,
- uint32_t msg_length,
- uint32_t response_length);
-
-void brw_set_dp_write_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t msg_control,
- uint32_t msg_type,
- uint32_t msg_length,
- bool header_present,
- uint32_t last_render_target,
- uint32_t response_length,
- uint32_t end_of_thread,
- uint32_t send_commit_msg);
-
-void brw_SAMPLE(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t msg_reg_nr,
- struct brw_reg src0,
- uint32_t binding_table_index,
- uint32_t sampler,
- uint32_t writemask,
- uint32_t msg_type,
- uint32_t response_length,
- uint32_t msg_length,
- uint32_t header_present,
- uint32_t simd_mode,
- uint32_t return_format);
-
-void brw_math_16(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t function,
- uint32_t saturate,
- uint32_t msg_reg_nr,
- struct brw_reg src,
- uint32_t precision);
-
-void brw_math(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t function,
- uint32_t saturate,
- uint32_t msg_reg_nr,
- struct brw_reg src,
- uint32_t data_type,
- uint32_t precision);
-
-void brw_math2(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t function,
- struct brw_reg src0,
- struct brw_reg src1);
-
-void brw_EOT(struct brw_compile *p, uint32_t msg_nr);
-
-void brw_oword_block_read(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
- uint32_t offset,
- uint32_t bind_table_index);
-
-void brw_oword_block_read_scratch(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
- int num_regs,
- uint32_t offset);
-
-void brw_oword_block_write_scratch(struct brw_compile *p,
- struct brw_reg mrf,
- int num_regs,
- uint32_t offset);
-
-void brw_dword_scattered_read(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
- uint32_t bind_table_index);
-/* Forward jumps:
- */
-void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx);
-
-void brw_NOP(struct brw_compile *p);
-
-void brw_WAIT(struct brw_compile *p);
-
-/* Special case: there is never a destination, execution size will be
- * taken from src0:
- */
-void brw_CMP(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t conditional,
- struct brw_reg src0,
- struct brw_reg src1);
-
-void brw_print_reg(struct brw_reg reg);
-
-void brw_copy_indirect_to_indirect(struct brw_compile *p,
- struct brw_indirect dst_ptr,
- struct brw_indirect src_ptr,
- uint32_t count);
-
-void brw_copy_from_indirect(struct brw_compile *p,
- struct brw_reg dst,
- struct brw_indirect ptr,
- uint32_t count);
-
-void brw_copy4(struct brw_compile *p,
- struct brw_reg dst,
- struct brw_reg src,
- uint32_t count);
-
-void brw_copy8(struct brw_compile *p,
- struct brw_reg dst,
- struct brw_reg src,
- uint32_t count);
-
-void brw_math_invert(struct brw_compile *p,
- struct brw_reg dst,
- struct brw_reg src);
-
-void brw_set_src1(struct brw_compile *p,
- struct brw_instruction *insn,
- struct brw_reg reg);
-
-void brw_set_uip_jip(struct brw_compile *p);
-
uint32_t brw_swap_cmod(uint32_t cmod);
#ifdef __cplusplus
#define Elements(x) (sizeof(x) / sizeof(*(x)))
-/***********************************************************************
- * Internal helper for constructing instructions
- */
-
-static void guess_execution_size(struct brw_compile *p,
- struct brw_instruction *insn,
- struct brw_reg reg)
+void brw_compile::guess_execution_size(brw_instruction *insn, brw_reg reg)
{
- if (reg.width == BRW_WIDTH_8 && p->compressed)
+ if (reg.width == BRW_WIDTH_8 && this->compressed)
insn->header.execution_size = BRW_EXECUTE_16;
else
insn->header.execution_size = reg.width; /* note - definitions are compatible */
}
+/* Returns the corresponding conditional mod for swapping src0 and
+ * src1 in e.g. CMP.
+ */
+uint32_t brw_swap_cmod(uint32_t cmod)
+{
+ switch (cmod) {
+ case BRW_CONDITIONAL_Z:
+ case BRW_CONDITIONAL_NZ:
+ return cmod;
+ case BRW_CONDITIONAL_G:
+ return BRW_CONDITIONAL_LE;
+ case BRW_CONDITIONAL_GE:
+ return BRW_CONDITIONAL_L;
+ case BRW_CONDITIONAL_L:
+ return BRW_CONDITIONAL_GE;
+ case BRW_CONDITIONAL_LE:
+ return BRW_CONDITIONAL_G;
+ default:
+ return ~0;
+ }
+}
+
+/* How does predicate control work when execution_size != 8? Do I
+ * need to test/set for 0xffff when execution_size is 16?
+ */
+void brw_compile::brw_set_predicate_control_flag_value(uint32_t value)
+{
+ if (value != 0xff) {
+ if (value != this->flag_value) {
+ this->brw_MOV(brw_flag_reg(), brw_imm_uw(value));
+ this->flag_value = value;
+ }
+ }
+}
+
+void brw_compile::brw_set_predicate_control(uint32_t pc)
+{
+ // p->current->header.predicate_control = pc;
+}
+
+void brw_compile::brw_set_predicate_inverse(bool predicate_inverse)
+{
+ // p->current->header.predicate_inverse = predicate_inverse;
+}
+
+void brw_compile::brw_set_conditionalmod(uint32_t conditional)
+{
+ // p->current->header.destreg__conditionalmod = conditional;
+}
+
+void brw_compile::brw_set_access_mode(uint32_t access_mode)
+{
+ // p->current->header.access_mode = access_mode;
+}
+
void
-brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
- struct brw_reg dest)
+brw_compile::brw_set_compression_control(enum brw_compression compression_control)
+{
+#if 0
+ p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
+
+ if (p->gen >= 6) {
+ /* Since we don't use the 32-wide support in gen6, we translate
+ * the pre-gen6 compression control here.
+ */
+ switch (compression_control) {
+ case BRW_COMPRESSION_NONE:
+ /* This is the "use the first set of bits of dmask/vmask/arf
+ * according to execsize" option.
+ */
+ p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+ break;
+ case BRW_COMPRESSION_2NDHALF:
+ /* For 8-wide, this is "use the second set of 8 bits." */
+ p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+ break;
+ case BRW_COMPRESSION_COMPRESSED:
+ /* For 16-wide instruction compression, use the first set of 16 bits
+ * since we don't do 32-wide dispatch.
+ */
+ p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ break;
+ default:
+ assert(!"not reached");
+ p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ break;
+ }
+ } else {
+ p->current->header.compression_control = compression_control;
+ }
+#endif
+}
+
+void brw_compile::brw_set_dest(brw_instruction *insn, brw_reg dest)
{
if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE)
assert(dest.nr < 128);
/* NEW: Set the execution size based on dest.width and
* insn->compression_control:
*/
- guess_execution_size(p, insn, dest);
+ guess_execution_size(insn, dest);
}
-extern int reg_type_size[];
+static const int reg_type_size[8] = { 4, 4, 2, 2, 1, 1, 4 };
static void
-validate_reg(struct brw_instruction *insn, struct brw_reg reg)
+validate_reg(brw_instruction *insn, brw_reg reg)
{
int hstride_for_reg[] = {0, 1, 2, 4};
int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
}
void
-brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
- struct brw_reg reg)
+brw_compile::brw_set_src0(brw_instruction *insn, brw_reg reg)
{
if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE)
assert(reg.nr < 128);
}
-void brw_set_src1(struct brw_compile *p,
- struct brw_instruction *insn,
- struct brw_reg reg)
+void brw_compile::brw_set_src1(
+ brw_instruction *insn,
+ brw_reg reg)
{
assert(reg.nr < 128);
* choose not to fill in irrelevant bits; they will be zero.
*/
static void
-brw_set_message_descriptor(struct brw_compile *p,
- struct brw_instruction *inst,
+brw_set_message_descriptor(brw_compile *p,
+ brw_instruction *inst,
enum brw_message_target sfid,
unsigned msg_length,
unsigned response_length,
bool header_present,
bool end_of_thread)
{
- brw_set_src1(p, inst, brw_imm_d(0));
+ p->brw_set_src1(inst, brw_imm_d(0));
if (p->gen >= 5) {
inst->bits3.generic_gen5.header_present = header_present;
}
}
-static void brw_set_math_message(struct brw_compile *p,
- struct brw_instruction *insn,
+static void brw_set_math_message(brw_compile *p,
+ brw_instruction *insn,
uint32_t function,
uint32_t integer_type,
bool low_precision,
}
void
-brw_set_dp_write_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t msg_control,
- uint32_t msg_type,
- uint32_t msg_length,
- bool header_present,
- uint32_t last_render_target,
- uint32_t response_length,
- uint32_t end_of_thread,
- uint32_t send_commit_msg)
+brw_compile::brw_set_dp_write_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t msg_control,
+ uint32_t msg_type,
+ uint32_t msg_length,
+ bool header_present,
+ uint32_t last_render_target,
+ uint32_t response_length,
+ uint32_t end_of_thread,
+ uint32_t send_commit_msg)
{
unsigned sfid;
sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
else
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
- brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
+ brw_set_message_descriptor(this, insn, brw_message_target(sfid),
+ msg_length, response_length,
header_present, end_of_thread);
insn->bits3.gen7_dp.binding_table_index = binding_table_index;
}
void
-brw_set_dp_read_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t msg_control,
- uint32_t msg_type,
- uint32_t target_cache,
- uint32_t msg_length,
- uint32_t response_length)
+brw_compile::brw_set_dp_read_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t msg_control,
+ uint32_t msg_type,
+ uint32_t target_cache,
+ uint32_t msg_length,
+ uint32_t response_length)
{
unsigned sfid;
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
- brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
+ brw_set_message_descriptor(this, insn, brw_message_target(sfid), msg_length, response_length,
true, false);
insn->bits3.gen7_dp.binding_table_index = binding_table_index;
}
void
-brw_set_sampler_message(struct brw_compile *p,
- struct brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t sampler,
- uint32_t msg_type,
- uint32_t response_length,
- uint32_t msg_length,
- uint32_t header_present,
- uint32_t simd_mode,
- uint32_t return_format)
+brw_compile::brw_set_sampler_message(brw_instruction *insn,
+ uint32_t binding_table_index,
+ uint32_t sampler,
+ uint32_t msg_type,
+ uint32_t response_length,
+ uint32_t msg_length,
+ uint32_t header_present,
+ uint32_t simd_mode,
+ uint32_t return_format)
{
- brw_set_message_descriptor(p, insn, BRW_SFID_SAMPLER, msg_length,
+ brw_set_message_descriptor(this, insn, BRW_SFID_SAMPLER, msg_length,
response_length, header_present, false);
insn->bits3.sampler_gen7.binding_table_index = binding_table_index;
insn->bits3.sampler_gen7.sampler = sampler;
}
#define next_insn brw_next_insn
-struct brw_instruction *
-brw_next_insn(struct brw_compile *p, uint32_t opcode)
+brw_instruction *
+brw_compile::brw_next_insn(uint32_t opcode)
{
- struct brw_instruction *insn;
- insn = &p->store[p->nr_insn++];
+ brw_instruction *insn;
+ insn = &this->store[this->nr_insn++];
insn->header.opcode = opcode;
return insn;
}
-static struct brw_instruction *brw_alu1(struct brw_compile *p,
- uint32_t opcode,
- struct brw_reg dest,
- struct brw_reg src)
+static brw_instruction *brw_alu1(brw_compile *p,
+ uint32_t opcode,
+ brw_reg dest,
+ brw_reg src)
{
- struct brw_instruction *insn = next_insn(p, opcode);
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src);
+ brw_instruction *insn = p->next_insn(opcode);
+ p->brw_set_dest(insn, dest);
+ p->brw_set_src0(insn, src);
return insn;
}
-static struct brw_instruction *brw_alu2(struct brw_compile *p,
- uint32_t opcode,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+static brw_instruction *brw_alu2(brw_compile *p,
+ uint32_t opcode,
+ brw_reg dest,
+ brw_reg src0,
+ brw_reg src1)
{
- struct brw_instruction *insn = next_insn(p, opcode);
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src0);
- brw_set_src1(p, insn, src1);
+ brw_instruction *insn = p->next_insn(opcode);
+ p->brw_set_dest(insn, dest);
+ p->brw_set_src0(insn, src0);
+ p->brw_set_src1(insn, src1);
return insn;
}
static int
-get_3src_subreg_nr(struct brw_reg reg)
+get_3src_subreg_nr(brw_reg reg)
{
if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
assert(brw_is_single_value_swizzle(reg.dw1.bits.swizzle));
return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0);
- } else {
+ } else
return reg.subnr / 4;
- }
}
-static struct brw_instruction *brw_alu3(struct brw_compile *p,
- uint32_t opcode,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1,
- struct brw_reg src2)
+static brw_instruction *brw_alu3(brw_compile *p,
+ uint32_t opcode,
+ brw_reg dest,
+ brw_reg src0,
+ brw_reg src1,
+ brw_reg src2)
{
- struct brw_instruction *insn = next_insn(p, opcode);
+ brw_instruction *insn = p->next_insn(opcode);
assert(insn->header.access_mode == BRW_ALIGN_16);
insn->bits1.da3src.dest_reg_nr = dest.nr;
insn->bits1.da3src.dest_subreg_nr = dest.subnr / 16;
insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
- guess_execution_size(p, insn, dest);
+ p->guess_execution_size(insn, dest);
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
/***********************************************************************
* Convenience routines.
*/
-#define ALU1(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0) \
-{ \
- return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
+#define ALU1(OP) \
+brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0) \
+{ \
+ return brw_alu1(this, BRW_OPCODE_##OP, dest, src0); \
}
-#define ALU2(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0, \
- struct brw_reg src1) \
-{ \
- return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
+#define ALU2(OP) \
+brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1) \
+{ \
+ return brw_alu2(this, BRW_OPCODE_##OP, dest, src0, src1); \
}
-#define ALU3(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src0, \
- struct brw_reg src1, \
- struct brw_reg src2) \
-{ \
- return brw_alu3(p, BRW_OPCODE_##OP, dest, \
- src0, src1, src2); \
+#define ALU3(OP) \
+brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1, brw_reg src2) \
+{ \
+ return brw_alu3(this, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
/* Rounding operations (other than RNDD) require two instructions - the first
*
* Sandybridge and later appear to round correctly without an ADD.
*/
-#define ROUND(OP) \
-void brw_##OP(struct brw_compile *p, \
- struct brw_reg dest, \
- struct brw_reg src) \
-{ \
- struct brw_instruction *rnd; \
- rnd = next_insn(p, BRW_OPCODE_##OP); \
- brw_set_dest(p, rnd, dest); \
- brw_set_src0(p, rnd, src); \
+#define ROUND(OP) \
+void brw_compile::brw_##OP(brw_reg dest, brw_reg src) \
+{ \
+ brw_instruction *rnd; \
+ rnd = this->next_insn(BRW_OPCODE_##OP); \
+ this->brw_set_dest(rnd, dest); \
+ this->brw_set_src0(rnd, src); \
}
ALU1(MOV)
ROUND(RNDZ)
ROUND(RNDE)
-struct brw_instruction *brw_ADD(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+brw_instruction *brw_compile::brw_ADD(
+ brw_reg dest,
+ brw_reg src0,
+ brw_reg src1)
{
/* 6.2.2: add */
if (src0.type == BRW_REGISTER_TYPE_F ||
assert(src0.type != BRW_REGISTER_TYPE_D);
}
- return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
+ return brw_alu2(this, BRW_OPCODE_ADD, dest, src0, src1);
}
-struct brw_instruction *brw_MUL(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+brw_instruction *brw_compile::brw_MUL(
+ brw_reg dest,
+ brw_reg src0,
+ brw_reg src1)
{
/* 6.32.38: mul */
if (src0.type == BRW_REGISTER_TYPE_D ||
assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE ||
src1.nr != BRW_ARF_ACCUMULATOR);
- return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1);
+ return brw_alu2(this, BRW_OPCODE_MUL, dest, src0, src1);
}
-void brw_NOP(struct brw_compile *p)
+void brw_compile::brw_NOP(void)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
- brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src1(p, insn, brw_imm_ud(0x0));
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_NOP);
+ this->brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ this->brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ this->brw_set_src1(insn, brw_imm_ud(0x0));
}
-/***********************************************************************
- * Comparisons, if/else/endif
- */
-
-struct brw_instruction *brw_JMPI(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+brw_instruction *brw_compile::brw_JMPI(
+ brw_reg dest,
+ brw_reg src0,
+ brw_reg src1)
{
- struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1);
+ brw_instruction *insn = brw_alu2(this, BRW_OPCODE_JMPI, dest, src0, src1);
insn->header.execution_size = 1;
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.mask_control = BRW_MASK_DISABLE;
- // p->current->header.predicate_control = BRW_PREDICATE_NONE;
+ // this->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}
* instruction should populate the flag register. It might be simpler
* just to use the flag reg for most WM tasks?
*/
-void brw_CMP(struct brw_compile *p,
- struct brw_reg dest,
+void brw_compile::brw_CMP(
+ brw_reg dest,
uint32_t conditional,
- struct brw_reg src0,
- struct brw_reg src1)
+ brw_reg src0,
+ brw_reg src1)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_CMP);
insn->header.destreg__conditionalmod = conditional;
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src0);
- brw_set_src1(p, insn, src1);
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src0);
+ this->brw_set_src1(insn, src1);
/* guess_execution_size(insn, src0); */
#if 0
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == 0) {
- p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
- p->flag_value = 0xff;
+ this->current->header.predicate_control = BRW_PREDICATE_NORMAL;
+ this->flag_value = 0xff;
}
#endif
}
/* Issue 'wait' instruction for n1, host could program MMIO
to wake up thread. */
-void brw_WAIT (struct brw_compile *p)
+void brw_compile::brw_WAIT(void)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT);
- struct brw_reg src = brw_notification_1_reg();
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_WAIT);
+ brw_reg src = brw_notification_1_reg();
- brw_set_dest(p, insn, src);
- brw_set_src0(p, insn, src);
- brw_set_src1(p, insn, brw_null_reg());
+ this->brw_set_dest(insn, src);
+ this->brw_set_src0(insn, src);
+ this->brw_set_src1(insn, brw_null_reg());
insn->header.execution_size = 0; /* must */
insn->header.predicate_control = 0;
insn->header.compression_control = 0;
}
-
-/***********************************************************************
- * Helpers for the various SEND message types:
- */
-
-/** Extended math function, float[8]. */
-void brw_math(struct brw_compile *p,
- struct brw_reg dest,
+/* Extended math function, float[8] */
+void brw_compile::brw_math(
+ brw_reg dest,
uint32_t function,
uint32_t saturate,
uint32_t msg_reg_nr,
- struct brw_reg src,
+ brw_reg src,
uint32_t data_type,
uint32_t precision)
{
- if (p->gen >= 6) {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH);
+ if (this->gen >= 6) {
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_MATH);
assert(dest.file == BRW_GENERAL_REGISTER_FILE);
assert(src.file == BRW_GENERAL_REGISTER_FILE);
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
- if (p->gen == 6)
+ if (this->gen == 6)
assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
/* Source modifiers are ignored for extended math instructions on Gen6. */
- if (p->gen == 6) {
+ if (this->gen == 6) {
assert(!src.negate);
assert(!src.abs);
}
insn->header.destreg__conditionalmod = function;
insn->header.saturate = saturate;
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src);
- brw_set_src1(p, insn, brw_null_reg());
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src);
+ this->brw_set_src1(insn, brw_null_reg());
} else {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_SEND);
/* Example code doesn't set predicate_control for send
* instructions.
insn->header.predicate_control = 0;
insn->header.destreg__conditionalmod = msg_reg_nr;
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src);
- brw_set_math_message(p,
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src);
+ brw_set_math_message(this,
insn,
function,
src.type == BRW_REGISTER_TYPE_D,
}
}
-/** Extended math function, float[8].
- */
-void brw_math2(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t function,
- struct brw_reg src0,
- struct brw_reg src1)
+/* Extended math function, float[8] */
+void brw_compile::brw_math2(brw_reg dest,
+ uint32_t function,
+ brw_reg src0,
+ brw_reg src1)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH);
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_MATH);
- assert(p->gen >= 6);
+ assert(this->gen >= 6);
assert(dest.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
- if (p->gen == 6) {
+ if (this->gen == 6) {
assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1);
}
}
/* Source modifiers are ignored for extended math instructions on Gen6. */
- if (p->gen == 6) {
+ if (this->gen == 6) {
assert(!src0.negate);
assert(!src0.abs);
assert(!src1.negate);
*/
insn->header.destreg__conditionalmod = function;
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src0);
- brw_set_src1(p, insn, src1);
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src0);
+ this->brw_set_src1(insn, src1);
}
-/**
- * Extended math function, float[16].
- * Use 2 send instructions.
- */
-void brw_math_16(struct brw_compile *p,
- struct brw_reg dest,
- uint32_t function,
- uint32_t saturate,
- uint32_t msg_reg_nr,
- struct brw_reg src,
- uint32_t precision)
+/* Extended math function, float[16] */
+void brw_compile::brw_math_16(brw_reg dest,
+ uint32_t function,
+ uint32_t saturate,
+ uint32_t msg_reg_nr,
+ brw_reg src,
+ uint32_t precision)
{
- struct brw_instruction *insn;
+ brw_instruction *insn;
- if (p->gen >= 6) {
- insn = next_insn(p, BRW_OPCODE_MATH);
+ insn = this->next_insn(BRW_OPCODE_MATH);
- /* Math is the same ISA format as other opcodes, except that CondModifier
- * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
- */
- insn->header.destreg__conditionalmod = function;
- insn->header.saturate = saturate;
-
- /* Source modifiers are ignored for extended math instructions. */
- assert(!src.negate);
- assert(!src.abs);
-
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src);
- brw_set_src1(p, insn, brw_null_reg());
- return;
- }
-
- /* First instruction:
- */
- brw_push_insn_state(p);
- brw_set_predicate_control_flag_value(p, 0xff);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-
- insn = next_insn(p, BRW_OPCODE_SEND);
- insn->header.destreg__conditionalmod = msg_reg_nr;
-
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src);
- brw_set_math_message(p,
- insn,
- function,
- BRW_MATH_INTEGER_UNSIGNED,
- precision,
- saturate,
- BRW_MATH_DATA_VECTOR);
-
- /* Second instruction:
- */
- insn = next_insn(p, BRW_OPCODE_SEND);
- insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
- insn->header.destreg__conditionalmod = msg_reg_nr+1;
-
- brw_set_dest(p, insn, offset(dest,1));
- brw_set_src0(p, insn, src);
- brw_set_math_message(p,
- insn,
- function,
- BRW_MATH_INTEGER_UNSIGNED,
- precision,
- saturate,
- BRW_MATH_DATA_VECTOR);
-
- brw_pop_insn_state(p);
-}
-
-
-/**
- * Write a block of OWORDs (half a GRF each) from the scratch buffer,
- * using a constant offset per channel.
- *
- * The offset must be aligned to oword size (16 bytes). Used for
- * register spilling.
- */
-void brw_oword_block_write_scratch(struct brw_compile *p,
- struct brw_reg mrf,
- int num_regs,
- uint32_t offset)
-{
- uint32_t msg_control, msg_type;
- int mlen;
-
- if (p->gen >= 6)
- offset /= 16;
-
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
-
- if (num_regs == 1) {
- msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
- mlen = 2;
- } else {
- msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
- mlen = 3;
- }
-
- /* Set up the message header. This is g0, with g0.2 filled with
- * the offset. We don't want to leave our offset around in g0 or
- * it'll screw up texture samples, so set it up inside the message
- * reg.
+ /* Math is the same ISA format as other opcodes, except that CondModifier
+ * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
*/
- {
- brw_push_insn_state(p);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-
- brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
-
- /* set message header global offset field (reg 0, element 2) */
- brw_MOV(p,
- retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE,
- mrf.nr,
- 2), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(offset));
-
- brw_pop_insn_state(p);
- }
-
- {
- struct brw_reg dest;
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
- int send_commit_msg;
- struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UW);
-
- if (insn->header.compression_control != BRW_COMPRESSION_NONE) {
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- src_header = vec16(src_header);
- }
- assert(insn->header.predicate_control == BRW_PREDICATE_NONE);
- insn->header.destreg__conditionalmod = mrf.nr;
-
- /* Until gen6, writes followed by reads from the same location
- * are not guaranteed to be ordered unless write_commit is set.
- * If set, then a no-op write is issued to the destination
- * register to set a dependency, and a read from the destination
- * can be used to ensure the ordering.
- *
- * For gen6, only writes between different threads need ordering
- * protection. Our use of DP writes is all about register
- * spilling within a thread.
- */
- if (p->gen >= 6) {
- dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
- send_commit_msg = 0;
- } else {
- dest = src_header;
- send_commit_msg = 1;
- }
-
- brw_set_dest(p, insn, dest);
- if (p->gen >= 6) {
- brw_set_src0(p, insn, mrf);
- } else {
- brw_set_src0(p, insn, brw_null_reg());
- }
-
- if (p->gen >= 6)
- msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
- else
- msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
-
- brw_set_dp_write_message(p,
- insn,
- 255, /* binding table index (255=stateless) */
- msg_control,
- msg_type,
- mlen,
- true, /* header_present */
- 0, /* not a render target */
- send_commit_msg, /* response_length */
- 0, /* eot */
- send_commit_msg);
- }
-}
-
-
-/**
- * Read a block of owords (half a GRF each) from the scratch buffer
- * using a constant index per channel.
- *
- * Offset must be aligned to oword size (16 bytes). Used for register
- * spilling.
- */
-void
-brw_oword_block_read_scratch(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
- int num_regs,
- uint32_t offset)
-{
- uint32_t msg_control;
- int rlen;
-
- if (p->gen >= 6)
- offset /= 16;
-
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
- dest = retype(dest, BRW_REGISTER_TYPE_UW);
-
- if (num_regs == 1) {
- msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
- rlen = 1;
- } else {
- msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
- rlen = 2;
- }
-
- {
- brw_push_insn_state(p);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
-
- brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
-
- /* set message header global offset field (reg 0, element 2) */
- brw_MOV(p,
- retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE,
- mrf.nr,
- 2), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(offset));
-
- brw_pop_insn_state(p);
- }
-
- {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ insn->header.destreg__conditionalmod = function;
+ insn->header.saturate = saturate;
- assert(insn->header.predicate_control == 0);
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.destreg__conditionalmod = mrf.nr;
+ /* Source modifiers are ignored for extended math instructions. */
+ assert(!src.negate);
+ assert(!src.abs);
- brw_set_dest(p, insn, dest); /* UW? */
- if (p->gen >= 6) {
- brw_set_src0(p, insn, mrf);
- } else {
- brw_set_src0(p, insn, brw_null_reg());
- }
-
- brw_set_dp_read_message(p,
- insn,
- 255, /* binding table index (255=stateless) */
- msg_control,
- BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
- BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
- 1, /* msg_length */
- rlen);
- }
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src);
+ this->brw_set_src1(insn, brw_null_reg());
}
-/**
- * Read a float[4] vector from the data port Data Cache (const buffer).
- * Location (in buffer) should be a multiple of 16.
- * Used for fetching shader constants.
- */
-void brw_oword_block_read(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
- uint32_t offset,
- uint32_t bind_table_index)
-{
-
- /* On newer hardware, offset is in units of owords. */
- if (p->gen >= 6)
- offset /= 16;
-
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
-
- brw_push_insn_state(p);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
-
- brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
-
- /* set message header global offset field (reg 0, element 2) */
- brw_MOV(p,
- retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE,
- mrf.nr,
- 2), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(offset));
-
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
- insn->header.destreg__conditionalmod = mrf.nr;
-
- /* cast dest to a uword[8] vector */
- dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
-
- brw_set_dest(p, insn, dest);
- if (p->gen >= 6) {
- brw_set_src0(p, insn, mrf);
- } else {
- brw_set_src0(p, insn, brw_null_reg());
- }
-
- brw_set_dp_read_message(p,
- insn,
- bind_table_index,
- BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW,
- BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
- BRW_DATAPORT_READ_TARGET_DATA_CACHE,
- 1, /* msg_length */
- 1); /* response_length (1 reg, 2 owords!) */
-
- brw_pop_insn_state(p);
-}
/**
* Read a set of dwords from the data port Data Cache (const buffer).
* Location (in buffer) appears as UD offsets in the register after
* the provided mrf header reg.
*/
-void brw_dword_scattered_read(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg mrf,
+void brw_compile::brw_dword_scattered_read(
+ brw_reg dest,
+ brw_reg mrf,
uint32_t bind_table_index)
{
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
- brw_push_insn_state(p);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
- brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
- brw_pop_insn_state(p);
+ this->brw_set_predicate_control(BRW_PREDICATE_NONE);
+ this->brw_set_compression_control(BRW_COMPRESSION_NONE);
+ this->brw_MOV(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ brw_instruction *insn = this->next_insn(BRW_OPCODE_SEND);
insn->header.destreg__conditionalmod = mrf.nr;
/* cast dest to a uword[8] vector */
dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, brw_null_reg());
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, brw_null_reg());
- brw_set_dp_read_message(p,
- insn,
+ this->brw_set_dp_read_message(insn,
bind_table_index,
BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS,
BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ,
* Note: the msg_type plus msg_length values determine exactly what kind
* of sampling operation is performed. See volume 4, page 161 of docs.
*/
-void brw_SAMPLE(struct brw_compile *p,
- struct brw_reg dest,
+void brw_compile::brw_SAMPLE(
+ brw_reg dest,
uint32_t msg_reg_nr,
- struct brw_reg src0,
+ brw_reg src0,
uint32_t binding_table_index,
uint32_t sampler,
uint32_t writemask,
assert (writemask == WRITEMASK_XYZW);
{
- struct brw_instruction *insn;
+ brw_instruction *insn;
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = this->next_insn(BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
- if (p->gen < 6)
+ if (this->gen < 6)
insn->header.destreg__conditionalmod = msg_reg_nr;
- brw_set_dest(p, insn, dest);
- brw_set_src0(p, insn, src0);
- brw_set_sampler_message(p, insn,
+ this->brw_set_dest(insn, dest);
+ this->brw_set_src0(insn, src0);
+ this->brw_set_sampler_message(insn,
binding_table_index,
sampler,
msg_type,
}
if (need_stall) {
- struct brw_reg reg = vec8(offset(dest, response_length-1));
+ brw_reg reg = vec8(offset(dest, response_length-1));
- /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 }
- */
- brw_push_insn_state(p);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_MOV(p, retype(reg, BRW_REGISTER_TYPE_UD),
- retype(reg, BRW_REGISTER_TYPE_UD));
- brw_pop_insn_state(p);
+ /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 } */
+ this->brw_set_compression_control(BRW_COMPRESSION_NONE);
+ this->brw_MOV(retype(reg, BRW_REGISTER_TYPE_UD),
+ retype(reg, BRW_REGISTER_TYPE_UD));
}
}
void
-brw_EOT(struct brw_compile *p, uint32_t msg_nr)
+brw_compile::brw_EOT(uint32_t msg_nr)
{
- struct brw_instruction *insn = NULL;
+ brw_instruction *insn = NULL;
- insn = brw_MOV(p, brw_vec8_grf(msg_nr,0), brw_vec8_grf(0,0));
+ insn = this->brw_MOV(brw_vec8_grf(msg_nr,0), brw_vec8_grf(0,0));
insn->header.mask_control = BRW_MASK_DISABLE;
- insn = next_insn(p, BRW_OPCODE_SEND);
- brw_set_dest(p, insn, brw_null_reg());
- brw_set_src0(p, insn, brw_vec8_grf(msg_nr,0));
- brw_set_src1(p, insn, brw_imm_ud(0));
+ insn = this->next_insn(BRW_OPCODE_SEND);
+ this->brw_set_dest(insn, brw_null_reg());
+ this->brw_set_src0(insn, brw_vec8_grf(msg_nr,0));
+ this->brw_set_src1(insn, brw_imm_ud(0));
insn->header.execution_size = BRW_EXECUTE_8;
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->bits3.spawner_gen5.resource = BRW_DO_NOT_DEREFERENCE_URB;
GenKernel *genKernel = static_cast<GenKernel*>(this->kernel);
brw_compile *p = (brw_compile*) GBE_MALLOC(sizeof(brw_compile));
std::memset(p, 0, sizeof(*p));
- brw_EOT(p, 127);
+ p->brw_EOT(127);
genKernel->insnNum = p->nr_insn;
genKernel->insns = GBE_NEW_ARRAY(brw_instruction, genKernel->insnNum);
std::memcpy(genKernel->insns, p->store, genKernel->insnNum * sizeof(brw_instruction));
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