drm/i915: Use standard form terminating condition for lane for loops

Use <4 instead of <=3 as the terminating condition for the
loops over the 4 lanes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fb5bd1f970c6152a52bf3e29d2cf93ffcdc74d29..4b8cae12a3821732a39028160c6117c96d7ea6d5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 
        /* Program PORT_TX_DW4 */
        /* We cannot write to GRP. It would overwrite individual loadgen. */
-       for (ln = 0; ln <= 3; ln++) {
+       for (ln = 0; ln < 4; ln++) {
                val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
                val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
                         CURSOR_COEFF_MASK);
@@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
         * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
         * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
         */
-       for (ln = 0; ln <= 3; ln++) {
+       for (ln = 0; ln < 4; ln++) {
                val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
                val &= ~LOADGEN_SELECT;