drm/radeon/kms: R3XX-R4XX fix GPU reset code

Previous reset code leaded to computer hard lockup (need to unplug
the power too reboot the computer) on various configuration. This
patch change the reset code to avoid hard lockup. The GPU reset
is failing most of the time but at least user can log in remotely
or properly shutdown the computer.

Two issues were leading to hard lockup :
- Writting to the scratch register lead to hard lockup most likely
because the write back mecanism is in fuzy state after GPU lockup.
- Resetting the GPU memory controller and not reinitializing it
after leaded to hard lockup. We did only reinitialize in case of
successfull reset thus unsuccessfull reset quickly leaded to hard
lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index bb005bf..5d622cb 100644 (file)
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -445,14 +445,6 @@ int r300_asic_reset(struct radeon_device *rdev)
        mdelay(1);
        status = RREG32(R_000E40_RBBM_STATUS);
        dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
-       /* reset MC */
-       WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
-       RREG32(R_0000F0_RBBM_SOFT_RESET);
-       mdelay(500);
-       WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
-       mdelay(1);
-       status = RREG32(R_000E40_RBBM_STATUS);
-       dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
        /* restore PCI & busmastering */
        pci_restore_state(rdev->pdev);
        r100_enable_bm(rdev);

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 1b8b9cc..b1f9a81 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -237,10 +237,10 @@ retry:
                         * as signaled for now
                         */
                        rdev->gpu_lockup = true;
-                       WREG32(rdev->fence_drv.scratch_reg, fence->seq);
                        r = radeon_gpu_reset(rdev);
                        if (r)
                                return r;
+                       WREG32(rdev->fence_drv.scratch_reg, fence->seq);
                        rdev->gpu_lockup = false;
                }
                timeout = RADEON_FENCE_JIFFIES_TIMEOUT;