drm/amd/amdgpu: add ih ip block for beige_goby
authorChengming Gui <Jack.Gui@amd.com>
Tue, 13 Oct 2020 08:58:01 +0000 (16:58 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 20 May 2021 02:40:19 +0000 (22:40 -0400)
Enable ih block for beige_goby, same as dimgrey_cavefish

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/nv.c

index f4e4040bbd25505e5df76bf0687bae008b57bfef..6eb60bca9f43a21ddbabdd06e67150448a621d8e 100644 (file)
@@ -311,6 +311,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
                        case CHIP_NAVY_FLOUNDER:
                        case CHIP_VANGOGH:
                        case CHIP_DIMGREY_CAVEFISH:
+                       case CHIP_BEIGE_GOBY:
                                ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
                                ih_chicken = REG_SET_FIELD(ih_chicken,
                                                IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
index 636f3652ca2ae17136eb374ff00af595cb295e99..cdb2a0abf632439a99051e34c28f2dc529125fd5 100644 (file)
@@ -954,6 +954,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
        case CHIP_BEIGE_GOBY:
                amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
                amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
                break;
        default:
                return -EINVAL;