S/390: Remove code duplication in vec_* comparison expanders

s390.md uses a lot of near-identical expanders that perform dispatching
to other expanders based on operand types. Since the following patch
would require even more of these, avoid copy-pasting the code by
generating these expanders using an iterator.

gcc/ChangeLog:

2019-10-01  Ilya Leoshkevich  <iii@linux.ibm.com>

	PR target/77918
	* config/s390/s390.c (s390_expand_vec_compare): Use
	gen_vec_cmpordered and gen_vec_cmpunordered.
	* config/s390/vector.md (vec_cmpuneq, vec_cmpltgt, vec_ordered,
	vec_unordered): Delete.
	(vec_ordered<mode>): Rename to vec_cmpordered<mode>.
	(vec_unordered<mode>): Rename to vec_cmpunordered<mode>.
	(VEC_CMP_EXPAND): New iterator for the generic dispatcher.
	(vec_cmp<code>): Generic dispatcher.

From-SVN: r276409

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 60c8f9f..c32bf84 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,18 @@
 2019-10-01  Ilya Leoshkevich  <iii@linux.ibm.com>
 
        PR target/77918
+       * config/s390/s390.c (s390_expand_vec_compare): Use
+       gen_vec_cmpordered and gen_vec_cmpunordered.
+       * config/s390/vector.md (vec_cmpuneq, vec_cmpltgt, vec_ordered,
+       vec_unordered): Delete.
+       (vec_ordered<mode>): Rename to vec_cmpordered<mode>.
+       (vec_unordered<mode>): Rename to vec_cmpunordered<mode>.
+       (VEC_CMP_EXPAND): New iterator for the generic dispatcher.
+       (vec_cmp<code>): Generic dispatcher.
+
+2019-10-01  Ilya Leoshkevich  <iii@linux.ibm.com>
+
+       PR target/77918
        * config/s390/vector.md (V_HW): Add V1TI in order to make
        vcond$a$b generate vcondv1tiv1tf.
 

diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 1764c34..062cbd8 100644 (file)
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -6523,10 +6523,10 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond,
          emit_insn (gen_vec_cmpltgt (target, cmp_op1, cmp_op2));
          return;
        case ORDERED:
-         emit_insn (gen_vec_ordered (target, cmp_op1, cmp_op2));
+         emit_insn (gen_vec_cmpordered (target, cmp_op1, cmp_op2));
          return;
        case UNORDERED:
-         emit_insn (gen_vec_unordered (target, cmp_op1, cmp_op2));
+         emit_insn (gen_vec_cmpunordered (target, cmp_op1, cmp_op2));
          return;
        default: break;
        }

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index d624d3f..451d07d 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1472,22 +1472,6 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
-(define_expand "vec_cmpuneq"
-  [(match_operand 0 "register_operand" "")
-   (match_operand 1 "register_operand" "")
-   (match_operand 2 "register_operand" "")]
-  "TARGET_VX"
-{
-  if (GET_MODE (operands[1]) == V4SFmode)
-    emit_insn (gen_vec_cmpuneqv4sf (operands[0], operands[1], operands[2]));
-  else if (GET_MODE (operands[1]) == V2DFmode)
-    emit_insn (gen_vec_cmpuneqv2df (operands[0], operands[1], operands[2]));
-  else
-    gcc_unreachable ();
-
-  DONE;
-})
-
 ; LTGT a <> b -> a > b | b > a
 (define_expand "vec_cmpltgt<mode>"
   [(set (match_operand:<tointvec>         0 "register_operand" "=v")
@@ -1500,24 +1484,8 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
-(define_expand "vec_cmpltgt"
-  [(match_operand 0 "register_operand" "")
-   (match_operand 1 "register_operand" "")
-   (match_operand 2 "register_operand" "")]
-  "TARGET_VX"
-{
-  if (GET_MODE (operands[1]) == V4SFmode)
-    emit_insn (gen_vec_cmpltgtv4sf (operands[0], operands[1], operands[2]));
-  else if (GET_MODE (operands[1]) == V2DFmode)
-    emit_insn (gen_vec_cmpltgtv2df (operands[0], operands[1], operands[2]));
-  else
-    gcc_unreachable ();
-
-  DONE;
-})
-
 ; ORDERED (a, b): a >= b | b > a
-(define_expand "vec_ordered<mode>"
+(define_expand "vec_cmpordered<mode>"
   [(set (match_operand:<tointvec>          0 "register_operand" "=v")
        (ge:<tointvec> (match_operand:VFT 1 "register_operand"  "v")
                 (match_operand:VFT 2 "register_operand"  "v")))
@@ -1528,45 +1496,32 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
-(define_expand "vec_ordered"
-  [(match_operand 0 "register_operand" "")
-   (match_operand 1 "register_operand" "")
-   (match_operand 2 "register_operand" "")]
-  "TARGET_VX"
-{
-  if (GET_MODE (operands[1]) == V4SFmode)
-    emit_insn (gen_vec_orderedv4sf (operands[0], operands[1], operands[2]));
-  else if (GET_MODE (operands[1]) == V2DFmode)
-    emit_insn (gen_vec_orderedv2df (operands[0], operands[1], operands[2]));
-  else
-    gcc_unreachable ();
-
-  DONE;
-})
-
 ; UNORDERED (a, b): !ORDERED (a, b)
-(define_expand "vec_unordered<mode>"
+(define_expand "vec_cmpunordered<mode>"
   [(match_operand:<tointvec> 0 "register_operand" "=v")
    (match_operand:VFT        1 "register_operand" "v")
    (match_operand:VFT        2 "register_operand" "v")]
   "TARGET_VX"
 {
-  emit_insn (gen_vec_ordered<mode> (operands[0], operands[1], operands[2]));
+  emit_insn (gen_vec_cmpordered<mode> (operands[0], operands[1], operands[2]));
   emit_insn (gen_rtx_SET (operands[0],
             gen_rtx_NOT (<tointvec>mode, operands[0])));
   DONE;
 })
 
-(define_expand "vec_unordered"
+(define_code_iterator VEC_CMP_EXPAND
+  [uneq ltgt ordered unordered])
+
+(define_expand "vec_cmp<code>"
   [(match_operand 0 "register_operand" "")
-   (match_operand 1 "register_operand" "")
-   (match_operand 2 "register_operand" "")]
+   (VEC_CMP_EXPAND (match_operand 1 "register_operand" "")
+                   (match_operand 2 "register_operand" ""))]
   "TARGET_VX"
 {
   if (GET_MODE (operands[1]) == V4SFmode)
-    emit_insn (gen_vec_unorderedv4sf (operands[0], operands[1], operands[2]));
+    emit_insn (gen_vec_cmp<code>v4sf (operands[0], operands[1], operands[2]));
   else if (GET_MODE (operands[1]) == V2DFmode)
-    emit_insn (gen_vec_unorderedv2df (operands[0], operands[1], operands[2]));
+    emit_insn (gen_vec_cmp<code>v2df (operands[0], operands[1], operands[2]));
   else
     gcc_unreachable ();