D: Support for Freescale Total5200 platform
W: http://www.mobilegt.com/
+N: Mark Jonas
+E: mark.jonas@de.bosch.com
+D: Support for MPR2 board
+
N: Sam Song
E: samsongshu@yahoo.com.cn
D: Port to the RPXlite_DW board
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
+D: Support for ColdFire MCF5275
N: Michal Simek
E: monstr@monstr.eu
bunbinga PPC405EP
canyonlands PPC460EX
ebony PPC440GP
+ glacier PPC460GT
haleakala PPC405EXr
katmai PPC440SPe
kilauea PPC405EX
TASREG MCF5249
-Zachary P. Landau <zachary.landau@labxtechnologies.com>
-
- r5200 mcf52x2
-
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
# Board CPU #
#########################################################################
-Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
MS7750SE SH7750
MS7722SE SH7722
+ R7780MP SH7780
+ R2DPlus SH7751R
+
+Mark Jonas <mark.jonas@de.bosch.com>
+
+ mpr2 SH7720
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
+Yusuke Goda <goda.yusuke@renesas.com>
+
+ MIGO-R SH7722
+
#########################################################################
# Blackfin Systems: #
# #
ERIC \
EXBITGEN \
G2000 \
+ glacier \
haleakala \
haleakala_nand \
hcu4 \
davinci_dvevm \
davinci_schmoogie \
davinci_sonata \
+ pmdra \
"
#########################################################################
cp1136 \
omap2420h4 \
apollon \
+ imx31_litekit \
+ imx31_phycore \
+ mx31ads \
"
#########################################################################
M5253EVB \
M5271EVB \
M5272C3 \
+ M5275EVB \
M5282EVB \
M5329AFEE \
M5373EVB \
M54455EVB \
M5475AFE \
M5485AFE \
- r5200 \
TASREG \
"
LIST_sh4=" \
ms7750se \
ms7722se \
+ Migo-R \
+ r7780mp \
+ r2dplus \
"
LIST_sh3=" \
+ mpr2 \
ms7720se \
"
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
-canyonlands_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc
+# Canyonlands & Glacier use different U-Boot images
+canyonlands_config \
+glacier_config: unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+ tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+ @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
canyonlands_nand_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/canyonlands
M5272C3_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
+M5275EVB_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale
+
M5282EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
TASREG_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
-r5200_config : unconfig
- @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
-
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \
davinci_sonata_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
+pmdra_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs pmdra prodrive davinci
+
omap1610inn_config \
omap1610inn_cs0boot_config \
omap1610inn_cs3boot_config \
## ARM1136 Systems
#########################################################################
omap2420h4_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
apollon_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
- @$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+ @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
+imx31_litekit_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
+
+imx31_phycore_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+
+mx31ads_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+
#========================================================================
# i386
#========================================================================
BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
- @$(MKCONFIG) $(@:_config=) blackfin $(firstword $(subst -, ,$@)) $(@:_config=)
+ @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
$(BFIN_BOARDS):
$(MAKE) $@_config
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
+mpr2_config: unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MPR2 1" >> include/config.h
+ @$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2
+
ms7720se_config: unconfig
@echo "#define CONFIG_MS7720SE 1" > include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se
@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se
+MigoR_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MIGO_R 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 MigoR
+
+r7780mp_config: unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_R7780MP 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 r7780mp
+
+r2dplus_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_R2DPLUS 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 r2dplus
+
#########################################################################
#########################################################################
#########################################################################
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
+ $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds \
+ $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
@rm -f $(obj)api_examples/demo $(VERSION_FILE)
CONFIG_E1000
Support for Intel 8254x gigabit chips.
+ CONFIG_E1000_FALLBACK_MAC
+ default MAC for empty eeprom after production.
+
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
of the "hostname" environment variable is passed as
option 12 to the DHCP server.
+ CONFIG_BOOTP_DHCP_REQUEST_DELAY
+
+ A 32bit value in microseconds for a delay between
+ receiving a "DHCP Offer" and sending the "DHCP Request".
+ This fixes a problem with certain DHCP servers that don't
+ respond 100% of the time to a "DHCP request". E.g. On an
+ AT91RM9200 processor running at 180MHz, this delay needed
+ to be *at least* 15,000 usec before a Windows Server 2003
+ DHCP server would reply 100% of the time. I recommend at
+ least 50,000 usec to be safe. The alternative is to hope
+ that one of the retries will be successful but note that
+ the DHCP timeout and retry process takes a longer than
+ this delay.
+
- CDP Options:
CONFIG_CDP_DEVICE_ID
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
+- CFG_MEM_TOP_HIDE (PPC only):
+ If CFG_MEM_TOP_HIDE is defined in the board config header,
+ this specified memory area will get subtracted from the top
+ (end) of ram and won't get "touched" at all by U-Boot. By
+ fixing up gd->ram_size the Linux kernel should gets passed
+ the now "corrected" memory size and won't touch it either.
+ This should work for arch/ppc and arch/powerpc. Only Linux
+ board ports in arch/powerpc with bootwrapper support that
+ recalculate the memory size from the SDRAM controller setup
+ will have to get fixed in Linux additionally.
+
+ This option can be used as a workaround for the 440EPx/GRx
+ CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
+ be touched.
+
+ WARNING: Please make sure that this value is a multiple of
+ the Linux page size (normally 4k). If this is not the case,
+ then the end address of the Linux memory will be located at a
+ non page size aligned address and this could cause major
+ problems.
+
- CFG_TFTP_LOADADDR:
Default load address for network file downloads
# MA 02111-1307 USA
#
+CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
+CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
+
PLATFORM_RELFLAGS += -ffixed-P5
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := migo_r.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
-# U-boot - config.mk
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# board/MigoR/config.mk
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
-PLATFORM_RELFLAGS += -mcpu=bf561
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D, r0 ! Instruction Cache Invalidate
+ mov.l r0, @r1
+
+ mov.l MMUCR_A, r1 ! Address of MMU Control Register
+ mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
+ mov.l r0, @r1
+
+ mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
+ mov.l MSTPCR0_D, r0 !
+ mov.l r0, @r1
+
+ mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
+ mov.l MSTPCR2_D, r0 !
+ mov.l r0, @r1
+
+ mov.l PFC_PULCR_A, r1
+ mov.w PFC_PULCR_D, r0
+ mov.w r0,@r1
+
+ mov.l PFC_DRVCR_A, r1
+ mov.w PFC_DRVCR_D, r0
+ mov.w r0, @r1
+
+ mov.l SBSCR_A, r1 !
+ mov.w SBSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l PSCR_A, r1 !
+ mov.w PSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
+ mov.w r0, @r1
+
+ mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
+ mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
+ mov.w r0, @r1
+
+ mov.l DLLFRQ_A, r1 ! 20080115
+ mov.l DLLFRQ_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
+ mov.l FRQCR_D, r0 ! 20080115
+ mov.l r0, @r1
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D_2, r0 ! ??
+ mov.l r0, @r1
+
+bsc_init:
+
+ mov.l CMNCR_A, r1 ! CMNCR address -> R1
+ mov.l CMNCR_D, r0 ! CMNCR data -> R0
+ mov.l r0, @r1 ! CMNCR set
+
+ mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
+ mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
+ mov.l r0, @r1 ! CS0BCR set
+
+ mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
+ mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
+ mov.l r0, @r1 ! CS4BCR set
+
+ mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
+ mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
+ mov.l r0, @r1 ! CS5ABCR set
+
+ mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
+ mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
+ mov.l r0, @r1 ! CS5BBCR set
+
+ mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
+ mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
+ mov.l r0, @r1 ! CS6ABCR set
+
+ mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
+ mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
+ mov.l r0, @r1 ! CS0WCR set
+
+ mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
+ mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
+ mov.l r0, @r1 ! CS4WCR set
+
+ mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
+ mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
+ mov.l r0, @r1 ! CS5AWCR set
+
+ mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
+ mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
+ mov.l r0, @r1 ! CS5BWCR set
+
+ mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
+ mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
+ mov.l r0, @r1 ! CS6AWCR set
+
+ ! SDRAM initialization
+ mov.l SDCR_A, r1 ! SB_SDCR address -> R1
+ mov.l SDCR_D, r0 ! SB_SDCR data -> R0
+ mov.l r0, @r1 ! SB_SDCR set
+
+ mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
+ mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
+ mov.l r0, @r1 ! SB_SDWCR set
+
+ mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
+ mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
+ mov.l r0, @r1 ! SB_SDPCR set
+
+ mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
+ mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
+ mov.l r0, @r1 ! SB_RTCOR set
+
+ mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
+ mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
+ mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
+ mov.l r0, @r1 ! SB_RTCSR set
+
+ mov.l RFCR_A, r1 ! SB_RFCR address -> R1
+ mov.l RFCR_D, r0 ! SB_RFCR data -> R0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1 ! SDMR3 address -> R1
+ mov #0x00, r0 ! SDMR3 data -> R0
+ mov.b r0, @r1 ! SDMR3 set
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+
+
+ .align 4
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+PFC_PULCR_A: .long PULCR
+PFC_DRVCR_A: .long DRVCR
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+PLLCR_A: .long PLLCR
+DLLFRQ_A: .long DLLFRQ
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+PFC_PULCR_D: .long 0x6000
+PFC_DRVCR_D: .long 0x0464
+FRQCR_D: .long 0x07033639
+PLLCR_D: .long 0x00005000
+DLLFRQ_D: .long 0x000004F6 ! 20080115
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x0000001B ! 20080115
+CS0BCR_A: .long CS0BCR ! Flash bank 1
+CS0BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR !
+CS4BCR_D: .long 0x10003400 ! 20080115
+CS5ABCR_A: .long CS5ABCR !
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR !
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR !
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000380
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00100A81 ! 20080115
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x80160809 ! 20080115
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x0014450C ! 20080115
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCNT_A: .long SBSC_RTCNT
+RTCNT_D: .long 0xA55A0012
+RTCOR_D: .long 0xA55A001C ! 20080115
+RTCSR_A: .long SBSC_RTCSR
+RFCR_A: .long SBSC_RFCR
+RFCR_D: .long 0xA55A0221
+RTCSR_D: .long 0xA55A009a ! 20080115
+SDMR3_A: .long 0xFE581180 ! 20080115
+
+SR_MASK_D: .long 0xEFFFFF0F
+
+ .align 2
+
+SBSCR_D: .word 0x0044
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA504 ! 20080115
+RWTCNT_D: .word 0x5A00
+
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas MigoR\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}
+
--- /dev/null
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
+
DECLARE_GLOBAL_DATA_PTR;
+#define CFG_BCSR3_PCIE 0x10
+
+#define BOARD_CANYONLANDS_PCIE 1
+#define BOARD_CANYONLANDS_SATA 2
+#define BOARD_GLACIER 3
+
int board_early_init_f(void)
{
u32 sdr0_cust0;
+ u32 pvr = get_pvr();
- /*------------------------------------------------------------------+
+ /*
* Setup the interrupt controller polarities, triggers, etc.
- *------------------------------------------------------------------*/
+ */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
- /*
- * Configure USB-STP pins as alternate and not GPIO
- * It seems to be neccessary to configure the STP pins as GPIO
- * input at powerup (perhaps while USB reset is asserted). So
- * we configure those pins to their "real" function now.
- */
- gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ }
return 0;
}
-int checkboard (void)
+static void canyonlands_sata_init(int board_type)
+{
+ u32 reg;
+
+ if (board_type == BOARD_CANYONLANDS_SATA) {
+ /* Put SATA in reset */
+ SDR_WRITE(SDR0_SRST1, 0x00020001);
+
+ /* Set the phy for SATA, not PCI-E port 0 */
+ reg = SDR_READ(PESDR0_PHY_CTL_RST);
+ SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
+ reg = SDR_READ(PESDR0_L0CLK);
+ SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
+ SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
+ SDR_WRITE(PESDR0_L0DRV, 0x00000104);
+
+ /* Bring SATA out of reset */
+ SDR_WRITE(SDR0_SRST1, 0x00000000);
+ }
+}
+
+int checkboard(void)
{
char *s = getenv("serial#");
u32 pvr = get_pvr();
- if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
+ if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
- else
+ gd->board_type = BOARD_GLACIER;
+ } else {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
+ if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
+ gd->board_type = BOARD_CANYONLANDS_PCIE;
+ else
+ gd->board_type = BOARD_CANYONLANDS_SATA;
+ }
+
+ switch (gd->board_type) {
+ case BOARD_CANYONLANDS_PCIE:
+ case BOARD_GLACIER:
+ puts(", 2*PCIe");
+ break;
+
+ case BOARD_CANYONLANDS_SATA:
+ puts(", 1*PCIe/1*SATA");
+ break;
+ }
+
+ printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
if (s != NULL) {
puts(", serial# ");
}
putc('\n');
+ canyonlands_sata_init(gd->board_type);
+
return (0);
}
}
#endif
-/*************************************************************************
+/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
- *
- ************************************************************************/
+ */
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
- /*-------------------------------------------------------------------+
+ /*
* Disable everything
- *-------------------------------------------------------------------*/
+ */
out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
- /*-------------------------------------------------------------------+
+ /*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
+ */
out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
- /*-------------------------------------------------------------------+
+ /*
* Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
+ */
out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
int ret = 0;
char *env;
unsigned int delay;
+ int start;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
- for (i = 0; i <= 1; i++) {
+
+ /*
+ * Canyonlands with SATA enabled has only one PCIe slot
+ * (2nd one).
+ */
+ if (gd->board_type == BOARD_CANYONLANDS_SATA)
+ start = 1;
+ else
+ start = 0;
+
+ for (i = start; i <= 1; i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
+ u32 pvr = get_pvr();
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
- eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+ eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ else
+ eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
mtsdr(SDR0_ETH_CFG, eth_cfg);
/*
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
+ val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
val, sizeof(val), 1);
*(COMMON)
}
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
_end = . ;
PROVIDE (end = .);
}
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
-# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
-TEXT_BASE = 0x01FC0000
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
+
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
+MEMORY
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- . = CFG_MONITOR_BASE;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector before the environment sector. If it throws */
- /* an error during compilation remove an object here to get */
- /* it linked after the configuration sector. */
+ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
- cpu/bf533/start.o (.text)
- cpu/bf533/start1.o (.text)
- cpu/bf533/traps.o (.text)
- cpu/bf533/interrupt.o (.text)
- cpu/bf533/serial.o (.text)
- common/dlmalloc.o (.text)
-/* lib_blackfin/bf533_string.o (.text) */
-/* lib_generic/vsprintf.o (.text) */
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- board/bf533-ezkit/bf533-ezkit.o (.text)
+SECTIONS
+{
+ .text :
+ {
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
- . = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ cpu/blackfin/start.o (.text)
+ cpu/blackfin/traps.o (.text)
+ cpu/blackfin/interrupt.o (.text)
+ cpu/blackfin/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ board/bf533-ezkit/bf533-ezkit.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+#endif
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ *(.text .text.*)
+ } >ram
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
- ___u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- ___u_boot_cmd_end = .;
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
}
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o spi.o
+COBJS := $(BOARD).o spi_flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
-# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
-TEXT_BASE = 0x07FC0000
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+++ /dev/null
-/****************************************************************************
- * SPI flash driver for M25P64
- ****************************************************************************/
-#include <common.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/spi.h>
-
-#if defined(CONFIG_SPI)
-
- /*Application definitions */
-
-#define NUM_SECTORS 128 /* number of sectors */
-#define SECTOR_SIZE 0x10000
-#define NOP_NUM 1000
-
-#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /*Settings to the SPI_CTL */
-#define TIMOD01 (0x01) /*stes the SPI to work with core instructions */
-
- /*Flash commands */
-#define SPI_WREN (0x06) /*Set Write Enable Latch */
-#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
-#define SPI_RDSR (0x05) /*Read Status Register */
-#define SPI_WRSR (0x01) /*Write Status Register */
-#define SPI_READ (0x03) /*Read data from memory */
-#define SPI_PP (0x02) /*Program Data into memory */
-#define SPI_SE (0xD8) /*Erase one sector in memory */
-#define SPI_BE (0xC7) /*Erase all memory */
-#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
-#define WEL (0x2) /*Check the write enable bit of the SPI status register */
-
-#define TIMEOUT 350000000
-
-typedef enum {
- NO_ERR,
- POLL_TIMEOUT,
- INVALID_SECTOR,
- INVALID_BLOCK,
-} ERROR_CODE;
-
-void spi_init_f(void);
-void spi_init_r(void);
-ssize_t spi_read(uchar *, int, uchar *, int);
-ssize_t spi_write(uchar *, int, uchar *, int);
-
-char ReadStatusRegister(void);
-void Wait_For_SPIF(void);
-void SetupSPI(const int spi_setting);
-void SPI_OFF(void);
-void SendSingleCommand(const int iCommand);
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
-ERROR_CODE EraseBlock(int nBlock);
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE Wait_For_Status(char Statusbit);
-ERROR_CODE Wait_For_WEL(void);
-
-/* -------------------
- * Variables
- * ------------------- */
-
-/* **************************************************************************
- *
- * Function: spi_init_f
- *
- * Description: Init SPI-Controller (ROM part)
- *
- * return: ---
- *
- * *********************************************************************** */
-void spi_init_f(void)
-{
-}
-
-/* **************************************************************************
- *
- * Function: spi_init_r
- *
- * Description: Init SPI-Controller (RAM part) -
- * The malloc engine is ready and we can move our buffers to
- * normal RAM
- *
- * return: ---
- *
- * *********************************************************************** */
-void spi_init_r(void)
-{
- return;
-}
-
-/****************************************************************************
- * Function: spi_write
- **************************************************************************** */
-ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
-{
- unsigned long offset;
- int start_block, end_block;
- int start_byte, end_byte;
- ERROR_CODE result = NO_ERR;
- uchar temp[SECTOR_SIZE];
- int i, num;
-
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
- /* Get the start block number */
- result = GetSectorNumber(offset, &start_block);
- if (result == INVALID_SECTOR) {
- printf("Invalid sector! ");
- return 0;
- }
- /* Get the end block number */
- result = GetSectorNumber(offset + len - 1, &end_block);
- if (result == INVALID_SECTOR) {
- printf("Invalid sector! ");
- return 0;
- }
-
- for (num = start_block; num <= end_block; num++) {
- ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
- start_byte = num * SECTOR_SIZE;
- end_byte = (num + 1) * SECTOR_SIZE - 1;
- if (start_byte < offset)
- start_byte = offset;
- if (end_byte > (offset + len))
- end_byte = (offset + len - 1);
- for (i = start_byte; i <= end_byte; i++)
- temp[i - num * SECTOR_SIZE] = buffer[i - offset];
- EraseBlock(num);
- result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
- if (result != NO_ERR)
- return 0;
- printf(".");
- }
- return len;
-}
-
-/****************************************************************************
- * Function: spi_read
- **************************************************************************** */
-ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
-{
- unsigned long offset;
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
- ReadData(offset, len, (int *)buffer);
- return len;
-}
-
-void SendSingleCommand(const int iCommand)
-{
- unsigned short dummy;
-
- /*turns on the SPI in single write mode */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
- /*sends the actual command to the SPI TX register */
- *pSPI_TDBR = iCommand;
- SSYNC();
-
- /*The SPI status register will be polled to check the SPIF bit */
- Wait_For_SPIF();
-
- dummy = *pSPI_RDBR;
-
- /*The SPI will be turned off */
- SPI_OFF();
-
-}
-
-void SetupSPI(const int spi_setting)
-{
-
- if (icache_status() || dcache_status())
- udelay(CONFIG_CCLK_HZ / 50000000);
- /*sets up the PF2 to be the slave select of the SPI */
- *pSPI_FLG = 0xFB04;
- *pSPI_BAUD = CONFIG_SPI_BAUD;
- *pSPI_CTL = spi_setting;
- SSYNC();
-}
-
-void SPI_OFF(void)
-{
-
- *pSPI_CTL = 0x0400; /* disable SPI */
- *pSPI_FLG = 0;
- *pSPI_BAUD = 0;
- SSYNC();
- udelay(CONFIG_CCLK_HZ / 50000000);
-
-}
-
-void Wait_For_SPIF(void)
-{
- unsigned short dummyread;
- while ((*pSPI_STAT & TXS)) ;
- while (!(*pSPI_STAT & SPIF)) ;
- while (!(*pSPI_STAT & RXS)) ;
- dummyread = *pSPI_RDBR; /* Read dummy to empty the receive register */
-
-}
-
-ERROR_CODE Wait_For_WEL(void)
-{
- int i;
- char status_register = 0;
- ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
-
- for (i = 0; i < TIMEOUT; i++) {
- status_register = ReadStatusRegister();
- if ((status_register & WEL)) {
- ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
- break;
- }
- ErrorCode = POLL_TIMEOUT; /* Time out error */
- };
-
- return ErrorCode;
-}
-
-ERROR_CODE Wait_For_Status(char Statusbit)
-{
- int i;
- char status_register = 0xFF;
- ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
-
- for (i = 0; i < TIMEOUT; i++) {
- status_register = ReadStatusRegister();
- if (!(status_register & Statusbit)) {
- ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
- break;
- }
- ErrorCode = POLL_TIMEOUT; /* Time out error */
- };
-
- return ErrorCode;
-}
-
-char ReadStatusRegister(void)
-{
- char status_register = 0;
-
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
-
- *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- *pSPI_TDBR = 0; /*send dummy to receive the status register */
- SSYNC();
- Wait_For_SPIF(); /*wait until the data has been sent */
- status_register = *pSPI_RDBR; /*read the status register */
-
- SPI_OFF(); /* Turn off the SPI */
-
- return status_register;
-}
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
-{
- int nSector = 0;
- ERROR_CODE ErrorCode = NO_ERR;
-
- if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
- ErrorCode = INVALID_SECTOR;
- return ErrorCode;
- }
-
- nSector = (int)ulOffset / 0x10000;
- *pnSector = nSector;
-
- /* ok */
- return ErrorCode;
-}
-
-ERROR_CODE EraseBlock(int nBlock)
-{
- unsigned long ulSectorOff = 0x0, ShiftValue;
- ERROR_CODE ErrorCode = NO_ERR;
-
- /* if the block is invalid just return */
- if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
- ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
- return ErrorCode;
- }
- /* figure out the offset of the block in flash */
- if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
- ulSectorOff = (nBlock * SECTOR_SIZE);
-
- } else {
- ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
- return ErrorCode;
- }
-
- /* A write enable instruction must previously have been executed */
- SendSingleCommand(SPI_WREN);
-
- /*The status register will be polled to check the write enable latch "WREN" */
- ErrorCode = Wait_For_WEL();
-
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Erase block error\n");
- return ErrorCode;
- } else
- /*Turn on the SPI to send single commands */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
- /* Send the erase block command to the flash followed by the 24 address */
- /* to point to the start of a sector. */
- *pSPI_TDBR = SPI_SE;
- SSYNC();
- Wait_For_SPIF();
- ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
- ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
- *pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
-
- /*Turns off the SPI */
- SPI_OFF();
-
- /* Poll the status register to check the Write in Progress bit */
- /* Sector erase takes time */
- ErrorCode = Wait_For_Status(WIP);
-
- /* block erase should be complete */
- return ErrorCode;
-}
-
-/*****************************************************************************
-* ERROR_CODE ReadData()
-*
-* Read a value from flash for verify purpose
-*
-* Inputs: unsigned long ulStart - holds the SPI start address
-* int pnData - pointer to store value read from flash
-* long lCount - number of elements to read
-***************************************************************************** */
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
-{
- unsigned long ShiftValue;
- char *cnData;
- int i;
-
- cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
-
- /* Start SPI interface */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
- *pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
- ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
- *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
- ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
- *pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
- *pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
- SSYNC();
- Wait_For_SPIF(); /* Wait until the instruction has been sent */
-
- /* After the SPI device address has been placed on the MOSI pin the data can be */
- /* received on the MISO pin. */
- for (i = 0; i < lCount; i++) {
- *pSPI_TDBR = 0; /*send dummy */
- SSYNC();
- while (!(*pSPI_STAT & RXS)) ;
- *cnData++ = *pSPI_RDBR; /*read */
-
- if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
- printf(".");
- }
-
- SPI_OFF(); /* Turn off the SPI */
-
- return NO_ERR;
-}
-
-ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
- int *iDataSource, long *lWriteCount)
-{
-
- unsigned long ulWAddr;
- long lWTransferCount = 0;
- int i;
- char iData;
- char *temp = (char *)iDataSource;
- ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
-
- /* First, a Write Enable Command must be sent to the SPI. */
- SendSingleCommand(SPI_WREN);
-
- /* Second, the SPI Status Register will be tested whether the */
- /* Write Enable Bit has been set. */
- ErrorCode = Wait_For_WEL();
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Write Time Out\n");
- return ErrorCode;
- } else
- /* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
- *pSPI_TDBR = SPI_PP;
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- ulWAddr = (ulStartAddr >> 16);
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- ulWAddr = (ulStartAddr >> 8);
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- ulWAddr = ulStartAddr;
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- /* Fourth, maximum number of 256 bytes will be taken from the Buffer */
- /* and sent to the SPI device. */
- for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
- iData = *temp;
- *pSPI_TDBR = iData;
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- temp++;
- }
-
- SPI_OFF(); /* Turns the SPI off */
-
- /* Sixth, the SPI Write in Progress Bit must be toggled to ensure the */
- /* programming is done before start of next transfer. */
- ErrorCode = Wait_For_Status(WIP);
-
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Program Time out!\n");
- return ErrorCode;
- } else
-
- *lWriteCount = lWTransferCount;
-
- return ErrorCode;
-}
-
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
-{
-
- unsigned long ulWStart = ulStart;
- long lWCount = lCount, lWriteCount;
- long *pnWriteCount = &lWriteCount;
-
- ERROR_CODE ErrorCode = NO_ERR;
-
- while (lWCount != 0) {
- ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
-
- /* After each function call of WriteFlash the counter must be adjusted */
- lWCount -= *pnWriteCount;
-
- /* Also, both address pointers must be recalculated. */
- ulWStart += *pnWriteCount;
- pnData += *pnWriteCount / 4;
- }
-
- /* return the appropriate error code */
- return ErrorCode;
-}
-
-#endif /* CONFIG_SPI */
--- /dev/null
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
+
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
+MEMORY
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- . = CFG_MONITOR_BASE;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector before the environment sector. If it throws */
- /* an error during compilation remove an object here to get */
- /* it linked after the configuration sector. */
+ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
- cpu/bf533/start.o (.text)
- cpu/bf533/start1.o (.text)
- cpu/bf533/traps.o (.text)
- cpu/bf533/interrupt.o (.text)
- cpu/bf533/serial.o (.text)
- common/dlmalloc.o (.text)
-/* lib_blackfin/bf533_string.o (.text) */
-/* lib_generic/vsprintf.o (.text) */
- lib_generic/crc32.o (.text)
-/* lib_generic/zlib.o (.text) */
-/* board/stamp/stamp.o (.text) */
+SECTIONS
+{
+ .text :
+ {
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
- . = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ cpu/blackfin/start.o (.text)
+ cpu/blackfin/traps.o (.text)
+ cpu/blackfin/interrupt.o (.text)
+ cpu/blackfin/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+#endif
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ *(.text .text.*)
+ } >ram
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
- ___u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- ___u_boot_cmd_end = .;
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
}
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
+COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#if defined(CONFIG_CMD_NET)
char nid[32];
unsigned char *pMACaddr = (unsigned char *)0x203F0000;
- u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
-#if defined(CONFIG_CMD_NET)
/* The 0xFF check here is to make sure we don't use the address
* in flash if it's simply been erased (aka all 0xFF values) */
if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
setenv("ethaddr", nid);
}
#endif
-#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
#if defined(CONFIG_BFIN_IDE)
#if defined(CONFIG_BFIN_TRUE_IDE)
#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_POST
-#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
-/* Using sw10-PF5 as the hotkey */
-int post_hotkeys_pressed(void)
-{
- return 0;
-}
-#else
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
}
}
#endif
-#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store(ulong a)
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
-# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
-TEXT_BASE = 0x03FC0000
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
--- /dev/null
+/*
+ * SPI flash driver
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Configuration options:
+ * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK)
+ * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read
+ * WARNING: make sure your SCLK + SPI_BAUD is slow enough
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
+
+/* Forcibly phase out these */
+#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
+# error do not set CONFIG_SPI_FLASH_NUM_SECTORS
+#endif
+#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE
+# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE
+#endif
+
+#if defined(CONFIG_SPI)
+
+struct flash_info {
+ char *name;
+ uint16_t id;
+ unsigned sector_size;
+ unsigned num_sectors;
+};
+
+/* SPI Speeds: 50 MHz / 33 MHz */
+static struct flash_info flash_spansion_serial_flash[] = {
+ { "S25FL016", 0x0215, 64 * 1024, 32 },
+ { "S25FL032", 0x0216, 64 * 1024, 64 },
+ { "S25FL064", 0x0217, 64 * 1024, 128 },
+ { "S25FL0128", 0x0218, 256 * 1024, 64 },
+ { NULL, 0, 0, 0 }
+};
+
+/* SPI Speeds: 50 MHz / 20 MHz */
+static struct flash_info flash_st_serial_flash[] = {
+ { "m25p05", 0x2010, 32 * 1024, 2 },
+ { "m25p10", 0x2011, 32 * 1024, 4 },
+ { "m25p20", 0x2012, 64 * 1024, 4 },
+ { "m25p40", 0x2013, 64 * 1024, 8 },
+ { "m25p16", 0x2015, 64 * 1024, 32 },
+ { "m25p32", 0x2016, 64 * 1024, 64 },
+ { "m25p64", 0x2017, 64 * 1024, 128 },
+ { "m25p128", 0x2018, 256 * 1024, 64 },
+ { NULL, 0, 0, 0 }
+};
+
+/* SPI Speeds: 66 MHz / 33 MHz */
+static struct flash_info flash_atmel_dataflash[] = {
+ { "AT45DB011x", 0x0c, 264, 512 },
+ { "AT45DB021x", 0x14, 264, 1025 },
+ { "AT45DB041x", 0x1c, 264, 2048 },
+ { "AT45DB081x", 0x24, 264, 4096 },
+ { "AT45DB161x", 0x2c, 528, 4096 },
+ { "AT45DB321x", 0x34, 528, 8192 },
+ { "AT45DB642x", 0x3c, 1056, 8192 },
+ { NULL, 0, 0, 0 }
+};
+
+/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
+static struct flash_info flash_winbond_serial_flash[] = {
+ { "W25X10", 0x3011, 16 * 256, 32 },
+ { "W25X20", 0x3012, 16 * 256, 64 },
+ { "W25X40", 0x3013, 16 * 256, 128 },
+ { "W25X80", 0x3014, 16 * 256, 256 },
+ { "W25P80", 0x2014, 256 * 256, 16 },
+ { "W25P16", 0x2015, 256 * 256, 32 },
+ { NULL, 0, 0, 0 }
+};
+
+struct flash_ops {
+ uint8_t read, write, erase, status;
+};
+
+#ifdef CONFIG_SPI_FLASH_SLOW_READ
+# define OP_READ 0x03
+#else
+# define OP_READ 0x0B
+#endif
+static struct flash_ops flash_st_ops = {
+ .read = OP_READ,
+ .write = 0x02,
+ .erase = 0xD8,
+ .status = 0x05,
+};
+
+static struct flash_ops flash_atmel_ops = {
+ .read = OP_READ,
+ .write = 0x82,
+ .erase = 0x81,
+ .status = 0xD7,
+};
+
+static struct flash_ops flash_winbond_ops = {
+ .read = OP_READ,
+ .write = 0x02,
+ .erase = 0x20,
+ .status = 0x05,
+};
+
+struct manufacturer_info {
+ const char *name;
+ uint8_t id;
+ struct flash_info *flashes;
+ struct flash_ops *ops;
+};
+
+static struct {
+ struct manufacturer_info *manufacturer;
+ struct flash_info *flash;
+ struct flash_ops *ops;
+ uint8_t manufacturer_id, device_id1, device_id2;
+ unsigned int write_length;
+ unsigned long sector_size, num_sectors;
+} flash;
+
+enum {
+ JED_MANU_SPANSION = 0x01,
+ JED_MANU_ST = 0x20,
+ JED_MANU_ATMEL = 0x1F,
+ JED_MANU_WINBOND = 0xEF,
+};
+
+static struct manufacturer_info flash_manufacturers[] = {
+ {
+ .name = "Spansion",
+ .id = JED_MANU_SPANSION,
+ .flashes = flash_spansion_serial_flash,
+ .ops = &flash_st_ops,
+ },
+ {
+ .name = "ST",
+ .id = JED_MANU_ST,
+ .flashes = flash_st_serial_flash,
+ .ops = &flash_st_ops,
+ },
+ {
+ .name = "Atmel",
+ .id = JED_MANU_ATMEL,
+ .flashes = flash_atmel_dataflash,
+ .ops = &flash_atmel_ops,
+ },
+ {
+ .name = "Winbond",
+ .id = JED_MANU_WINBOND,
+ .flashes = flash_winbond_serial_flash,
+ .ops = &flash_winbond_ops,
+ },
+};
+
+#define TIMEOUT 5000 /* timeout of 5 seconds */
+
+/* BF54x support */
+#ifndef pSPI_CTL
+# define pSPI_CTL pSPI0_CTL
+# define pSPI_BAUD pSPI0_BAUD
+# define pSPI_FLG pSPI0_FLG
+# define pSPI_RDBR pSPI0_RDBR
+# define pSPI_STAT pSPI0_STAT
+# define pSPI_TDBR pSPI0_TDBR
+# define SPI0_SCK 0x0001
+# define SPI0_MOSI 0x0004
+# define SPI0_MISO 0x0002
+# define SPI0_SEL1 0x0010
+#endif
+
+/* Default to the SPI SSEL that we boot off of:
+ * BF54x, BF537, (everything new?): SSEL1
+ * BF533, BF561: SSEL2
+ */
+#ifndef CONFIG_SPI_FLASH_SSEL
+# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || defined(__ADSPBF561__)
+# define CONFIG_SPI_FLASH_SSEL 2
+# else
+# define CONFIG_SPI_FLASH_SSEL 1
+# endif
+#endif
+#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
+
+static void SPI_INIT(void)
+{
+ /* [#3541] This delay appears to be necessary, but not sure
+ * exactly why as the history behind it is non-existant.
+ */
+ udelay(CONFIG_CCLK_HZ / 25000000);
+
+ /* enable SPI pins: SSEL, MOSI, MISO, SCK */
+#ifdef __ADSPBF54x__
+ *pPORTE_FER |= (SPI0_SCK | SPI0_MOSI | SPI0_MISO | SPI0_SEL1);
+#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
+ *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
+#elif defined(__ADSPBF52x__)
+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3);
+ bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4);
+#endif
+
+ /* initate communication upon write of TDBR */
+ *pSPI_CTL = (SPE|MSTR|CPHA|CPOL|0x01);
+ *pSPI_BAUD = CONFIG_SPI_BAUD;
+}
+
+static void SPI_DEINIT(void)
+{
+ /* put SPI settings back to reset state */
+ *pSPI_CTL = 0x0400;
+ *pSPI_BAUD = 0;
+ SSYNC();
+}
+
+static void SPI_ON(void)
+{
+ /* toggle SSEL to reset the device so it'll take a new command */
+ *pSPI_FLG = 0xFF00 | SSEL_MASK;
+ SSYNC();
+
+ *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK;
+ SSYNC();
+}
+
+static void SPI_OFF(void)
+{
+ /* put SPI settings back to reset state */
+ *pSPI_FLG = 0xFF00;
+ SSYNC();
+}
+
+static uint8_t spi_write_read_byte(uint8_t transmit)
+{
+ *pSPI_TDBR = transmit;
+ SSYNC();
+
+ while ((*pSPI_STAT & TXS))
+ if (ctrlc())
+ break;
+ while (!(*pSPI_STAT & SPIF))
+ if (ctrlc())
+ break;
+ while (!(*pSPI_STAT & RXS))
+ if (ctrlc())
+ break;
+
+ /* Read dummy to empty the receive register */
+ return *pSPI_RDBR;
+}
+
+static uint8_t read_status_register(void)
+{
+ uint8_t status_register;
+
+ /* send instruction to read status register */
+ SPI_ON();
+ spi_write_read_byte(flash.ops->status);
+ /* send dummy to receive the status register */
+ status_register = spi_write_read_byte(0);
+ SPI_OFF();
+
+ return status_register;
+}
+
+static int wait_for_ready_status(void)
+{
+ ulong start = get_timer(0);
+
+ while (get_timer(0) - start < TIMEOUT) {
+ switch (flash.manufacturer_id) {
+ case JED_MANU_SPANSION:
+ case JED_MANU_ST:
+ case JED_MANU_WINBOND:
+ if (!(read_status_register() & 0x01))
+ return 0;
+ break;
+
+ case JED_MANU_ATMEL:
+ if (read_status_register() & 0x80)
+ return 0;
+ break;
+ }
+
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return -1;
+ }
+ }
+
+ puts("Timeout\n");
+ return -1;
+}
+
+/* Request and read the manufacturer and device id of parts which
+ * are compatible with the JEDEC standard (JEP106) and use that to
+ * setup other operating conditions.
+ */
+static int spi_detect_part(void)
+{
+ uint16_t dev_id;
+ size_t i;
+
+ static char called_init;
+ if (called_init)
+ return 0;
+
+ SPI_ON();
+
+ /* Send the request for the part identification */
+ spi_write_read_byte(0x9F);
+
+ /* Now read in the manufacturer id bytes */
+ do {
+ flash.manufacturer_id = spi_write_read_byte(0);
+ if (flash.manufacturer_id == 0x7F)
+ puts("Warning: unhandled manufacturer continuation byte!\n");
+ } while (flash.manufacturer_id == 0x7F);
+
+ /* Now read in the first device id byte */
+ flash.device_id1 = spi_write_read_byte(0);
+
+ /* Now read in the second device id byte */
+ flash.device_id2 = spi_write_read_byte(0);
+
+ SPI_OFF();
+
+ dev_id = (flash.device_id1 << 8) | flash.device_id2;
+
+ for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
+ if (flash.manufacturer_id == flash_manufacturers[i].id)
+ break;
+ }
+ if (i == ARRAY_SIZE(flash_manufacturers))
+ goto unknown;
+
+ flash.manufacturer = &flash_manufacturers[i];
+ flash.ops = flash_manufacturers[i].ops;
+
+ switch (flash.manufacturer_id) {
+ case JED_MANU_SPANSION:
+ case JED_MANU_ST:
+ case JED_MANU_WINBOND:
+ for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
+ if (dev_id == flash.manufacturer->flashes[i].id)
+ break;
+ }
+ if (!flash.manufacturer->flashes[i].name)
+ goto unknown;
+
+ flash.flash = &flash.manufacturer->flashes[i];
+ flash.sector_size = flash.flash->sector_size;
+ flash.num_sectors = flash.flash->num_sectors;
+ flash.write_length = 256;
+ break;
+
+ case JED_MANU_ATMEL: {
+ uint8_t status = read_status_register();
+
+ for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
+ if ((status & 0x3c) == flash.manufacturer->flashes[i].id)
+ break;
+ }
+ if (!flash.manufacturer->flashes[i].name)
+ goto unknown;
+
+ flash.flash = &flash.manufacturer->flashes[i];
+ flash.sector_size = flash.flash->sector_size;
+ flash.num_sectors = flash.flash->num_sectors;
+
+ /* see if flash is in "power of 2" mode */
+ if (status & 0x1)
+ flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1));
+
+ flash.write_length = flash.sector_size;
+ break;
+ }
+ }
+
+ called_init = 1;
+ return 0;
+
+ unknown:
+ printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n",
+ flash.manufacturer_id, flash.device_id1, flash.device_id2);
+ return 1;
+}
+
+/*
+ * Function: spi_init_f
+ * Description: Init SPI-Controller (ROM part)
+ * return: ---
+ */
+void spi_init_f(void)
+{
+}
+
+/*
+ * Function: spi_init_r
+ * Description: Init SPI-Controller (RAM part) -
+ * The malloc engine is ready and we can move our buffers to
+ * normal RAM
+ * return: ---
+ */
+void spi_init_r(void)
+{
+#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI)
+ /* Our testing strategy here is pretty basic:
+ * - fill src memory with an 8-bit pattern
+ * - write the src memory to the SPI flash
+ * - read the SPI flash into the dst memory
+ * - compare src and dst memory regions
+ * - repeat a few times
+ * The variations we test for:
+ * - change the 8-bit pattern a bit
+ * - change the read/write block size so we know:
+ * - writes smaller/equal/larger than the buffer work
+ * - writes smaller/equal/larger than the sector work
+ * - change the SPI offsets so we know:
+ * - writing partial sectors works
+ */
+ uint8_t *mem_src, *mem_dst;
+ size_t i, c, l, o;
+ size_t test_count, errors;
+ uint8_t pattern;
+
+ SPI_INIT();
+
+ if (spi_detect_part())
+ goto out;
+ eeprom_info();
+
+ ulong lengths[] = {
+ flash.write_length,
+ flash.write_length * 2,
+ flash.write_length / 2,
+ flash.sector_size,
+ flash.sector_size * 2,
+ flash.sector_size / 2
+ };
+ ulong offsets[] = {
+ 0,
+ flash.write_length,
+ flash.write_length * 2,
+ flash.write_length / 2,
+ flash.write_length / 4,
+ flash.sector_size,
+ flash.sector_size * 2,
+ flash.sector_size / 2,
+ flash.sector_size / 4,
+ };
+
+ /* the exact addresses are arbitrary ... they just need to not overlap */
+ mem_src = (void *)(0);
+ mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2);
+
+ test_count = 0;
+ errors = 0;
+ pattern = 0x00;
+
+ for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */
+ for (l = 0; l < ARRAY_SIZE(lengths); ++l) {
+ for (o = 0; o < ARRAY_SIZE(offsets); ++o) {
+ ulong len = lengths[l];
+ ulong off = offsets[o];
+
+ printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off);
+
+ /* setup the source memory region */
+ memset(mem_src, pattern, len);
+
+ test_count += 4;
+ for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ goto out;
+ }
+
+ /* make sure background fill pattern != pattern */
+ memset(mem_dst, pattern ^ 0xFF, len);
+
+ /* write out the source memory and then read it back and compare */
+ eeprom_write(0, off, mem_src, len);
+ eeprom_read(0, off, mem_dst, len);
+
+ if (memcmp(mem_src, mem_dst, len)) {
+ for (c = 0; c < len; ++c)
+ if (mem_src[c] != mem_dst[c])
+ break;
+ printf(" FAIL @ offset %u, skipping repeats ", c);
+ ++errors;
+ break;
+ }
+
+ /* XXX: should shrink write region here to test with
+ * leading/trailing canaries so we know surrounding
+ * bytes don't get screwed.
+ */
+ }
+ puts("\n");
+ }
+ }
+
+ /* invert the pattern every other run and shift out bits slowly */
+ pattern ^= 0xFF;
+ if (i % 2)
+ pattern = (pattern | 0x01) << 1;
+ }
+
+ if (errors)
+ printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors);
+ else
+ printf("SPI PASS: %i tests worked!\n", test_count);
+
+ out:
+ SPI_DEINIT();
+
+#endif
+}
+
+static void transmit_address(uint32_t addr)
+{
+ /* Send the highest byte of the 24 bit address at first */
+ spi_write_read_byte(addr >> 16);
+ /* Send the middle byte of the 24 bit address at second */
+ spi_write_read_byte(addr >> 8);
+ /* Send the lowest byte of the 24 bit address finally */
+ spi_write_read_byte(addr);
+}
+
+/*
+ * Read a value from flash for verify purpose
+ * Inputs: unsigned long ulStart - holds the SPI start address
+ * int pnData - pointer to store value read from flash
+ * long lCount - number of elements to read
+ */
+static int read_flash(unsigned long address, long count, uchar *buffer)
+{
+ size_t i;
+
+ /* Send the read command to SPI device */
+ SPI_ON();
+ spi_write_read_byte(flash.ops->read);
+ transmit_address(address);
+
+#ifndef CONFIG_SPI_FLASH_SLOW_READ
+ /* Send dummy byte when doing SPI fast reads */
+ spi_write_read_byte(0);
+#endif
+
+ /* After the SPI device address has been placed on the MOSI pin the data can be */
+ /* received on the MISO pin. */
+ for (i = 1; i <= count; ++i) {
+ *buffer++ = spi_write_read_byte(0);
+ if (i % flash.sector_size == 0)
+ puts(".");
+ }
+
+ SPI_OFF();
+
+ return 0;
+}
+
+static int enable_writing(void)
+{
+ ulong start;
+
+ if (flash.manufacturer_id == JED_MANU_ATMEL)
+ return 0;
+
+ /* A write enable instruction must previously have been executed */
+ SPI_ON();
+ spi_write_read_byte(0x06);
+ SPI_OFF();
+
+ /* The status register will be polled to check the write enable latch "WREN" */
+ start = get_timer(0);
+ while (get_timer(0) - start < TIMEOUT) {
+ if (read_status_register() & 0x02)
+ return 0;
+
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return -1;
+ }
+ }
+
+ puts("Timeout\n");
+ return -1;
+}
+
+static long address_to_sector(unsigned long address)
+{
+ if (address > (flash.num_sectors * flash.sector_size) - 1)
+ return -1;
+ return address / flash.sector_size;
+}
+
+static int erase_sector(int address)
+{
+ /* sector gets checked in higher function, so assume it's valid
+ * here and figure out the offset of the sector in flash
+ */
+ if (enable_writing())
+ return -1;
+
+ /*
+ * Send the erase block command to the flash followed by the 24 address
+ * to point to the start of a sector
+ */
+ SPI_ON();
+ spi_write_read_byte(flash.ops->erase);
+ transmit_address(address);
+ SPI_OFF();
+
+ return wait_for_ready_status();
+}
+
+/* Write [count] bytes out of [buffer] into the given SPI [address] */
+static long write_flash(unsigned long address, long count, uchar *buffer)
+{
+ long i, write_buffer_size;
+
+ if (enable_writing())
+ return -1;
+
+ /* Send write command followed by the 24 bit address */
+ SPI_ON();
+ spi_write_read_byte(flash.ops->write);
+ transmit_address(address);
+
+ /* Shoot out a single write buffer */
+ write_buffer_size = min(count, flash.write_length);
+ for (i = 0; i < write_buffer_size; ++i)
+ spi_write_read_byte(buffer[i]);
+
+ SPI_OFF();
+
+ /* Wait for the flash to do its thing */
+ if (wait_for_ready_status()) {
+ puts("SPI Program Time out! ");
+ return -1;
+ }
+
+ return i;
+}
+
+/* Write [count] bytes out of [buffer] into the given SPI [address] */
+static int write_sector(unsigned long address, long count, uchar *buffer)
+{
+ long write_cnt;
+
+ while (count != 0) {
+ write_cnt = write_flash(address, count, buffer);
+ if (write_cnt == -1)
+ return -1;
+
+ /* Now that we've sent some bytes out to the flash, update
+ * our counters a bit
+ */
+ count -= write_cnt;
+ address += write_cnt;
+ buffer += write_cnt;
+ }
+
+ /* return the appropriate error code */
+ return 0;
+}
+
+/*
+ * Function: spi_write
+ */
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
+{
+ unsigned long offset;
+ int start_sector, end_sector;
+ int start_byte, end_byte;
+ uchar *temp = NULL;
+ int num, ret = 0;
+
+ SPI_INIT();
+
+ if (spi_detect_part())
+ goto out;
+
+ offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+
+ /* Get the start block number */
+ start_sector = address_to_sector(offset);
+ if (start_sector == -1) {
+ puts("Invalid sector! ");
+ goto out;
+ }
+ end_sector = address_to_sector(offset + len - 1);
+ if (end_sector == -1) {
+ puts("Invalid sector! ");
+ goto out;
+ }
+
+ /* Since flashes operate in sector units but the eeprom command
+ * operates as a continuous stream of bytes, we need to emulate
+ * the eeprom behavior. So here we read in the sector, overlay
+ * any bytes we're actually modifying, erase the sector, and
+ * then write back out the new sector.
+ */
+ temp = malloc(flash.sector_size);
+ if (!temp) {
+ puts("Malloc for sector failed! ");
+ goto out;
+ }
+
+ for (num = start_sector; num <= end_sector; num++) {
+ unsigned long address = num * flash.sector_size;
+
+ /* XXX: should add an optimization when spanning sectors:
+ * No point in reading in a sector if we're going to be
+ * clobbering the whole thing. Need to also add a test
+ * case to make sure the optimization is correct.
+ */
+ if (read_flash(address, flash.sector_size, temp)) {
+ puts("Read sector failed! ");
+ len = 0;
+ break;
+ }
+
+ start_byte = max(address, offset);
+ end_byte = address + flash.sector_size - 1;
+ if (end_byte > (offset + len))
+ end_byte = (offset + len - 1);
+
+ memcpy(temp + start_byte - address,
+ buffer + start_byte - offset,
+ end_byte - start_byte + 1);
+
+ if (erase_sector(address)) {
+ puts("Erase sector failed! ");
+ goto out;
+ }
+
+ if (write_sector(address, flash.sector_size, temp)) {
+ puts("Write sector failed! ");
+ goto out;
+ }
+
+ puts(".");
+ }
+
+ ret = len;
+
+ out:
+ free(temp);
+
+ SPI_DEINIT();
+
+ return ret;
+}
+
+/*
+ * Function: spi_read
+ */
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
+{
+ unsigned long offset;
+
+ SPI_INIT();
+
+ if (spi_detect_part())
+ len = 0;
+ else {
+ offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+ read_flash(offset, len, buffer);
+ }
+
+ SPI_DEINIT();
+
+ return len;
+}
+
+/*
+ * Spit out some useful information about the SPI eeprom
+ */
+int eeprom_info(void)
+{
+ int ret = 0;
+
+ SPI_INIT();
+
+ if (spi_detect_part())
+ ret = 1;
+ else
+ printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
+ "Parameters: num sectors = %i, sector size = %i, write size = %i\n"
+ "Flash Size: %i mbit (%i mbyte)\n"
+ "Status: 0x%02X\n",
+ flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
+ flash.device_id1, flash.device_id2, flash.num_sectors,
+ flash.sector_size, flash.write_length,
+ (flash.num_sectors * flash.sector_size) >> 17,
+ (flash.num_sectors * flash.sector_size) >> 20,
+ read_status_register());
+
+ SPI_DEINIT();
+
+ return ret;
+}
+
+#endif
+++ /dev/null
-/****************************************************************************
- * SPI flash driver for M25P64
- ****************************************************************************/
-#include <common.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/spi.h>
-
-#if defined(CONFIG_SPI)
-
-/* Application definitions */
-
-#define NUM_SECTORS 128 /* number of sectors */
-#define SECTOR_SIZE 0x10000
-#define NOP_NUM 1000
-
-#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
-#define TIMOD01 (0x01) /* stes the SPI to work with core instructions */
-
-/* Flash commands */
-#define SPI_WREN (0x06) /*Set Write Enable Latch */
-#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
-#define SPI_RDSR (0x05) /*Read Status Register */
-#define SPI_WRSR (0x01) /*Write Status Register */
-#define SPI_READ (0x03) /*Read data from memory */
-#define SPI_FAST_READ (0x0B) /*Read data from memory */
-#define SPI_PP (0x02) /*Program Data into memory */
-#define SPI_SE (0xD8) /*Erase one sector in memory */
-#define SPI_BE (0xC7) /*Erase all memory */
-#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
-#define WEL (0x2) /*Check the write enable bit of the SPI status register */
-
-#define TIMEOUT 350000000
-
-typedef enum {
- NO_ERR,
- POLL_TIMEOUT,
- INVALID_SECTOR,
- INVALID_BLOCK,
-} ERROR_CODE;
-
-void spi_init_f(void);
-void spi_init_r(void);
-ssize_t spi_read(uchar *, int, uchar *, int);
-ssize_t spi_write(uchar *, int, uchar *, int);
-
-char ReadStatusRegister(void);
-void Wait_For_SPIF(void);
-void SetupSPI(const int spi_setting);
-void SPI_OFF(void);
-void SendSingleCommand(const int iCommand);
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
-ERROR_CODE EraseBlock(int nBlock);
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
-ERROR_CODE Wait_For_Status(char Statusbit);
-ERROR_CODE Wait_For_WEL(void);
-
-/*
- * Function: spi_init_f
- * Description: Init SPI-Controller (ROM part)
- * return: ---
- */
-void spi_init_f(void)
-{
-}
-
-/*
- * Function: spi_init_r
- * Description: Init SPI-Controller (RAM part) -
- * The malloc engine is ready and we can move our buffers to
- * normal RAM
- * return: ---
- */
-void spi_init_r(void)
-{
- return;
-}
-
-/*
- * Function: spi_write
- */
-ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
-{
- unsigned long offset;
- int start_block, end_block;
- int start_byte, end_byte;
- ERROR_CODE result = NO_ERR;
- uchar temp[SECTOR_SIZE];
- int i, num;
-
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
- /* Get the start block number */
- result = GetSectorNumber(offset, &start_block);
- if (result == INVALID_SECTOR) {
- printf("Invalid sector! ");
- return 0;
- }
- /* Get the end block number */
- result = GetSectorNumber(offset + len - 1, &end_block);
- if (result == INVALID_SECTOR) {
- printf("Invalid sector! ");
- return 0;
- }
-
- for (num = start_block; num <= end_block; num++) {
- ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
- start_byte = num * SECTOR_SIZE;
- end_byte = (num + 1) * SECTOR_SIZE - 1;
- if (start_byte < offset)
- start_byte = offset;
- if (end_byte > (offset + len))
- end_byte = (offset + len - 1);
- for (i = start_byte; i <= end_byte; i++)
- temp[i - num * SECTOR_SIZE] = buffer[i - offset];
- EraseBlock(num);
- result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
- if (result != NO_ERR)
- return 0;
- printf(".");
- }
- return len;
-}
-
-/*
- * Function: spi_read
- */
-ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
-{
- unsigned long offset;
- offset = addr[0] << 16 | addr[1] << 8 | addr[2];
- ReadData(offset, len, (int *)buffer);
- return len;
-}
-
-void SendSingleCommand(const int iCommand)
-{
- unsigned short dummy;
-
- /* turns on the SPI in single write mode */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
- /* sends the actual command to the SPI TX register */
- *pSPI_TDBR = iCommand;
- SSYNC();
-
- /* The SPI status register will be polled to check the SPIF bit */
- Wait_For_SPIF();
-
- dummy = *pSPI_RDBR;
-
- /* The SPI will be turned off */
- SPI_OFF();
-
-}
-
-void SetupSPI(const int spi_setting)
-{
-
- if (icache_status() || dcache_status())
- udelay(CONFIG_CCLK_HZ / 50000000);
- /*sets up the PF10 to be the slave select of the SPI */
- *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
- *pSPI_FLG = 0xFF02;
- *pSPI_BAUD = CONFIG_SPI_BAUD;
- *pSPI_CTL = spi_setting;
- SSYNC();
-
- *pSPI_FLG = 0xFD02;
- SSYNC();
-}
-
-void SPI_OFF(void)
-{
-
- *pSPI_CTL = 0x0400; /* disable SPI */
- *pSPI_FLG = 0;
- *pSPI_BAUD = 0;
- SSYNC();
- udelay(CONFIG_CCLK_HZ / 50000000);
-
-}
-
-void Wait_For_SPIF(void)
-{
- unsigned short dummyread;
- while ((*pSPI_STAT & TXS)) ;
- while (!(*pSPI_STAT & SPIF)) ;
- while (!(*pSPI_STAT & RXS)) ;
- /* Read dummy to empty the receive register */
- dummyread = *pSPI_RDBR;
-}
-
-ERROR_CODE Wait_For_WEL(void)
-{
- int i;
- char status_register = 0;
- ERROR_CODE ErrorCode = NO_ERR;
-
- for (i = 0; i < TIMEOUT; i++) {
- status_register = ReadStatusRegister();
- if ((status_register & WEL)) {
- ErrorCode = NO_ERR;
- break;
- }
- ErrorCode = POLL_TIMEOUT; /* Time out error */
- };
-
- return ErrorCode;
-}
-
-ERROR_CODE Wait_For_Status(char Statusbit)
-{
- int i;
- char status_register = 0xFF;
- ERROR_CODE ErrorCode = NO_ERR;
-
- for (i = 0; i < TIMEOUT; i++) {
- status_register = ReadStatusRegister();
- if (!(status_register & Statusbit)) {
- ErrorCode = NO_ERR;
- break;
- }
- ErrorCode = POLL_TIMEOUT; /* Time out error */
- };
-
- return ErrorCode;
-}
-
-char ReadStatusRegister(void)
-{
- char status_register = 0;
-
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
-
- *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
- SSYNC();
- Wait_For_SPIF(); /*wait until the instruction has been sent */
- *pSPI_TDBR = 0; /*send dummy to receive the status register */
- SSYNC();
- Wait_For_SPIF(); /*wait until the data has been sent */
- status_register = *pSPI_RDBR; /*read the status register */
-
- SPI_OFF(); /* Turn off the SPI */
-
- return status_register;
-}
-
-ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
-{
- int nSector = 0;
- ERROR_CODE ErrorCode = NO_ERR;
-
- if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
- ErrorCode = INVALID_SECTOR;
- return ErrorCode;
- }
-
- nSector = (int)ulOffset / 0x10000;
- *pnSector = nSector;
-
- return ErrorCode;
-}
-
-ERROR_CODE EraseBlock(int nBlock)
-{
- unsigned long ulSectorOff = 0x0, ShiftValue;
- ERROR_CODE ErrorCode = NO_ERR;
-
- /* if the block is invalid just return */
- if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
- ErrorCode = INVALID_BLOCK;
- return ErrorCode;
- }
- /* figure out the offset of the block in flash */
- if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
- ulSectorOff = (nBlock * SECTOR_SIZE);
-
- } else {
- ErrorCode = INVALID_BLOCK;
- return ErrorCode;
- }
-
- /* A write enable instruction must previously have been executed */
- SendSingleCommand(SPI_WREN);
-
- /* The status register will be polled to check the write enable latch "WREN" */
- ErrorCode = Wait_For_WEL();
-
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Erase block error\n");
- return ErrorCode;
- } else
-
- /* Turn on the SPI to send single commands */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
- /*
- * Send the erase block command to the flash followed by the 24 address
- * to point to the start of a sector
- */
- *pSPI_TDBR = SPI_SE;
- SSYNC();
- Wait_For_SPIF();
- /* Send the highest byte of the 24 bit address at first */
- ShiftValue = (ulSectorOff >> 16);
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
- /* Send the middle byte of the 24 bit address at second */
- ShiftValue = (ulSectorOff >> 8);
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
- /* Send the lowest byte of the 24 bit address finally */
- *pSPI_TDBR = ulSectorOff;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
-
- /* Turns off the SPI */
- SPI_OFF();
-
- /* Poll the status register to check the Write in Progress bit */
- /* Sector erase takes time */
- ErrorCode = Wait_For_Status(WIP);
-
- /* block erase should be complete */
- return ErrorCode;
-}
-
-/*
- * ERROR_CODE ReadData()
- * Read a value from flash for verify purpose
- * Inputs: unsigned long ulStart - holds the SPI start address
- * int pnData - pointer to store value read from flash
- * long lCount - number of elements to read
- */
-ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
-{
- unsigned long ShiftValue;
- char *cnData;
- int i;
-
- /* Pointer cast to be able to increment byte wise */
-
- cnData = (char *)pnData;
- /* Start SPI interface */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
-
-#ifdef CONFIG_SPI_FLASH_FAST_READ
- /* Send the read command to SPI device */
- *pSPI_TDBR = SPI_FAST_READ;
-#else
- /* Send the read command to SPI device */
- *pSPI_TDBR = SPI_READ;
-#endif
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
- /* Send the highest byte of the 24 bit address at first */
- ShiftValue = (ulStart >> 16);
- /* Send the byte to the SPI device */
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
- /* Send the middle byte of the 24 bit address at second */
- ShiftValue = (ulStart >> 8);
- /* Send the byte to the SPI device */
- *pSPI_TDBR = ShiftValue;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
- /* Send the lowest byte of the 24 bit address finally */
- *pSPI_TDBR = ulStart;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
-
-#ifdef CONFIG_SPI_FLASH_FAST_READ
- /* Send dummy for FAST_READ */
- *pSPI_TDBR = 0;
- SSYNC();
- /* Wait until the instruction has been sent */
- Wait_For_SPIF();
-#endif
-
- /* After the SPI device address has been placed on the MOSI pin the data can be */
- /* received on the MISO pin. */
- for (i = 0; i < lCount; i++) {
- *pSPI_TDBR = 0;
- SSYNC();
- while (!(*pSPI_STAT & RXS)) ;
- *cnData++ = *pSPI_RDBR;
-
- if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
- printf(".");
- }
-
- /* Turn off the SPI */
- SPI_OFF();
-
- return NO_ERR;
-}
-
-ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
- int *iDataSource, long *lWriteCount)
-{
-
- unsigned long ulWAddr;
- long lWTransferCount = 0;
- int i;
- char iData;
- char *temp = (char *)iDataSource;
- ERROR_CODE ErrorCode = NO_ERR;
-
- /* First, a Write Enable Command must be sent to the SPI. */
- SendSingleCommand(SPI_WREN);
-
- /*
- * Second, the SPI Status Register will be tested whether the
- * Write Enable Bit has been set
- */
- ErrorCode = Wait_For_WEL();
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Write Time Out\n");
- return ErrorCode;
- } else
- /* Third, the 24 bit address will be shifted out
- * the SPI MOSI bytewise.
- * Turns the SPI on
- */
- SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
- *pSPI_TDBR = SPI_PP;
- SSYNC();
- /*wait until the instruction has been sent */
- Wait_For_SPIF();
- ulWAddr = (ulStartAddr >> 16);
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- /*wait until the instruction has been sent */
- Wait_For_SPIF();
- ulWAddr = (ulStartAddr >> 8);
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- /*wait until the instruction has been sent */
- Wait_For_SPIF();
- ulWAddr = ulStartAddr;
- *pSPI_TDBR = ulWAddr;
- SSYNC();
- /*wait until the instruction has been sent */
- Wait_For_SPIF();
- /*
- * Fourth, maximum number of 256 bytes will be taken from the Buffer
- * and sent to the SPI device.
- */
- for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
- iData = *temp;
- *pSPI_TDBR = iData;
- SSYNC();
- /*wait until the instruction has been sent */
- Wait_For_SPIF();
- temp++;
- }
-
- /* Turns the SPI off */
- SPI_OFF();
-
- /*
- * Sixth, the SPI Write in Progress Bit must be toggled to ensure the
- * programming is done before start of next transfer
- */
- ErrorCode = Wait_For_Status(WIP);
-
- if (POLL_TIMEOUT == ErrorCode) {
- printf("SPI Program Time out!\n");
- return ErrorCode;
- } else
-
- *lWriteCount = lWTransferCount;
-
- return ErrorCode;
-}
-
-ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
-{
-
- unsigned long ulWStart = ulStart;
- long lWCount = lCount, lWriteCount;
- long *pnWriteCount = &lWriteCount;
-
- ERROR_CODE ErrorCode = NO_ERR;
-
- while (lWCount != 0) {
- ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
-
- /*
- * After each function call of WriteFlash the counter
- * must be adjusted
- */
- lWCount -= *pnWriteCount;
-
- /* Also, both address pointers must be recalculated. */
- ulWStart += *pnWriteCount;
- pnData += *pnWriteCount / 4;
- }
-
- /* return the appropriate error code */
- return ErrorCode;
-}
-
-#endif /* CONFIG_SPI */
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
- {
- ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
- l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
- l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
- }
+{
+ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
SECTIONS
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS; /*0x1000;*/
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- . = CFG_MONITOR_BASE;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector before the environment sector. If it throws */
- /* an error during compilation remove an object here to get */
- /* it linked after the configuration sector. */
-
- cpu/bf537/start.o (.text)
- cpu/bf537/start1.o (.text)
- cpu/bf537/traps.o (.text)
- cpu/bf537/interrupt.o (.text)
- cpu/bf537/serial.o (.text)
- common/dlmalloc.o (.text)
-/* lib_blackfin/bf533_string.o (.text) */
-/* lib_generic/vsprintf.o (.text) */
- lib_generic/crc32.o (.text)
-/* lib_generic/zlib.o (.text) */
-/* board/bf537-stamp/bf537-stamp.o (.text) */
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
-
- *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
- *(.fixup)
- *(.got1)
- } > ram
- _etext = .;
- PROVIDE (etext = .);
- .text_l1 :
- {
- . = ALIGN(4) ;
- _text_l1 = .;
- PROVIDE (text_l1 = .);
- board/bf537-stamp/post-memory.o (.text)
- . = ALIGN(4) ;
- _etext_l1 = .;
- PROVIDE (etext_l1 = .);
- } > l1_code AT > ram
-
- .rodata :
- {
- . = ALIGN(4);
- *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
- *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
- *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
- *(.eh_frame)
- . = ALIGN(4);
- } > ram
-
- . = ALIGN(4);
- _erodata = .;
- PROVIDE (erodata = .);
- .rodata_l1 :
- {
- . = ALIGN(4) ;
- _rodata_l1 = .;
- PROVIDE (rodata_l1 = .);
- board/bf537-stamp/post-memory.o (.rodata)
- board/bf537-stamp/post-memory.o (.rodata1)
- board/bf537-stamp/post-memory.o (.rodata.str1.4)
- . = ALIGN(4) ;
- _erodata_l1 = .;
- PROVIDE(erodata_l1 = .);
- } > l1_data AT > ram
-
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- } > ram
- _edata = .;
- PROVIDE (edata = .);
-
- ___u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) } > ram
- ___u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- .bss :
- {
- __bss_start = .;
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- } > ram
- _end = . ;
- PROVIDE (end = .);
+ .text :
+ {
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/start.o (.text)
+ cpu/blackfin/traps.o (.text)
+ cpu/blackfin/interrupt.o (.text)
+ cpu/blackfin/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+#endif
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
}
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
-# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
-TEXT_BASE = 0x03FC0000
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2007 Analog Device Inc.
+ * Copyright (c) 2005-2008 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
OUTPUT_ARCH(bfin)
-OUTPUT_ARCH(bfin)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
+
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
+MEMORY
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- . = CFG_MONITOR_BASE;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector before the environment sector. If it throws */
- /* an error during compilation remove an object here to get */
- /* it linked after the configuration sector. */
+ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
- cpu/bf561/start.o (.text)
- cpu/bf561/start1.o (.text)
- cpu/bf561/traps.o (.text)
- cpu/bf561/interrupt.o (.text)
- cpu/bf561/serial.o (.text)
- common/dlmalloc.o (.text)
-/* lib_blackfin/bf533_string.o (.text) */
-/* lib_generic/vsprintf.o (.text) */
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- board/bf561-ezkit/bf561-ezkit.o (.text)
+SECTIONS
+{
+ .text :
+ {
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
- . = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ cpu/blackfin/start.o (.text)
+ cpu/blackfin/traps.o (.text)
+ cpu/blackfin/interrupt.o (.text)
+ cpu/blackfin/serial.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ board/bf561-ezkit/bf561-ezkit.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+#endif
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ *(.text .text.*)
+ } >ram
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
- ___u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- ___u_boot_cmd_end = .;
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
}
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
CFG_GPIO1_IORSTN |
+ CFG_GPIO1_IORST2N |
CFG_GPIO1_LEDUSR1 |
CFG_GPIO1_LEDUSR2 |
CFG_GPIO1_LEDPOST |
CFG_GPIO1_LEDDU);
out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
-
out_be32((void*)GPIO1_OSRL, 0x5c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
out_be32((void*)GPIO1_TSRL, 0x0c000000);
* release IO-RST#
* We have to wait at least 560ms until we may call usbhub_init
*/
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
+ CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
/*
* flash USR1/2 LEDs (600ms)
#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
#define CFG_GPIO1_HWVER_SHIFT 4
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*
*/
-
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "pmc440.h"
int is_monarch(void);
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt);
int eeprom_write_enable(unsigned dev_addr, int state);
DECLARE_GLOBAL_DATA_PTR;
return rc;
}
-
int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
NULL
);
-
void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
{
u32 ctrl;
}
}
-
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
got_fifoirq = 0;
/* unmask global fifo irq */
FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+ HOSTCTRL_FIFOIE_GATE |
+ HOSTCTRL_FIFOIE_FLAG);
}
}
for (i=0; i<n; i++)
FPGA_OUT32(&fpga->fifo[f].data, data);
} else {
- printf("writing %d x %08x to fifo port at address %08x\n",
+ printf("writing %d x %08x to fifo port at "
+ "address %08x\n",
n, data, f);
for (i=0; i<n; i++)
out32(f, data);
" - without arguments: print all fifo's status\n"
" - with 'wait' argument: interrupt driven read from all fifos\n"
" - with 'read' argument: read current contents from all fifos\n"
- " - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
+ " - with 'write' argument: write 'data' 'cnt' times to "
+ "'fifo' or 'address'\n"
);
-
int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong sdsdp[5];
sdsdp[2]=0x40082350;
sdsdp[3]=0x0d050000;
} else if (!strcmp(argv[1], "test")) {
- /* TODO: this will replace the 667 MHz config above.
+ /*
+ * TODO: this will replace the 667 MHz config above.
* But it needs some more testing on a real 667 MHz CPU.
*/
- printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
+ printf("Bootstrapping for test"
+ " (667MHz PLB=133PLB PLB/PCI=3)\n");
sdsdp[0]=0x8778a256;
sdsdp[1]=0x095fa030;
sdsdp[2]=0x40082350;
"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
);
-
#if defined(CONFIG_PRAM)
#include <environment.h>
extern env_t *env_ptr;
);
#endif /* CONFIG_PRAM */
-
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc > 1) {
NULL
);
-
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
/* deassert */
printf("PMC-RESETOUT# deasserted\n");
FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
+ HOSTCTRL_PMCRSTOUT_GATE |
+ HOSTCTRL_PMCRSTOUT_FLAG);
}
} else {
printf("PMC-RESETOUT# is %s\n",
NULL
);
-
int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (is_monarch()) {
in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
}
} else {
- printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
+ printf("inta# is %s\n",
+ in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
+ "active" : "inactive");
}
return 0;
}
NULL
);
-
/* test-only */
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pciaddr &= 0xf0000000;
/* map PCI address at 0xc0000000 in PLB space */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
- out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
+
+ /* PMM1 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1MA, 0x00000000);
+ /* PMM1 Local Address */
+ out32r(PCIX0_PMM1LA, 0xc0000000);
+ /* PMM1 PCI Low Address */
+ out32r(PCIX0_PMM1PCILA, pciaddr);
+ /* PMM1 PCI High Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000);
+ /* 256MB + No prefetching, and enable region */
+ out32r(PCIX0_PMM1MA, 0xf0000001);
} else {
printf("Usage:\npmm %s\n", cmdtp->help);
}
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
* Based on board/amcc/sequoia/sequoia.c
*
#include <ppc440.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/bitops.h>
#include <command.h>
#include <i2c.h>
#ifdef CONFIG_RESET_PHY_R
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size(ulong base, int banknum);
int pci_is_66mhz(void);
-int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
-
+int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt);
struct serial_device *default_serial_console(void)
{
/* mark scratchreg valid */
scratchreg = (scratchreg & 0xffffff00) | 0x80;
- i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
+ i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0x10, buf, 4);
if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
scratchreg |= buf[2];
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xf8400000);
- /*--------------------------------------------------------------------
+ /*
* Setup the GPIO pins
* TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
- *-------------------------------------------------------------------*/
+ */
out32(GPIO0_OR, 0x40000002);
out32(GPIO0_TCR, 0x4c90011f);
out32(GPIO0_OSRL, 0x28011400);
mtspr(dbcr0, 0x20000000); /* do chip reset */
}
- /*--------------------------------------------------------------------
+ /*
* Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
+ */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
/* enable 2nd IIC */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
return 0;
}
-/*---------------------------------------------------------------------------+
- | misc_init_r.
- +---------------------------------------------------------------------------*/
+/*
+ * misc_init_r.
+ */
int misc_init_r(void)
{
uint pbcr;
mtdcr(ebccfga, pb0cr);
#endif
pbcr = mfdcr(ebccfgd);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb2cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- /* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /*clear resets*/
+ /* clear resets */
udelay(1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay(1000);
printf("USB: Host\n");
- } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- /*-------------------PATCH-------------------------------*/
+ } else if ((strcmp(act, "dev") == 0) ||
+ (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000);
udelay (1000);
mtsdr(SDR0_SRST1, 0x60306000);
- /*-------------------PATCH-------------------------------*/
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
}
#endif
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
+/*
+ * pci_pre_init
*
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
*
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
+/*
+ * pci_target_init
*
- ************************************************************************/
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
- /*--------------------------------------------------------------------------+
+ char *ptmla_str, *ptmms_str;
+
+ /*
* Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0x80000000-0xBFFFFFFF
+ * ==> PCI address 0x80000000-0xBFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */
+ out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
+ /* and enable region */
if (!is_monarch()) {
- /* BAR1: top 64MB of RAM */
- out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */
+ ptmla_str = getenv("ptm1la");
+ ptmms_str = getenv("ptm1ms");
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ out32r(PCIX0_PTM1MS,
+ simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIX0_PTM1LA,
+ simple_strtoul(ptmla_str, NULL, 16));
+ } else {
+ /* BAR1: default top 64MB of RAM */
+ out32r(PCIX0_PTM1MS, 0xfc000001);
+ out32r(PCIX0_PTM1LA, 0x0c000000);
+ }
} else {
- /* BAR1: complete 256MB RAM (TODO: make dynamic) */
- out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */
+ /* BAR1: default: complete 256MB RAM */
+ out32r(PCIX0_PTM1MS, 0xf0000001);
+ out32r(PCIX0_PTM1LA, 0x00000000);
}
- /* BAR2: 16 MB FPGA registers */
- out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+ ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
+ ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+ } else {
+ /* BAR2: default: 16 MB FPGA + registers */
+ out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+ }
if (is_monarch()) {
/* BAR2: map FPGA registers behind system memory at 1GB */
pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
}
- /*--------------------------------------------------------------------------+
+ /*
* Set up Configuration registers
- *--------------------------------------------------------------------------*/
+ */
/* Program the board's vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
-#if 0 /* disabled for PMC405 backward compatibility */
+ /* disabled for PMC405 backward compatibility */
/* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-#endif
+ /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
+
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
CFG_PCI_CLASSCODE_NONMONARCH);
/* PCI configuration done: release ERREADY */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
- out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
+ out_be32((void*)GPIO1_TCR,
+ in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
} else {
/* Program the board's subsystem id/classcode */
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
+/*
+ * pci_master_init
+ */
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
if (is_monarch()) {
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-
static void wait_for_pci_ready(void)
{
int i;
}
}
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
+/*
+ * is_pci_host
*
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
*
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
*
- ************************************************************************/
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
return 0;
}
#endif /* defined(CONFIG_PCI) */
+
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
}
#endif /* CONFIG_POST */
-
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#endif
#if defined(CFG_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
* 0: disable write
* 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable(unsigned dev_addr, int state)
{
- if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
+ (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
return -1;
} else {
switch (state) {
}
#endif /* #if defined(CFG_EEPROM_WREN) */
-
#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
{
unsigned end = offset + cnt;
unsigned blk_off;
#if defined(CFG_EEPROM_WREN)
eeprom_write_enable(dev_addr, 1);
#endif
- /* Write data until done or would cross a write page boundary.
+ /*
+ * Write data until done or would cross a write page boundary.
* We must write the address again when changing pages
* because the address counter only increments within a page.
*/
#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
- maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
if (maxlen > I2C_RXTX_LEN)
maxlen = I2C_RXTX_LEN;
return rcode;
}
-
-int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
{
unsigned end = offset + cnt;
unsigned blk_off;
int rcode = 0;
- /* Read data until done or would cross a page boundary.
+ /*
+ * Read data until done or would cross a page boundary.
* We must write the address again when changing pages
* because the next page may be in a different device.
*/
return rcode;
}
-
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
if ((act == NULL || strcmp(act, "hostdev") == 0) &&
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
/* enable power on USB socket */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
for (i=0; i<1000; i++)
udelay(1000);
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o mii.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0x10000000
+TEXT_BASE = 0xffe00000
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+#define PERIOD 13 /* system bus period in ns */
+#define SDRAM_TREFI 7800 /* in ns */
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5275 EVB\n");
+ return 0;
+};
+
+long int initdram(int board_type)
+{
+ volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+ gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+
+ /* Set up chip select */
+ sdp->sdbar0 = CFG_SDRAM_BASE;
+ sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+
+ /* Set up timing */
+ sdp->sdcfg1 = 0x83711630;
+ sdp->sdcfg2 = 0x46770000;
+
+ /* Enable clock */
+ sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LEMR */
+ sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
+ | MCF_SDRAMC_SDMR_AD(0x0)
+ | MCF_SDRAMC_SDMR_CMD;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LMR */
+ sdp->sdmr = 0x058d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+
+ /* Set precharge */
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop manual precharge, send 2 IREF */
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
+ sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Write mode register, clear reset DLL */
+ sdp->sdmr = 0x018d0000;
+ *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+
+ /* Turn on auto refresh, lock SDMR */
+ sdp->sdcr =
+ MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_MUX(1)
+ /* 1 added to round up */
+ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
int fecpin_setclear(struct eth_device *dev, int setclear)
{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
} else {
+ if (info->iobase == CFG_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
}
return 0;
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
+#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/string.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+#define STM_ID_M25P16 0x20152015
+#define FLASH_M25P16 0x0055
+#endif
+
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
+int serial_flash_read_status(int chipsel);
+static int ser_flash_cs = 0;
+#endif
+
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
ulong size = 0;
ulong fbase = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ dspi_init();
+#endif
+
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 2:
+ fbase = (ulong) CFG_FLASH2_BASE;
+ break;
+#endif
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
{
int i, j, k;
int sectors, bs, banks;
- ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+ info->start[0] = CFG_FLASH2_BASE;
+ for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
+ info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
+ info->protect[k] = 0;
+ }
+ }
+#endif
return ERR_OK;
}
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ printf("ST ");
+ break;
+#endif
default:
printf("Unknown Vendor ");
break;
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
- printf("Intel 28F128J3A\n");
+ printf("28F128J3A\n");
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_M25P16:
+ printf("M25P16\n");
break;
+#endif
default:
printf("Unknown Chip Type\n");
return;
u16 value;
int i;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ if ((ulong) addr == CFG_FLASH2_BASE) {
+ int manufactId = 0;
+ int deviceId = 0;
+
+ ser_flash_cs = 1;
+
+ dspi_tx(ser_flash_cs, 0x80, SER_RDID);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+
+ dspi_rx();
+ manufactId = dspi_rx();
+ deviceId = dspi_rx() << 8;
+ deviceId |= dspi_rx();
+
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ switch (manufactId) {
+ case (u8) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ }
+
+ switch (deviceId) {
+ case (u16) STM_ID_M25P16:
+ info->flash_id += FLASH_M25P16;
+ break;
+ }
+
+ info->sector_count = CFG_STM_SECT;
+ info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
+
+ return (info->size);
+ }
+#endif
+
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
return (int)addr[index];
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int serial_flash_read_status(int chipsel)
+{
+ u16 status;
+
+ dspi_tx(chipsel, 0x80, SER_RDSR);
+ dspi_rx();
+
+ dspi_tx(chipsel, 0x00, 0);
+ status = dspi_rx();
+
+ return status;
+}
+#endif
+
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
{
int flag, prot, sect;
ulong type, start, last;
- int rcode = 0, intel = 0;
-
+ int rcode = 0, flashtype = 0;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ int count;
+ u16 status;
+#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
type = (info->flash_id & FLASH_VENDMASK);
- if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
- if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
- type = (info->flash_id & FLASH_VENDMASK);
- printf
- ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
+ switch (type) {
+ case FLASH_MAN_ATM:
+ flashtype = 1;
+ break;
+ case FLASH_MAN_INTEL:
+ flashtype = 2;
+ break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ flashtype = 3;
+ break;
+#endif
+ default:
+ type = (info->flash_id & FLASH_VENDMASK);
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
}
- if (type == FLASH_MAN_INTEL)
- intel = 1;
-
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
start = get_timer(0);
last = start;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ /* Perform bulk erase */
+ if (flashtype == 3) {
+ if ((s_last - s_first) == (CFG_STM_SECT - 1)) {
+ if (prot == 0) {
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Can't erase flash\n");
+ return 1;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE);
+ dspi_rx();
+
+ count = 0;
+ start = get_timer(0);
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (count++ > 0x10000) {
+ spin_wheel();
+ count = 0;
+ }
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ printf("\b. done\n");
+ return 0;
+ } else if (prot == CFG_STM_SECT) {
+ return 1;
+ }
+ }
+ }
+#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
- if (intel) {
- *addr = (FPW) INTEL_READID;
- min = addr[INTEL_CFI_TERB] & 0xff;
- min = 1 << min; /* ms */
- min = (min / info->sector_count) * 1000;
-
- /* start erase block */
- *addr = (FPW) INTEL_CLEAR; /* clear status register */
- *addr = (FPW) INTEL_ERASE; /* erase setup */
- *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
-
- while ((*addr & (FPW) INTEL_FINISHED) !=
- (FPW) INTEL_FINISHED) {
-
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
- *addr = (FPW) INTEL_RESET; /* reset to read mode */
-
- rcode = 1;
- break;
+ switch (flashtype) {
+ case 1:
+ {
+ FPWV *base; /* first address in bank */
+ FPWV *atmeladdr;
+
+ flag = disable_interrupts();
+
+ atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
+ base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ *atmeladdr = (u8) 0x00300030; /* erase sector */
+
+ if (flag)
+ enable_interrupts();
+
+ while ((*atmeladdr & (u8) 0x00800080) !=
+ (u8) 0x00800080) {
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
}
- }
-
- *addr = (FPW) INTEL_RESET; /* resest to read mode */
- } else {
- FPWV *base; /* first address in bank */
- FPWV *atmeladdr;
-
- flag = disable_interrupts();
- atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
- base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
-
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
- *atmeladdr = (u8) 0x00300030; /* erase sector */
+ *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ break;
+ }
- if (flag)
- enable_interrupts();
+ case 2:
+ {
+ *addr = (FPW) INTEL_READID;
+ min = addr[INTEL_CFI_TERB] & 0xff;
+ min = 1 << min; /* ms */
+ min = (min / info->sector_count) * 1000;
+
+ /* start erase block */
+ *addr = (FPW) INTEL_CLEAR; /* clear status register */
+ *addr = (FPW) INTEL_ERASE; /* erase setup */
+ *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+ while ((*addr & (FPW) INTEL_FINISHED) !=
+ (FPW) INTEL_FINISHED) {
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
+ *addr = (FPW) INTEL_RESET; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
- while ((*atmeladdr & (u8) 0x00800080) !=
- (u8) 0x00800080) {
- if (get_timer(start) >
- CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
+ *addr = (FPW) INTEL_RESET; /* resest to read mode */
+ break;
+ }
- rcode = 1;
- break;
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case 3:
+ {
+ u8 sec = ((ulong) addr >> 16) & 0xFF;
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+ if (((status & 0x9C) != 0)
+ && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
}
- }
- *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
- } /* Atmel or Intel */
+ dspi_tx(ser_flash_cs, 0x80,
+ SER_SECT_ERASE);
+ dspi_tx(ser_flash_cs, 0x80, sec);
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ dspi_tx(ser_flash_cs, 0x00, 0);
+
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ do {
+ status =
+ serial_flash_read_status
+ (ser_flash_cs);
+
+ if (get_timer(start) >
+ CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ break;
+ }
+#endif
+ } /* switch (flashtype) */
}
}
printf(" done\n");
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
+ int count;
+
if (info->flash_id == FLASH_UNKNOWN)
return 4;
{
ulong cp, wp;
u16 data;
- int count, i, l, rc, port_width;
+ int i, l, rc, port_width;
/* get lower word aligned address */
wp = addr;
} /* case FLASH_MAN_INTEL */
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+ case FLASH_MAN_STM:
+ {
+ ulong wp;
+ u8 *data = (u8 *) src;
+ int left; /* number of bytes left to program */
+
+ wp = addr;
+
+ /* page align, each page is 256 bytes */
+ if ((wp % 0x100) != 0) {
+ left = (0x100 - (wp & 0xFF));
+ write_ser_data(info, wp, data, left);
+ cnt -= left;
+ wp += left;
+ data += left;
+ }
+
+ /* page program - 256 bytes at a time */
+ if (cnt > 255) {
+ count = 0;
+ while (cnt >= 0x100) {
+ write_ser_data(info, wp, data, 0x100);
+ cnt -= 0x100;
+ wp += 0x100;
+ data += 0x100;
+
+ if (count++ > 0x400) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ }
+
+ /* remainint bytes */
+ if (cnt && (cnt < 256)) {
+ write_ser_data(info, wp, data, cnt);
+ wp += cnt;
+ data += cnt;
+ cnt -= cnt;
+ }
+
+ printf("\b.");
+ }
+#endif
} /* switch */
return ERR_OK;
return (0);
}
+#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
+int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt)
+{
+ ulong start;
+ int status, i;
+ u8 flashdata;
+
+ /* Check if Flash is (sufficiently) erased */
+ dspi_tx(ser_flash_cs, 0x80, SER_READ);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF);
+ dspi_tx(ser_flash_cs, 0x80, dest & 0xFF);
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_tx(ser_flash_cs, 0x80, 0);
+ flashdata = dspi_rx();
+ dspi_tx(ser_flash_cs, 0x00, 0);
+ dspi_rx();
+
+ if ((flashdata & *data) != *data) {
+ printf("not erased at %08lx (%lx)\n", (ulong) dest,
+ (ulong) flashdata);
+ return (2);
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, SER_WREN);
+ dspi_rx();
+
+ status = serial_flash_read_status(ser_flash_cs);
+ if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) {
+ printf("Error Programming\n");
+ return 1;
+ }
+
+ start = get_timer(0);
+
+ dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG);
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16));
+ dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8));
+ dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF));
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+ dspi_rx();
+
+ for (i = 0; i < (cnt - 1); i++) {
+ dspi_tx(ser_flash_cs, 0x80, *data);
+ dspi_rx();
+ data++;
+ }
+
+ dspi_tx(ser_flash_cs, 0x00, *data);
+ dspi_rx();
+
+ do {
+ status = serial_flash_read_status(ser_flash_cs);
+
+ if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return 1;
+ }
+ } while (status & 0x01);
+
+ return (0);
+}
+#endif
+
/*-----------------------------------------------------------------------
* Write a word to Flash for ATMEL FLASH
* A word is 16 bits, whichever the bus width of the flash bank
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
+#ifdef CFG_DRAMSZ1
+ u32 temp;
+#endif
siu->drv = CFG_SDRAM_DRVSTRENGTH;
#endif
}
#endif
+
+#if defined(CFG_I2C_MAC_OFFSET)
+int mac_read_from_eeprom(void)
+{
+ uchar buf[28];
+ char str[18];
+ int i = 0;
+ unsigned int crc = 0;
+ unsigned char enetvar[32];
+
+ /* Read MAC addresses from EEPROM */
+ if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) {
+ printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
+ CFG_I2C_EEPROM_ADDR);
+ } else {
+ if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
+ printf("Reading MAC from EEPROM\n");
+ for (i = 0; i < 4; i++) {
+ if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
+ sprintf(str,
+ "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[i * 6], buf[i * 6 + 1],
+ buf[i * 6 + 2], buf[i * 6 + 3],
+ buf[i * 6 + 4], buf[i * 6 + 5]);
+ sprintf((char *)enetvar,
+ i ? "eth%daddr" : "ethaddr", i);
+ setenv((char *)enetvar, str);
+ }
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_I2C_MAC_OFFSET */
/* Enable flash write */
bcsr[0xa] &= ~0x04;
- /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
- if (immr->sysconf.spridr == SPR_8360_REV20 ||
- immr->sysconf.spridr == SPR_8360E_REV20 ||
- immr->sysconf.spridr == SPR_8360_REV21 ||
- immr->sysconf.spridr == SPR_8360E_REV21)
+ /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
+ if (REVID_MAJOR(immr->sysconf.spridr) == 2)
bcsr[0xe] = 0x30;
/* Enable second UART */
* if on mpc8360ea rev. 2.1,
* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
*/
- if (immr->sysconf.spridr == SPR_8360_REV21 ||
- immr->sysconf.spridr == SPR_8360E_REV21) {
+ if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
+ (REVID_MINOR(immr->sysconf.spridr) == 1)) {
int nodeoffset;
const char *prop;
int path;
#include <common.h>
#include <i2c.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
/* Clear all of the interrupt of BCSR */
bcsr[0xe] = 0xff;
+#ifdef CONFIG_FSL_SERDES
+ immap_t *immr = (immap_t *)CFG_IMMR;
+ u32 spridr = in_be32(&immr->sysconf.spridr);
+
+ /* we check only part num, and don't look for CPU revisions */
+ switch (spridr) {
+ case SPR_8377:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8378:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8379:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ default:
+ printf("serdes not configured: unknown CPU part number: "
+ "%04x\n", spridr >> 16);
+ break;
+ }
+#endif /* CONFIG_FSL_SERDES */
return 0;
}
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
- switch (spridr >> 16) {
- case SPR_8379E_REV10 >> 16:
- case SPR_8379_REV10 >> 16:
+ switch (PARTID_NO_E(spridr)) {
+ case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8378E_REV10 >> 16:
- case SPR_8378_REV10 >> 16:
+ case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8377E_REV10 >> 16:
- case SPR_8377_REV10 >> 16:
+ case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
default:
--- /dev/null
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx31_litekit.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#######################################################################
+##
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+ __REG(CSCR_L(0)) = 0xa0330d01;
+ __REG(CSCR_A(0)) = 0x00220800;
+
+ __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
+ __REG(CSCR_L(4)) = 0x444a4541;
+ __REG(CSCR_A(4)) = 0x44443302;
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: i.MX31 Litekit\n");
+ return 0;
+}
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
+ PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
+ PLL_MFN(0x23)
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
+ REG 0x43FAC288, 0
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx31_phycore.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+ __REG(CSCR_L(0)) = 0x10000d03;
+ __REG(CSCR_A(0)) = 0x00720900;
+
+ __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
+ __REG(CSCR_L(1)) = 0x444a4541;
+ __REG(CSCR_A(1)) = 0x44443302;
+
+ __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
+ __REG(CSCR_L(4)) = 0x22252521;
+ __REG(CSCR_A(4)) = 0x22220a00;
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ /* setup pins for I2C2 (for EEPROM, RTC) */
+ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
+ mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: Phytec phyCore i.MX31\n");
+ return 0;
+}
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
+ PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
+ REG 0x43FAC288, 0
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
# Korat (PPC440EPx) board
#
-TEXT_BASE = 0xFFFA0000
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
+ifeq ($(emul),1)
+PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
+endif
+
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000
+endif
+
+ifeq ($(perm),1)
+PLATFORM_CPPFLAGS += -DCONFIG_KORAT_PERMANENT
+TEXT_BASE = 0xFFFA0000
+else
+TEXT_BASE = 0xF7F60000
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
endif
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
/*
* TLB entries for SDRAM are not needed on this platform. They are
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
+ AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M,
+ CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+ tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M,
+ CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+ tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M,
+ CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+
+ tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M,
+ CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for EBC */
tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
- tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
/*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
+
+#if defined(CONFIG_KORAT_PERMANENT)
+ .globl korat_branch_absolute
+korat_branch_absolute:
+ mtlr r3
+ blr
+#endif
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org
*
- * (C) Copyright 2006-2008
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
ulong flash_get_size(ulong base, int banknum);
+#if defined(CONFIG_KORAT_PERMANENT)
+void korat_buzzer(int const on)
+{
+ if (on) {
+ out_8((u8 *) CFG_CPLD_BASE + 0x05,
+ in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80);
+ } else {
+ out_8((u8 *) CFG_CPLD_BASE + 0x05,
+ in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80);
+ }
+}
+#endif
+
int board_early_init_f(void)
{
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
+ uint32_t sdr0_pfc1, sdr0_pfc2;
+ uint32_t reg;
int eth;
+#if defined(CONFIG_KORAT_PERMANENT)
+ unsigned mscount;
+
+ extern void korat_branch_absolute(uint32_t addr);
+
+ for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) {
+ udelay(1000);
+ if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) {
+ /* This call does not return. */
+ korat_branch_absolute(
+ CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4);
+ }
+ }
+ korat_buzzer(1);
+ while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_))
+ udelay(1000);
+
+ korat_buzzer(0);
+#endif
+
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
- /* take sim card reader and CF controller out of reset */
- out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
+ /*
+ * Take sim card reader and CF controller out of reset. Also enable PHY
+ * auto-detect until board-specific PHY resets are available.
+ */
+ out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0);
/* Configure the two Ethernet PHYs. For each PHY, configure for fiber
* if the SFP module is present, and for copper if it is not present.
if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
/* SFP module not present: configure PHY for copper. */
/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
- out_8((u8 *) CFG_CPLD_BASE + 0x06,
- in_8((u8 *) CFG_CPLD_BASE + 0x06) |
+ out_8((u8 *) CFG_CPLD_BASE + 0x03,
+ in_8((u8 *) CFG_CPLD_BASE + 0x03) |
0x06 << (4 * eth));
} else {
/* SFP module present: configure PHY for fiber and
gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
- /* select Ethernet pins */
+ /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
+ udelay(1000);
+ out_8((u8 *) CFG_CPLD_BASE + 0x03,
+ in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88);
+
+ /* select Ethernet (and optionally IIC1) pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+ sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;
return 0;
}
+/*
+ * The boot flash on CS0 normally has its write-enable pin disabled, and so will
+ * not respond to CFI commands. This routine therefore fills in the flash
+ * information for the boot flash. (The flash at CS1 operates normally.)
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ uint32_t addr;
+ int i;
+
+ if (1 != banknum)
+ return 0;
+
+ info->size = CFG_FLASH0_SIZE;
+ info->sector_count = CFG_FLASH0_SIZE / 0x20000;
+ info->flash_id = 0x01000000;
+ info->portwidth = 2;
+ info->chipwidth = 2;
+ info->buffer_size = 32;
+ info->erase_blk_tout = 16384;
+ info->write_tout = 2;
+ info->buffer_write_tout = 5;
+ info->vendor = 2;
+ info->cmd_reset = 0x00F0;
+ info->interface = 2;
+ info->legacy_unlock = 0;
+ info->manufacturer_id = 1;
+ info->device_id = 0x007E;
+
+#if CFG_FLASH0_SIZE == 0x01000000
+ info->device_id2 = 0x2101;
+#elif CFG_FLASH0_SIZE == 0x04000000
+ info->device_id2 = 0x2301;
+#else
+#error Unable to set device_id2 for current CFG_FLASH0_SIZE
+#endif
+
+ info->ext_addr = 0x0040;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0055;
+ info->addr_unlock1 = 0x00000555;
+ info->addr_unlock2 = 0x000002AA;
+ info->name = "CFI conformant";
+ for (i = 0, addr = -info->size;
+ i < info->sector_count;
+ ++i, addr += 0x20000) {
+ info->start[i] = addr;
+ info->protect[i] = 0x00;
+ }
+ return 1;
+}
+
static int man_data_read(unsigned int addr)
{
/*
* If the environmental variable "serial#" is not set, try to set it
* from the manufacturer's information serial EEPROM.
*/
- char s[MAN_SERIAL_NO_LENGTH + 1];
+ char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
+
+ if (getenv("serial#"))
+ return;
+
+ if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
+ return;
+
+ s[MAN_INFO_LENGTH] = '-';
+ if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
+ MAN_MAC_ADDR_LENGTH))
+ return;
- if (0 == getenv("serial#") &&
- 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
- MAN_SERIAL_NO_LENGTH))
- setenv("serial#", s);
+ setenv("serial#", s);
}
static void set_mac_addresses(void)
* set, try to set them from the manufacturer's information serial
* EEPROM.
*/
- char s[MAN_MAC_ADDR_LENGTH + 1];
+
+#if MAN_MAC_ADDR_LENGTH % 2 != 0
+#error MAN_MAC_ADDR_LENGTH must be an even number
+#endif
+
+ char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
+ char *src;
+ char *dst;
if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
return;
- if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
- MAN_MAC_ADDR_LENGTH))
+ if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
+ MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
return;
+ for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
+ *dst++ = *src++;
+ *dst++ = *src++;
+ *dst++ = ':';
+ }
if (0 == getenv("ethaddr"))
setenv("ethaddr", s);
if (0 == getenv("eth1addr")) {
- ++s[MAN_MAC_ADDR_LENGTH - 1];
+ ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
setenv("eth1addr", s);
}
}
int misc_init_r(void)
{
- uint pbcr;
- int size_val = 0;
- u32 reg;
+ uint32_t pbcr;
+ int size_val;
+ uint32_t reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
- char *act = getenv("usbact");
-
- /* Re-do flash sizing to get full correct info */
+ uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE;
+ char const *const act = getenv("usbact");
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ /*
+ * Re-do FLASH1 sizing and adjust flash start and offset.
+ */
+ gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size;
gd->bd->bi_flashoffset = 0;
- mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
+ size_val = ffs(flash1_size) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, pbcr);
/*
*/
flash_get_size(gd->bd->bi_flashstart, 0);
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
- &flash_info[0]);
+ /*
+ * Re-do FLASH1 sizing and adjust flash offset to reserve space for
+ * environment
+ */
+ gd->bd->bi_flashoffset =
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR;
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb1cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /* Monitor protection ON by default */
+#if defined(CONFIG_KORAT_PERMANENT)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ flash_info + 1);
+#else
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ flash_info);
+#endif
/* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ flash_info);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ flash_info);
/*
* USB suff...
set_serial_number();
set_mac_addresses();
+ gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1);
+
return 0;
}
u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
printf("Board: Korat, Rev. %X", rev);
- if (s != NULL)
+ if (s)
printf(", serial# %s", s);
- printf(", Ethernet PHY 0: ");
+ printf(".\n Ethernet PHY 0: ");
if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
printf("fiber");
else
printf("copper");
printf(".\n");
- return (0);
+#if defined(CONFIG_KORAT_PERMANENT)
+ printf(" Executing permanent copy of U-Boot.\n");
+#endif
+ return 0;
}
#if defined(CFG_DRAM_TEST)
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
+ * PLB address 0x80000000-0xBFFFFFFF
+ * ==> PCI address 0x80000000-0xBFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCILA,
+ CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1LA,
+ CFG_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA,
+ CFG_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
/*
- * (C) Copyright 2000
+ * (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
-OUTPUT_ARCH(m68k)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
+ .resetvec 0xF7FBFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xF7FBF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
-
.reloc :
{
- __got_start = .;
*(.got)
- __got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
__bss_start = .;
.bss (NOLOAD) :
{
- _sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
- . = ALIGN(4);
- _ebss = .;
}
+
_end = . ;
PROVIDE (end = .);
}
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
#include <asm/mmu.h>
#include <asm/io.h>
#include <ppc440.h>
+#include <watchdog.h>
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
*/
}
-static void blank_string(int size)
-{
- int i;
-
- for (i=0; i<size; i++)
- putc('\b');
- for (i=0; i<size; i++)
- putc(' ');
- for (i=0; i<size; i++)
- putc('\b');
-}
-
static void program_ecc(u32 start_address,
u32 num_bytes,
u32 tlb_word2_i_value)
{
- u32 current_address;
- u32 end_address;
- u32 address_increment;
u32 val;
- char str[] = "ECC generation -";
- char slash[] = "\\|/-\\|/-";
- int loop = 0;
- int loopi = 0;
-
- current_address = start_address;
+ u32 current_addr = start_address;
+ int bytes_remaining;
sync();
- eieio();
wait_ddr_idle();
- if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
- /* ECC bit set method for non-cached memory */
- address_increment = 4;
- end_address = current_address + num_bytes;
-
- puts(str);
-
- while (current_address < end_address) {
- *((u32 *)current_address) = 0x00000000;
- current_address += address_increment;
-
- if ((loop++ % (2 << 20)) == 0) {
- putc('\b');
- putc(slash[loopi++ % 8]);
- }
- }
+ /*
+ * Because of 440EPx errata CHIP 11, we don't touch the last 256
+ * bytes of SDRAM.
+ */
+ bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
- blank_string(strlen(str));
- } else {
- /* ECC bit set method for cached memory */
-#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
- /*
- * Some boards (like lwmon5) need to preserve the memory
- * content upon ECC generation (for the log-buffer).
- * Therefore we don't fill the memory with a pattern or
- * just zero it, but write the same values back that are
- * already in the memory cells.
- */
- address_increment = CFG_CACHELINE_SIZE;
- end_address = current_address + num_bytes;
-
- current_address = start_address;
- while (current_address < end_address) {
- /*
- * TODO: Th following sequence doesn't work correctly.
- * Just invalidating and flushing the cache doesn't
- * seem to trigger the re-write of the memory.
- */
- ppcDcbi(current_address);
- ppcDcbf(current_address);
- current_address += CFG_CACHELINE_SIZE;
- }
-#else
- dcbz_area(start_address, num_bytes);
- dflush();
-#endif
+ /*
+ * We have to write the ECC bytes by zeroing and flushing in smaller
+ * steps, since the whole 256MByte takes too long for the external
+ * watchdog.
+ */
+ while (bytes_remaining > 0) {
+ dcbz_area(current_addr, min((64 << 20), bytes_remaining));
+ current_addr += 64 << 20;
+ bytes_remaining -= 64 << 20;
+ WATCHDOG_RESET();
}
+ dflush();
sync();
- eieio();
wait_ddr_idle();
/* Clear error status */
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
sync();
- eieio();
wait_ddr_idle();
}
#endif
--- /dev/null
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# (C) Copyright 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mpr2.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# Copyright (C) 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * board/mpr2/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+/*
+ * Set frequency multipliers and dividers in FRQCR.
+ */
+ mov.l WTCSR_A,r1
+ mov.l WTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l WTCNT_A,r1
+ mov.l WTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.w r0,@r1
+
+/*
+ * Setup CS0 (Flash).
+ */
+ mov.l CS0BCR_A, r1
+ mov.l CS0BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS0WCR_A, r1
+ mov.l CS0WCR_D, r0
+ mov.l r0, @r1
+
+/*
+ * Setup CS3 (SDRAM).
+ */
+ mov.l CS3BCR_A, r1
+ mov.l CS3BCR_D, r0
+ mov.l r0, @r1
+
+ mov.l CS3WCR_A, r1
+ mov.l CS3WCR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D1, r0
+ mov.l r0, @r1
+
+ mov.l RTCSR_A, r1
+ mov.l RTCSR_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCNT_A, r1
+ mov.l RTCNT_D, r0
+ mov.l r0, @r1
+
+ mov.l RTCOR_A, r1
+ mov.l RTCOR_D, r0
+ mov.l r0, @r1
+
+ mov.l SDCR_A, r1
+ mov.l SDCR_D2, r0
+ mov.l r0, @r1
+
+ mov.l SDMR3_A, r1
+ mov.l SDMR3_D, r0
+ add r0, r1
+ mov #0, r0
+ mov.w r0, @r1
+
+ rts
+ nop
+
+ .align 4
+
+/*
+ * Configuration for MPR2 A.3 through A.7
+ */
+
+/*
+ * PLL Settings
+ */
+FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
+WTCNT_D: .long 0x5A00 /* start counting at zero */
+WTCSR_D: .long 0xA507 /* divide by 4096 */
+
+/*
+ * Spansion S29GL256N11 @ 48 MHz
+ */
+CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
+CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+
+/*
+ * Samsung K4S511632B-UL75 @ 48 MHz
+ * Micron MT48LC32M16A2-75 @ 48 MHz
+ */
+CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D2: .long 0x00000812 /* refresh */
+RTCSR_D: .long 0xA55A0008 /* 1/4, once */
+RTCNT_D: .long 0xA55A005D /* count 93 */
+RTCOR_D: .long 0xa55a005d /* count 93 */
+SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
+
+/*
+ * Registers
+ */
+
+FRQCR_A: .long 0xA415FF80
+WTCNT_A: .long 0xA415FF84
+WTCSR_A: .long 0xA415FF86
+
+#define BSC_BASE 0xA4FD0000
+CS0BCR_A: .long BSC_BASE + 0x04
+CS3BCR_A: .long BSC_BASE + 0x0C
+CS0WCR_A: .long BSC_BASE + 0x24
+CS3WCR_A: .long BSC_BASE + 0x2C
+SDCR_A: .long BSC_BASE + 0x44
+RTCSR_A: .long BSC_BASE + 0x48
+RTCNT_A: .long BSC_BASE + 0x4C
+RTCOR_A: .long BSC_BASE + 0x50
+SDMR3_A: .long BSC_BASE + 0x5000
--- /dev/null
+/*
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * board/mpr2/mpr2.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: MPR2\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * For MPR2 A.3 through A.7
+ */
+
+ /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
+ __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
+ __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
+
+ /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
+ __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
+ __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
+ __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
+ __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+
+ /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
+ __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
+
+ /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
+ __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
+
+ /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
+ __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
+
+ /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
+ __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
+
+ /* OTH: (00) Other fuction
+ * GPO: (01) General Purpose Output
+ * GPI: (11) General Purpose Input
+ * GPI+: (10) General Purpose Input with internal pull-up
+ *-------------------------------------------------------
+ * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
+ * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
+ __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
+
+ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
+ * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
+ __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
+ * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
+ __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
+
+ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
+ * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
+ __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
+ * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
+ __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
+
+ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
+ * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
+ __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
+
+ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
+ * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
+ __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
+
+ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
+ * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
+ __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
+
+ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
+ * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
+ __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* K7 (x); K6 (x); K5 (x); K4 (x)
+ * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
+ __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
+
+ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
+ * L3 TCK; L2 (x); L1 (x); L0 (x); */
+ __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
+ * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
+ __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
+ __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
+
+ /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
+ * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
+ __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
+ __raw_writeb(0x10, PPDR); /* no current flow through pullup */
+
+ /* R7 A25; R6 A24; R5 A23; R4 A22;
+ * R3 A21; R2 A20; R1 A19; R0 A0; */
+ __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
+ * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
+ __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
+
+ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
+ * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
+ __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
+
+ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
+ * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
+ __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
+
+ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
+ * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
+ __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x8C000000.
+ U-Boot resides in the last 256 kB of the 64 MB.
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh3/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
-# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2000-2008
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(BOARD).a
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
-
-EXTRA = init_sdram_bootrom_initblock.o
+COBJS := mx31ads.o
+SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+clean:
+ rm -f $(SOBJS) $(OBJS)
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
#########################################################################
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x77777777
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =0x53F00000
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, =0x53F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =0x43F04000
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =0x00302154
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =0xB8003000
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =0x43FAC200
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+ ldr r0, =WEIM_BASE
+ ldr r1, =0x0000D843
+ str r1, [r0, #0x40]
+ ldr r1, =0x22252521
+ str r1, [r0, #0x44]
+ ldr r1, =0x22220A00
+ str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Redboot initializes very early AIPS, what for?
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF */
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_drive_strength
+
+ init_cs4
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ /* Switch on Display Interface */
+ REG IPU_CONF, IPU_CONF_DI_EN
+ /* Clock Control Module: */
+ /* Use CKIH, MCU PLL off */
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+ /* MCU PLL on */
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ /* Switch to MCU PLL */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ /* PBC CPLD on CS4 */
+ mov r1, #CS4_BASE
+ ldrh r1, [r1, #0x2]
+ /* Is 27MHz switch set? */
+ ands r1, r1, #0x16
+
+ /* 532-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871D58
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldreq r1, MPCTL_PARAM_532
+ ldrne r1, MPCTL_PARAM_532_27
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldreq r1, UPCTL_PARAM_240
+ ldrne r1, UPCTL_PARAM_240_27
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x000002C0
+ add r1, r1, #0x00000006
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
+ PDR0_MCU_PODF(0)*/
+
+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
+ PLL_MFN(0x23)*/
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
+
+MPCTL_PARAM_532:
+ .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+ .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+UPCTL_PARAM_240:
+ .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+UPCTL_PARAM_240_27:
+ .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
--- /dev/null
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+#if 0
+ /* CS0: Nor Flash */
+ /*
+ * These are values from the RedBoot sources by Freescale. However,
+ * under U-Boot with this configuration 32-bit accesses don't work,
+ * lower 16 bits of data are read twice for each 32-bit read.
+ */
+ __REG(CSCR_U(0)) = 0x23524E80;
+ __REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but
+ * disabling it doesn't help either */
+ __REG(CSCR_A(0)) = 0x00720900;
+#endif
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ /* PBC setup */
+ /* Enable UART transceivers also reset the Ethernet/external UART */
+ readw(CS4_BASE + 4);
+
+ writew(0x8023, CS4_BASE + 4);
+
+ /* RedBoot also has an empty loop with 100000 iterations here -
+ * clock doesn't run yet */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* Clear the reset, toggle the LEDs */
+ writew(0xDF, CS4_BASE + 6);
+
+ /* clock still doesn't run */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: MX31ADS\n");
+ return 0;
+}
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
#include <common.h>
-#include <asm/processor.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
#include <miiphy.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
return (ctrlc());
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+#else
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
/* PCI */
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o mii.o
+COBJS := pmdra.o
+SOBJS := board_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-#########################################################################
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
-# defines $(obj).depend target
+#########################################################################
+# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
/*
- * U-boot - start1.S Code running out of RAM after relocation
+ * Copyright (C) 2008 Prodrive B.V.
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Board-specific low level initialization code. Called at the very end
+ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
-#define ASSEMBLY
-#include <linux/config.h>
#include <config.h>
-#include <asm/blackfin.h>
-.global start1;
-.global _start1;
+.globl dv_board_init
+dv_board_init:
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
+ mov pc, lr
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
--- /dev/null
+/*
+ * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * ---------------------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ---------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_DAVINCI_EVM 901
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void timer_init(void);
+extern int eth_hw_init(void);
+extern phy_t phy;
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+ dv_reg_p mdstat, mdctl;
+
+ if (id >= DAVINCI_LPSC_GEM)
+ return; /* Don't work on DSP Power Domain */
+
+ mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+ mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+ while (REG(PSC_PTSTAT) & 0x01) {; }
+
+ if ((*mdstat & 0x1f) == 0x03)
+ return; /* Already on and enabled */
+
+ *mdctl |= 0x03;
+
+ /* Special treatment for some modules as for sprue14 p.7.4.2 */
+ if ((id == DAVINCI_LPSC_VPSSSLV) ||
+ (id == DAVINCI_LPSC_EMAC) ||
+ (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+ (id == DAVINCI_LPSC_MDIO) ||
+ (id == DAVINCI_LPSC_USB) ||
+ (id == DAVINCI_LPSC_ATA) ||
+ (id == DAVINCI_LPSC_VLYNQ) ||
+ (id == DAVINCI_LPSC_UHPI) ||
+ (id == DAVINCI_LPSC_DDR_EMIF) ||
+ (id == DAVINCI_LPSC_AEMIF) ||
+ (id == DAVINCI_LPSC_MMC_SD) ||
+ (id == DAVINCI_LPSC_MEMSTICK) ||
+ (id == DAVINCI_LPSC_McBSP) ||
+ (id == DAVINCI_LPSC_GPIO))
+ *mdctl |= 0x200;
+
+ REG(PSC_PTCMD) = 0x01;
+
+ while (REG(PSC_PTSTAT) & 0x03) {; }
+ while ((*mdstat & 0x1f) != 0x03) {; } /* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+ int i;
+
+ if (REG(PSC_PDSTAT1) & 0x1f)
+ return; /* Already on */
+
+ REG(PSC_GBLCTL) |= 0x01;
+ REG(PSC_PDCTL1) |= 0x01;
+ REG(PSC_PDCTL1) &= ~0x100;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+ REG(PSC_PTCMD) = 0x02;
+
+ for (i = 0; i < 100; i++) {
+ if (REG(PSC_EPCPR) & 0x02)
+ break;
+ }
+
+ REG(PSC_CHP_SHRTSW) = 0x01;
+ REG(PSC_PDCTL1) |= 0x100;
+ REG(PSC_EPCCR) = 0x02;
+
+ for (i = 0; i < 100; i++) {
+ if (!(REG(PSC_PTSTAT) & 0x02))
+ break;
+ }
+
+ REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* Workaround for TMS320DM6446 errata 1.3.22 */
+ REG(PSC_SILVER_BULLET) = 0;
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_EMAC);
+ lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+ lpsc_on(DAVINCI_LPSC_MDIO);
+ lpsc_on(DAVINCI_LPSC_I2C);
+ lpsc_on(DAVINCI_LPSC_UART0);
+ lpsc_on(DAVINCI_LPSC_UART2);
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+ /* Powerup the DSP */
+ dsp_on();
+
+ /* Bringup UART0 and 2 out of reset */
+ REG(UART0_PWREMU_MGMT) = 0x00006001;
+ REG(UART2_PWREMU_MGMT) = 0x00006001;
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0;
+
+ /* Enable UART0 and 2 MUX lines */
+ REG(PINMUX1) |= 1;
+ REG(PINMUX1) |= 4;
+
+ /* Enable EMAC and AEMIF pins */
+ REG(PINMUX0) = 0x80000c1f;
+
+ /* Enable I2C pin Mux */
+ REG(PINMUX1) |= (1 << 7);
+
+ /* Set the Bus Priority Register to appropriate value */
+ REG(VBPR) = 0x20;
+
+ timer_init();
+
+ return(0);
+}
+
+int misc_init_r(void)
+{
+ int clk = 0;
+
+ clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+ printf("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27)/2);
+ printf("DDR Clock : %dMHz\n", (clk / 2));
+
+ if (!eth_hw_init())
+ printf("ethernet init failed!\n");
+ else
+ printf("ETH PHY : %s\n", phy.name);
+
+ return(0);
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return(0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r2dplus.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
-# U-boot - config.mk
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
#
-
-PLATFORM_RELFLAGS += -mcpu=bf537
+TEXT_BASE = 0x0FFC0000
--- /dev/null
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_D, r0
+ mov.l r0,@r1
+
+ mov.l MMUCR_A,r1
+ mov.l MMUCR_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR1_A,r1
+ mov.l BCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR2_A,r1
+ mov.l BCR2_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR3_A,r1
+ mov.l BCR3_D,r0
+ mov.w r0,@r1
+
+ mov.l BCR4_A,r1
+ mov.l BCR4_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR1_A,r1
+ mov.l WCR1_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR2_A,r1
+ mov.l WCR2_D,r0
+ mov.l r0,@r1
+
+ mov.l WCR3_A,r1
+ mov.l WCR3_D,r0
+ mov.l r0,@r1
+
+ mov.l PCR_A,r1
+ mov.l PCR_D,r0
+ mov.w r0,@r1
+
+ mov.l LED_A,r1
+ mov #0xff,r0
+ mov.w r0,@r1
+
+ mov.l MCR_A,r1
+ mov.l MCR_D1,r0
+ mov.l r0,@r1
+
+ mov.l RTCNT_A,r1
+ mov.l RTCNT_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCOR_A,r1
+ mov.l RTCOR_D,r0
+ mov.w r0,@r1
+
+ mov.l RFCR_A,r1
+ mov.l RFCR_D,r0
+ mov.w r0,@r1
+
+ mov.l RTCSR_A,r1
+ mov.l RTCSR_D,r0
+ mov.w r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0x55,r0
+ mov.b r0,@r1
+
+ /* Wait DRAM refresh 30 times */
+ mov.l RFCR_A,r1
+ mov #30,r3
+1:
+ mov.w @r1,r0
+ extu.w r0,r2
+ cmp/hi r3,r2
+ bf 1b
+
+ mov.l MCR_A,r1
+ mov.l MCR_D2,r0
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1
+ mov #0,r0
+ mov.b r0,@r1
+
+ mov.l IRLMASK_A,r1
+ mov.l IRLMASK_D,r0
+ mov.l r0,@r1
+
+ mov.l CCR_A, r1
+ mov.l CCR_D_E, r0
+ mov.l r0, @r1
+
+ rts
+ nop
+
+ .align 2
+CCR_A: .long CCR /* Cache Control Register */
+CCR_D_D: .long 0x0808 /* Flush the cache, disable */
+CCR_D_E: .long 0x8000090B
+
+FRQCR_A: .long FRQCR /* FRQCR Address */
+FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
+BCR1_A: .long BCR1 /* BCR1 Address */
+BCR1_D: .long 0x00180008
+BCR2_A: .long BCR2 /* BCR2 Address */
+BCR2_D: .long 0xabe8
+BCR3_A: .long BCR3 /* BCR3 Address */
+BCR3_D: .long 0x0000
+BCR4_A: .long BCR4 /* BCR4 Address */
+BCR4_D: .long 0x00000010
+WCR1_A: .long WCR1 /* WCR1 Address */
+WCR1_D: .long 0x33343333
+WCR2_A: .long WCR2 /* WCR2 Address */
+WCR2_D: .long 0xcff86fbf
+WCR3_A: .long WCR3 /* WCR3 Address */
+WCR3_D: .long 0x07777707
+LED_A: .long 0x04000036 /* LED Address */
+RTCNT_A: .long RTCNT /* RTCNT Address */
+RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCOR_A: .long RTCOR /* RTCOR Address */
+RTCOR_D: .long 0xA534 /* RTCOR Write Code */
+RTCSR_A: .long RTCSR /* RTCSR Address */
+RTCSR_D: .long 0xA510 /* RTCSR Write Code */
+SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
+SDMR3_D: .long 0x55
+MCR_A: .long MCR /* MCR Address */
+MCR_D1: .long 0x081901F4 /* MRSET:'0' */
+MCR_D2: .long 0x481901F4 /* MRSET:'1' */
+RFCR_A: .long RFCR /* RFCR Address */
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+PCR_A: .long PCR /* PCR Address */
+PCR_D: .long 0x0000
+MMUCR_A: .long MMUCR /* MMUCCR Address */
+MMUCR_D: .long 0x00000000 /* MMUCCR Data */
+IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
+IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
--- /dev/null
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Solutions R2D Plus\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7751_init( &hose );
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x0C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
+++ /dev/null
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-
-
-int checkboard (void) {
- puts ("Board: R5200 Ethernet Module\n");
- return 0;
-};
-
-long int initdram (int board_type) {
- int i;
-
- /*
- * Set CS2 pin to be SD_CS0
- */
- mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
- | MCF_GPIO_PAR_CS_PAR_CS2);
-
- mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
- | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
- /*
- * Initialize DRAM Control Register: DCR
- */
- mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
- | MCF_SDRAMC_DCR_RC(0x30));
-
- /*
- * Initialize DACR0
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
- | MCF_SDRAMC_DACRn_CASL(0)
- | MCF_SDRAMC_DACRn_CBM(3)
- | MCF_SDRAMC_DACRn_PS(2));
-
- /*
- * Initialize DMR0
- */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_8M
- | MCF_SDRAMC_DMRn_V);
-
- /*
- * Set IP bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_IP);
-
- /*
- * Wait at least 20ns to allow banks to precharge
- */
- for (i = 0; i < 5; i++)
- asm(" nop");
-
- /*
- * Write to this block to initiate precharge
- */
- *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
-
- /*
- * Set RE bit in DACR
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_RE);
-
-
- /*
- * Wait for at least 8 auto refresh cycles to occur
- */
- for (i = 0; i < 2000; i++)
- asm(" nop");
-
- /*
- * Finish the configuration by issuing the MRS.
- */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_MRS);
-
-
- /*
- * Write to the SDRAM Mode Register
- */
- *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
- }
-
- return CFG_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
--- /dev/null
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r7780mp/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := r7780mp.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
-# U-boot - config.mk
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# board/r77870mp/config.mk
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
#
-PLATFORM_RELFLAGS += -mcpu=bf533
+TEXT_BASE = 0x0FFC0000
--- /dev/null
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * u-boot/board/r7780mp/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 /* Address of Cache Control Register */
+ mov.l CCR_D, r0 /* Instruction Cache Invalidate */
+ mov.l r0, @r1
+
+ mov.l FRQCR_A, r1 /* Frequency control register */
+ mov.l FRQCR_D, r0
+ mov.l r0, @r1
+
+ /* pin_multi_setting */
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR1,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR1_A,r1
+ mov.l BBG_PMSR1_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR2,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR2_A,r1
+ mov.l BBG_PMSR2_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR3,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR3_A,r1
+ mov.l BBG_PMSR3_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSR4,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSR4_A,r1
+ mov.l BBG_PMSR4_D,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMMR_A,r1
+ mov.l BBG_PMMR_D_PMSRG,r0
+ mov.l r0,@r1
+
+ mov.l BBG_PMSRG_A,r1
+ mov.l BBG_PMSRG_D,r0
+ mov.l r0,@r1
+
+ /* cpg_setting */
+ mov.l FRQCR_A,r1
+ mov.l FRQCR_D,r0
+ mov.l r0,@r1
+
+ mov.l DLLCSR_A,r1
+ mov.l DLLCSR_D,r0
+ mov.l r0,@r1
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat0:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat0
+ nop
+
+ /* bsc_setting */
+ mov.l MMSELR_A,r1
+ mov.l MMSELR_D,r0
+ mov.l r0,@r1
+
+ mov.l BCR_A,r1
+ mov.l BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0BCR_A,r1
+ mov.l CS0BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1BCR_A,r1
+ mov.l CS1BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2BCR_A,r1
+ mov.l CS2BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4BCR_A,r1
+ mov.l CS4BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5BCR_A,r1
+ mov.l CS5BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6BCR_A,r1
+ mov.l CS6BCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS0WCR_A,r1
+ mov.l CS0WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS1WCR_A,r1
+ mov.l CS1WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS2WCR_A,r1
+ mov.l CS2WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS4WCR_A,r1
+ mov.l CS4WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5WCR_A,r1
+ mov.l CS5WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6WCR_A,r1
+ mov.l CS6WCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS5PCR_A,r1
+ mov.l CS5PCR_D,r0
+ mov.l r0,@r1
+
+ mov.l CS6PCR_A,r1
+ mov.l CS6PCR_D,r0
+ mov.l r0,@r1
+
+ /* ddr_setting */
+ /* wait 200us */
+ mov.l REPEAT0_R3,r3
+ mov #0,r2
+repeat1:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat1
+ nop
+
+ mov.l MIM_U_A,r0
+ mov.l MIM_U_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l STR_L_A,r0
+ mov.l STR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SDR_L_A,r0
+ mov.l SDR_L_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D0,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l EMRS_A,r0
+ mov.l EMRS_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS1_A,r0
+ mov.l MRS1_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D2,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D3,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D4,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS2_A,r0
+ mov.l MRS2_D,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A,r0
+ mov.l SCR_L_D5,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ /* wait 200us */
+ mov.l REPEAT0_R1,r3
+ mov #0,r2
+repeat2:
+ add #1,r2
+ cmp/hs r3,r2
+ bf repeat2
+
+ synco
+
+ mov.l MIM_L_A,r0
+ mov.l MIM_L_D1,r1
+ synco
+ mov.l r1,@r0
+ synco
+
+ rts
+ nop
+ .align 4
+
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+
+BBG_PMMR_A: .long 0xFF800010
+BBG_PMSR1_A: .long 0xFF800014
+BBG_PMSR2_A: .long 0xFF800018
+BBG_PMSR3_A: .long 0xFF80001C
+BBG_PMSR4_A: .long 0xFF800020
+BBG_PMSRG_A: .long 0xFF800024
+
+BBG_PMMR_D_PMSR1: .long 0xffffbffd
+BBG_PMSR1_D: .long 0x00004002
+BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
+BBG_PMSR2_D: .long 0x03de5800
+BBG_PMMR_D_PMSR3: .long 0xfffffff8
+BBG_PMSR3_D: .long 0x00000007
+BBG_PMMR_D_PMSR4: .long 0xdffdfff9
+BBG_PMSR4_D: .long 0x20020006
+BBG_PMMR_D_PMSRG: .long 0xffffffff
+BBG_PMSRG_D: .long 0x00000000
+
+FRQCR_A: .long FRQCR
+DLLCSR_A: .long 0xffc40010
+FRQCR_D: .long 0x40233035
+DLLCSR_D: .long 0x00000000
+
+/* for DDR-SDRAM */
+MIM_U_A: .long MIM_1
+MIM_L_A: .long MIM_2
+SCR_U_A: .long SCR_1
+SCR_L_A: .long SCR_2
+STR_U_A: .long STR_1
+STR_L_A: .long STR_2
+SDR_U_A: .long SDR_1
+SDR_L_A: .long SDR_2
+
+EMRS_A: .long 0xFEC02000
+MRS1_A: .long 0xFEC00B08
+MRS2_A: .long 0xFEC00308
+
+MIM_U_D: .long 0x00004000
+MIM_L_D0: .long 0x03e80009
+MIM_L_D1: .long 0x03e80209
+SCR_L_D0: .long 0x3
+SCR_L_D1: .long 0x2
+SCR_L_D2: .long 0x2
+SCR_L_D3: .long 0x4
+SCR_L_D4: .long 0x4
+SCR_L_D5: .long 0x0
+STR_L_D: .long 0x000f0000
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x0
+MRS1_D: .long 0x0
+MRS2_D: .long 0x0
+
+/* Cache Controller */
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+RWTCNT_A: .long WTCNT
+
+CCR_D: .long 0x0000090b
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+
+/* local Bus State Controller */
+MMSELR_A: .long MMSELR
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS1BCR_A: .long CS1BCR
+CS2BCR_A: .long CS2BCR
+CS4BCR_A: .long CS4BCR
+CS5BCR_A: .long CS5BCR
+CS6BCR_A: .long CS6BCR
+CS0WCR_A: .long CS0WCR
+CS1WCR_A: .long CS1WCR
+CS2WCR_A: .long CS2WCR
+CS4WCR_A: .long CS4WCR
+CS5WCR_A: .long CS5WCR
+CS6WCR_A: .long CS6WCR
+CS5PCR_A: .long CS5PCR
+CS6PCR_A: .long CS6PCR
+
+MMSELR_D: .long 0xA5A50003
+BCR_D: .long 0x00000000
+CS0BCR_D: .long 0x77777770
+CS1BCR_D: .long 0x77777670
+CS2BCR_D: .long 0x77777770
+CS4BCR_D: .long 0x77777770
+CS5BCR_D: .long 0x77777670
+CS6BCR_D: .long 0x77777770
+CS0WCR_D: .long 0x00020006
+CS1WCR_D: .long 0x00232304
+CS2WCR_D: .long 0x7777770F
+CS4WCR_D: .long 0x7777770F
+CS5WCR_D: .long 0x00101006
+CS6WCR_D: .long 0x77777703
+CS5PCR_D: .long 0x77000000
+CS6PCR_D: .long 0x77000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT0_R1: .long 0x0000200
--- /dev/null
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include "r7780mp.h"
+
+int checkboard(void)
+{
+#if defined(CONFIG_R7780MP)
+ puts("BOARD: Renesas Solutions R7780MP\n");
+#else
+ puts("BOARD: Renesas Solutions R7780RP\n");
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* SCIF Enable */
+ *(vu_short*)PHCR = 0x0000;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+
+}
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset){
+ (*(vu_short *)FPGA_CFCTL) = 0x432;
+#if defined(CONFIG_R7780MP)
+ (*(vu_short *)FPGA_CFPOW) |= 0x01;
+#else
+ (*(vu_short *)FPGA_CFPOW) |= 0x02;
+#endif
+ (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+ }
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7780_init( &hose );
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/board/r7780mp/r7780mp.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_R7780MP_R7780MP_H_
+#define _BOARD_R7780MP_R7780MP_H_
+
+/* R7780MP's FPGA register map */
+#define FPGA_BASE 0xa4000000
+#define FPGA_IRLMSK (FPGA_BASE + 0x00)
+#define FPGA_IRLMON (FPGA_BASE + 0x02)
+#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
+#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
+#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
+#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
+#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
+#define FPGA_PCIBD (FPGA_BASE + 0x0E)
+#define FPGA_PCICD (FPGA_BASE + 0x10)
+#define FPGA_EXTGIO (FPGA_BASE + 0x16)
+#define FPGA_IVDRMON (FPGA_BASE + 0x18)
+#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
+#define FPGA_OBLED (FPGA_BASE + 0x1C)
+#define FPGA_OBSW (FPGA_BASE + 0x1E)
+#define FPGA_TPCTL (FPGA_BASE + 0x100)
+#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
+#define FPGA_TPCLR (FPGA_BASE + 0x104)
+#define FPGA_TPXPOS (FPGA_BASE + 0x106)
+#define FPGA_TPYPOS (FPGA_BASE + 0x108)
+#define FPGA_DBSW (FPGA_BASE + 0x200)
+#define FPGA_VERSION (FPGA_BASE + 0x700)
+#define FPGA_CFCTL (FPGA_BASE + 0x300)
+#define FPGA_CFPOW (FPGA_BASE + 0x302)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
+#define FPGA_PMR (FPGA_BASE + 0x900)
+
+#endif /* _BOARD_R7780RP_R7780RP_H_ */
--- /dev/null
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x08000000 + (128*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
return 1;
}
-#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
+#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x) || defined(CONFIG_MII_INIT)
mii_init ();
#endif
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = interrupts.o cpu.o
+COBJS = cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
#include <common.h>
#include <command.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
unsigned long value;
__asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
return value;
}
-# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
-
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
+LIB = $(obj)lib$(SOC).a
-EXTRA = init_sdram_bootrom_initblock.o
+COBJS = interrupts.o serial.o generic.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
-#########################################################################
+#######################################################################
+##
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
-
-#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+ u32 mfi = (reg >> 10) & 0xf;
+ u32 mfn = reg & 0x3f;
+ u32 mfd = (reg >> 16) & 0x3f;
+ u32 pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+ mfd += 1;
+ pd += 1;
+
+ return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
+ (mfd * pd)) << 10;
+}
+
+u32 mx31_get_mpl_dpdgck_clk(void)
+{
+ u32 infreq;
+
+ if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+ infreq = CONFIG_MX31_CLK32 * 1024;
+ else
+ infreq = CONFIG_MX31_HCLK_FREQ;
+
+ return mx31_decode_pll(__REG(CCM_MPCTL), infreq); }
+
+u32 mx31_get_mcu_main_clk(void)
+{
+ /* For now we assume mpl_dpdgck_clk == mcu_main_clk
+ * which should be correct for most boards
+ */
+ return mx31_get_mpl_dpdgck_clk();
+}
+
+u32 mx31_get_ipg_clk(void)
+{
+ u32 freq = mx31_get_mcu_main_clk();
+ u32 pdr0 = __REG(CCM_PDR0);
+
+ freq /= ((pdr0 >> 3) & 0x7) + 1;
+ freq /= ((pdr0 >> 6) & 0x3) + 1;
+
+ return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+ u32 cpufreq = mx31_get_mcu_main_clk();
+ printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
+ printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+ unsigned long reg, shift, tmp;
+
+ reg = IOMUXC_BASE + (mode & 0xfc);
+ shift = (~mode & 0x3) * 8;
+
+ tmp = __REG(reg);
+ tmp &= ~(0xff << shift);
+ tmp |= ((mode >> 8) & 0xff) << shift;
+ __REG(reg) = tmp;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX31 at %d MHz\n",
+ mx31_get_mcu_main_clk() / 1000000);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR __REG(TIMER_BASE) /* Control register */
+#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
+#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
+#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ GPTCR = GPTCR_SWR;
+ for (i = 0; i < 100; i++) GPTCR = 0; /* We have no udelay by now */
+ GPTPR = 0; /* 32Khz */
+ /* Freerun Mode, PERCLK1 input */
+ GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ GPTCR = 0;
+ /* Freerun Mode, PERCLK1 input*/
+ GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = GPTCNT;
+ return val;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000; /* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_cpu(ulong addr)
+{
+ __REG16(WDOG_BASE) = 4;
+}
--- /dev/null
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#if defined CONFIG_MX31_UART
+
+#include <asm/arch/mx31.h>
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+#ifdef CFG_MX31_UART1
+#define UART_PHYS 0x43f90000
+#elif defined(CFG_MX31_UART2)
+#define UART_PHYS 0x43f94000
+#elif defined(CFG_MX31_UART3)
+#define UART_PHYS 0x5000c000
+#elif defined(CFG_MX31_UART4)
+#define UART_PHYS 0x43fb0000
+#elif defined(CFG_MX31_UART5)
+#define UART_PHYS 0x43fb4000
+#else
+#error "define CFG_MX31_UARTx to use the mx31 UART driver"
+#endif
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ u32 clk = mx31_get_ipg_clk();
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UBIR) = 0xf;
+ __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
+
+}
+
+int serial_getc(void)
+{
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ return __REG(UART_PHYS + URXD);
+}
+
+void serial_putc(const char c)
+{
+ __REG(UART_PHYS + UTXD) = c;
+
+ /* wait for transmitter to be ready */
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer */
+int serial_tstc(void)
+{
+ /* If receive fifo is empty, return false */
+ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ return 0;
+ return 1;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init(void)
+{
+ __REG(UART_PHYS + UCR1) = 0x0;
+ __REG(UART_PHYS + UCR2) = 0x0;
+
+ while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
+
+ __REG(UART_PHYS + UCR3) = 0x0704;
+ __REG(UART_PHYS + UCR4) = 0x8000;
+ __REG(UART_PHYS + UESC) = 0x002b;
+ __REG(UART_PHYS + UTIM) = 0x0;
+
+ __REG(UART_PHYS + UTS) = 0x0;
+
+ serial_setbrg();
+
+ __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | \
+ UCR2_TXEN | UCR2_SRST;
+
+ __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
+
+ return 0;
+}
+
+
+#endif /* CONFIG_MX31 */
-# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
-
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
+LIB = $(obj)lib$(SOC).a
-EXTRA = init_sdram_bootrom_initblock.o
+COBJS = interrupts.o
+SOBJS = start.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#include <common.h>
#include <asm/arch/bits.h>
-
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-# include <asm/arch/omap2420.h>
-#endif
+#include <asm/arch/omap2420.h>
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp.c */
-#else
+#define READ_TIMER (*((volatile ulong*)(CFG_TIMERBASE+TCRR)))
static ulong timestamp;
static ulong lastinc;
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
{
int32_t val;
/* Start the counter ticking up */
- *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
- val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
+ /* reload value on overflow*/
+ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
+ /* mask to enable timer*/
+ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;
*((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
reset_timer_masked(); /* init the timestamp and lastinc value */
/*
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo, tmp;
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
+ /* if "big" number, spread normalization to seconds */
+ if (usec >= 1000) {
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ /* finish normalize. */
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
-
- tmp = get_timer (0); /* get current timestamp */
- if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
+ /* get current timestamp */
+ tmp = get_timer(0);
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
else
- tmo += tmp; /* else, set advancing stamp wake up time */
- while (get_timer_masked () < tmo)/* loop till event */
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
- lastinc = READ_TIMER; /* capture current incrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ /* capture current incrementer value time */
+ lastinc = READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
- ulong now = READ_TIMER; /* current tick value */
+ ulong now = READ_TIMER; /* current tick value */
- if (now >= lastinc) /* normal mode (non roll) */
- timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
- else /* we have rollover of incrementer */
+ /* normal mode (non roll) */
+ if (now >= lastinc)
+ /* move stamp forward with absolute diff ticks */
+ timestamp += (now - lastinc);
+ else
+ /* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
lastinc = now;
return timestamp;
}
/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000;/* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_timer_masked() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_timer_masked();
diff = endtime - now;
} while (diff >= 0);
}
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
return tbclk;
}
-#endif /* !Integrator/CP */
--- /dev/null
+/*
+ * armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
+ *
+ * Copyright (c) 2001 Marius Gr??ger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Z??pke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap2420.h>
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl /* get addr for global reset reg */
+ mov r3, #0x2 /* full reset pll+mpu */
+ str r3, [r1] /* force reset */
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PM_RSTCTRL_WKUP
#include <config.h>
#include <version.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
.globl _start
_start: b reset
#ifdef CONFIG_ONENAND_IPL
arm1136_cache_flush:
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp/platform.S */
-#else
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl /* get addr for global reset reg */
- mov r3, #0x2 /* full reset pll+mpu */
- str r3, [r1] /* force reset */
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PM_RSTCTRL_WKUP
-
-#endif
#endif /* CONFIG_ONENAND_IPL */
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
+ * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
* Partially based on TI sources, original copyrights follow:
*/
/* Program the PLL Multiplier */
ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
+ mov r2, $CFG_DAVINCI_PLL2_PLLM
str r2, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2
- mov r3, $0x01
+ mov r3, $CFG_DAVINCI_PLL2_DIV2
str r3, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
+ mov r4, $CFG_DAVINCI_PLL2_DIV1
str r4, [r6]
/* PLL2 DIV2 MMR */
bne checkDDRStatClkStop
/*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
+ * Program DDR2 MMRs *
*------------------------------------------------------*/
/* Program PHY Control Register */
/* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
+ ldr r7, SDTIM0_VAL
str r7, [r6]
/* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
+ ldr r7, SDTIM1_VAL
str r7, [r6]
/* Program the SDRAM Bank Config Control Register */
/* Program the PLL Multiplier */
ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
+ mov r3, $CFG_DAVINCI_PLL1_PLLM
str r3, [r6]
/* Wait for PLL to Reset Properly */
nop
/*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
+ * AEMIF configuration for NAND/NOR Flash *
*------------------------------------------------------*/
ldr r0, _PINMUX0
ldr r1, _DEV_SETTING
orr r2, r2, r1
str r2, [r0]
+ ldr r0, ACFG2
+ ldr r1, ACFG2_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
ldr r0, ACFG3
ldr r1, ACFG3_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
+ ldr r0, NANDFCR
+ ldr r1, NANDFCR_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
/*--------------------------------------*
* VTP manual Calibration *
*--------------------------------------*/
.word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING:
- .word 0x00000c1f
+ .word CFG_DAVINCI_PINMUX_0
WAITCFG:
.word 0x01e00004
WAITCFG_VAL:
- .word 0
+ .word CFG_DAVINCI_WAITCFG
+ACFG2:
+ .word 0x01e00010
+ACFG2_VAL:
+ .word CFG_DAVINCI_ACFG2
ACFG3:
.word 0x01e00014
ACFG3_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG3
ACFG4:
.word 0x01e00018
ACFG4_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG4
ACFG5:
.word 0x01e0001c
ACFG5_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG5
+NANDFCR:
+ .word 0x01e00060
+NANDFCR_VAL:
+#ifdef CFG_DAVINCI_NANDCE
+ .word (1 << (CFG_DAVINCI_NANDCE - 2))
+#else
+ .word 0x00000000
+#endif
MDCTL_DDR2:
.word 0x01c41a34
PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+/* DDR2 MMR & CONFIGURATION VALUES */
DDRCTL:
.word 0x200000e4
DDRCTL_VAL:
- .word 0x50006405
+ .word CFG_DAVINCI_DDRCTL
SDREF:
.word 0x2000000c
SDREF_VAL:
- .word 0x000005c3
+ .word CFG_DAVINCI_SDREF
SDCFG:
.word 0x20000008
SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
+ .word CFG_DAVINCI_SDCFG
SDTIM0:
.word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
+SDTIM0_VAL:
+ .word CFG_DAVINCI_SDTIM0
SDTIM1:
.word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
+SDTIM1_VAL:
+ .word CFG_DAVINCI_SDTIM1
VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */
DDRVTPR:
MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL:
- .word 0x00444400
+ .word CFG_DAVINCI_MMARG_BRF0
DDR2_START_ADDR:
.word 0x80000000
dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC;
- emif_addr->NANDFCR |= (1 << 8);
+ emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
- region = 1;
+ region = (CFG_DAVINCI_NANDCE - 1);
while (n--) {
tmp = nand_davinci_readecc(mtd, region);
*ecc_code++ = tmp;
static void nand_flash_init(void)
{
- u_int32_t acfg1 = 0x3ffffffc;
- u_int32_t acfg2 = 0x3ffffffc;
- u_int32_t acfg3 = 0x3ffffffc;
- u_int32_t acfg4 = 0x3ffffffc;
- emifregs emif_regs;
-
- /*------------------------------------------------------------------*
- * NAND FLASH CHIP TIMEOUT @ 459 MHz *
- * *
- * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
- * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
- * *
- *------------------------------------------------------------------*/
- acfg1 = 0
- | (0 << 31 ) /* selectStrobe */
- | (0 << 30 ) /* extWait */
- | (1 << 26 ) /* writeSetup 10 ns */
- | (3 << 20 ) /* writeStrobe 40 ns */
- | (1 << 17 ) /* writeHold 10 ns */
- | (1 << 13 ) /* readSetup 10 ns */
- | (5 << 7 ) /* readStrobe 60 ns */
- | (1 << 4 ) /* readHold 10 ns */
- | (3 << 2 ) /* turnAround ?? ns */
- | (0 << 0 ) /* asyncSize 8-bit bus */
- ;
-
- emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- emif_regs->AWCCR |= 0x10000000;
- emif_regs->AB1CR = acfg1; /* 0x08244128 */;
- emif_regs->AB2CR = acfg2;
- emif_regs->AB3CR = acfg3;
- emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
+ /* All EMIF initialization is done in lowlevel_init.S
+ * and config values are in the board config files
+ */
}
int board_nand_init(struct nand_chip *nand)
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt_clksped;
- u_int32_t gpint_en;
- u_int32_t gpdir_dat;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
- u_int32_t tlgc;
- u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x) ((x) >> 4)
+#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06;
+ timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
- timer->tcr = 0x80 << 16;
timestamp = 0;
+ timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
- lastinc = DIV(READ_TIMER);
+ timer->tcr = 0x0;
+ timer->tim34 = 0;
+ lastinc = 0;
timestamp = 0;
+ timer->tcr = 2 << 22;
}
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
{
- ulong now = DIV(READ_TIMER);
+ ulong now = timer->tim34;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer_masked(void)
+ulong get_timer(ulong base)
+{
+ return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); }
+
+void set_timer(ulong t)
{
- return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+ timestamp = t;
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
- tmo /= 1000;
+ tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return(tbclk);
+ return CFG_HZ;
}
+++ /dev/null
-/*
- * U-boot - bf533_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf533_SERIAL_H
-#define _Bf533_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
+++ /dev/null
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
+++ /dev/null
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache,
- * clear it so we don't confuse the next application
- */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
+++ /dev/null
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
+++ /dev/null
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /* Anamoly 05000209 */
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
-
- /* Save in extraction pattern for later deposit. */
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:
- IFLUSH [P0++];
-ieall:
- NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
+++ /dev/null
-/*
- * U-boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags; /* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On BF533 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On BF533 it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 1;
-}
-
-int interrupt_init(void)
-{
- return (0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned long delay, start, stop;
- unsigned long cclk;
- cclk = (CONFIG_CCLK_HZ);
-
- while (usec > 1) {
- /*
- * how many clock ticks to delay?
- * - request(in useconds) * clock_ticks(Hz) / useconds/second
- */
- if (usec < 1000) {
- delay = (usec * (cclk / 244)) >> 12;
- usec = 0;
- } else {
- delay = (1000 * (cclk / 244)) >> 12;
- usec -= 1000;
- }
-
- asm volatile (" %0 = CYCLES;":"=r" (start));
- do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
- } while (stop - start < delay);
- }
-
- return;
-}
-
-void timer_init(void)
-{
- *pTCNTL = 0x1;
- *pTSCALE = 0x0;
- *pTCOUNT = MAX_TIM_LOAD;
- *pTPERIOD = MAX_TIM_LOAD;
- *pTCNTL = 0x7;
- asm("CSYNC;");
-
- timestamp = 0;
- last_time = 0;
-}
-
-/* Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
- ulong milisec;
-
- /* Number of clocks elapsed */
- ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
-
- /**
- * Find if the TCOUNT is reset
- * timestamp gives the number of times
- * TCOUNT got reset
- */
- if (clocks < last_time)
- timestamp++;
- last_time = clocks;
-
- /* Get the number of milliseconds */
- milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
- /**
- * Find the number of millisonds
- * that got elapsed before this TCOUNT cycle
- */
- milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
- return (milisec - base);
-}
+++ /dev/null
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SIC_IMASK) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
+++ /dev/null
-/*
- * U-boot - serial.c Serial driver for BF533
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include "bf533_serial.h"
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /* Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register*/
- *pUART_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART_LSR; /* Clear status bit */
- uart_rbr_val = *pUART_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART_THR = ch; /* putc() */
-
- return;
-}
+++ /dev/null
-/*
- * U-boot - start.S Startup file of u-boot for BF533/BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /* As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /* Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- call init_sdram;
-
- /* relocate into to RAM */
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.H = hi(SYSMMR_BASE);
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- /* Destination DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN);
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- /* Set Destination Base Address */
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
-
- /* Write 1 to clear DMA interrupt */
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end: nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
+++ /dev/null
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault,
- * return without doing anything. Then,
- * if we get the same fault again, handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n",
- addr, last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data) {
- addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
- } else {
- addr = *(unsigned int *)pICPLB_FAULT_ADDR;
- }
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
- fp->rete, fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n",
- fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
+++ /dev/null
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
+++ /dev/null
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
+++ /dev/null
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- if ((*pCHIPID >> 28) < 2)
- return;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- if ((*pCHIPID >> 28) < 2)
- return;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache,
- * clear it so we don't confuse the next application
- */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
-
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
+++ /dev/null
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
+++ /dev/null
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /* Anamoly 05000209 */
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
-
- /* Save in extraction pattern for later deposit. */
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-
-#ifdef CONFIG_BF537
- /* Enable PHY CLK buffer output */
- p0.h = hi(VR_CTL);
- p0.l = lo(VR_CTL);
- r0.l = w[p0];
- bitset(r0, 14);
- w[p0] = r0.l;
- ssync;
-#endif
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-
-#ifdef CONFIG_BF537
- /* Enable PHY CLK buffer output */
- p0.h = hi(VR_CTL);
- p0.l = lo(VR_CTL);
- r0.l = w[p0];
- bitset(r0, 14);
- w[p0] = r0.l;
- ssync;
-#endif
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
+++ /dev/null
-/*
- * U-boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags; /* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On BF533 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On BF533 it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 1;
-}
-
-int interrupt_init(void)
-{
- return (0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned long delay, start, stop;
- unsigned long cclk;
- cclk = (CONFIG_CCLK_HZ);
-
- while (usec > 1) {
- /*
- * how many clock ticks to delay?
- * - request(in useconds) * clock_ticks(Hz) / useconds/second
- */
- if (usec < 1000) {
- delay = (usec * (cclk / 244)) >> 12;
- usec = 0;
- } else {
- delay = (1000 * (cclk / 244)) >> 12;
- usec -= 1000;
- }
-
- asm volatile (" %0 = CYCLES;":"=r" (start));
- do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
- } while (stop - start < delay);
- }
-
- return;
-}
-
-void timer_init(void)
-{
- *pTCNTL = 0x1;
- *pTSCALE = 0x0;
- *pTCOUNT = MAX_TIM_LOAD;
- *pTPERIOD = MAX_TIM_LOAD;
- *pTCNTL = 0x7;
- asm("CSYNC;");
-
- timestamp = 0;
- last_time = 0;
-}
-
-/* Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
- ulong milisec;
-
- /* Number of clocks elapsed */
- ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
-
- /**
- * Find if the TCOUNT is reset
- * timestamp gives the number of times
- * TCOUNT got reset
- */
- if (clocks < last_time)
- timestamp++;
- last_time = clocks;
-
- /* Get the number of milliseconds */
- milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
- /**
- * Find the number of millisonds
- * that got elapsed before this TCOUNT cycle
- */
- milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
- return (milisec - base);
-}
-
-void reset_timer (void)
-{
- timestamp = 0;
-}
+++ /dev/null
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SIC_IMASK) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
+++ /dev/null
-/*
- * U-boot - serial.c Serial driver for BF537
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include "serial.h"
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART0_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART0_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART0_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /* Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register*/
- *pUART0_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART0_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART0_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART0_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART0_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART0_LSR; /* Clear status bit */
- uart_rbr_val = *pUART0_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART0_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART0_THR = ch; /* putc() */
-
- return;
-}
+++ /dev/null
-/*
- * U-boot - bf537_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf537_SERIAL_H
-#define _Bf537_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART0_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
+++ /dev/null
-/*
- * U-boot - start.S Startup file of u-boot for BF537
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-.global _icache_enable;
-.global _dcache_enable;
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
-.global _memory_post_test;
-.global _post_flag;
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /* As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /* Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
-#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
-
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- * we need to read MAC address from FLASH
- */
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
-#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- call init_sdram;
-#endif
-
-
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
- /* DMA POST code to Hi of L1 SRAM */
-postcopy:
- /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.H = hi(SYSMMR_BASE);
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = _text_l1;
- R0.L = _text_l1;
- R1.H = _etext_l1;
- R1.L = _etext_l1;
- R2 = R1 - R0; /* Count */
- R0.H = _etext;
- R0.L = _etext;
- R1.H = (CFG_MONITOR_BASE >> 16);
- R1.L = (CFG_MONITOR_BASE & 0xFFFF);
- R0 = R0 - R1;
- R1.H = (CFG_FLASH_BASE >> 16);
- R1.L = (CFG_FLASH_BASE & 0xFFFF);
- R0 = R0 + R1; /* Source Address */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- /* Destination DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN);
-
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-POST_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump POST_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* DMA POST data to Hi of L1 SRAM */
- R0.H = _rodata_l1;
- R0.L = _rodata_l1;
- R1.H = _erodata_l1;
- R1.L = _erodata_l1;
- R2 = R1 - R0; /* Count */
- R0.H = _erodata;
- R0.L = _erodata;
- R1.H = (CFG_MONITOR_BASE >> 16);
- R1.L = (CFG_MONITOR_BASE & 0xFFFF);
- R0 = R0 - R1;
- R1.H = (CFG_FLASH_BASE >> 16);
- R1.L = (CFG_FLASH_BASE & 0xFFFF);
- R0 = R0 + R1; /* Source Address */
- R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
- R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-POST_DATA_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump POST_DATA_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- p0.l = _memory_post_test;
- p0.h = _memory_post_test;
- r0 = 0x0;
- call (p0);
- r7 = r0; /* save return value */
-
- call init_sdram;
-#endif
-
- /* relocate into to RAM */
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
-#ifdef CONFIG_BF537
-/* Initialise General-Purpose I/O Modules on BF537
- * Rev 0.0 Anomaly 05000212 - PORTx_FER,
- * PORT_MUX Registers Do Not accept "writes" correctly
- */
- p0.h = hi(PORTF_FER);
- p0.l = lo(PORTF_FER);
- R0.L = W[P0]; /* Read */
- nop;
- nop;
- nop;
- ssync;
- R0 = 0x000F(Z);
- W[P0] = R0.L; /* Write */
- nop;
- nop;
- nop;
- ssync;
- W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
- nop;
- nop;
- nop;
- ssync;
-
- p0.h = hi(PORTH_FER);
- p0.l = lo(PORTH_FER);
- R0.L = W[P0]; /* Read */
- nop;
- nop;
- nop;
- ssync;
- R0 = 0xFFFF(Z);
- W[P0] = R0.L; /* Write */
- nop;
- nop;
- nop;
- ssync;
- W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
- nop;
- nop;
- nop;
- ssync;
-
-#endif
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
- p0.l = _post_flag;
- p0.h = _post_flag;
- r0 = r7;
- [p0] = r0;
-#endif
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end:
- nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
+++ /dev/null
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault,
- * return without doing anything. Then,
- * if we get the same fault again, handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n",
- addr, last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data) {
- addr = *pDCPLB_FAULT_ADDR;
- } else {
- addr = *pICPLB_FAULT_ADDR;
- }
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
-trap_c_return:
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
- fp->rete, fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n",
- fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
+++ /dev/null
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
+++ /dev/null
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
+++ /dev/null
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
-
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache, clear it so we don't confuse the next application */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
+++ /dev/null
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
+++ /dev/null
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
-
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-
- p0.h = hi(SICA_IWR0);
- p0.l = lo(SICA_IWR0);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
+++ /dev/null
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
+++ /dev/null
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SICA_IMASK0) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
+++ /dev/null
-/*
- * U-boot - serial.c Serial driver for BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include "serial.h"
-#include <asm/io.h>
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /*
- * Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register
- */
- *pUART_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART_LSR; /* Clear status bit */
- uart_rbr_val = *pUART_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART_THR = ch; /* putc() */
-
- return;
-}
+++ /dev/null
-/*
- * U-boot - bf561_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf561_SERIAL_H
-#define _Bf561_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
+++ /dev/null
-/*
- * U-boot - start.S Startup file of u-boot for BF533/BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /*
- * As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /*
- * Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
- p0.h = hi(SICA_IWR0);
- p0.l = lo(SICA_IWR0);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- /*
- * Check if the code is in SDRAM
- * If the code is in SDRAM, skip SDRAM initializaiton
- */
- call get_pc;
- r3.l = 0x0;
- r3.h = 0x2000;
- cc = r0 < r3 (iu);
- if cc jump sdram_initialized;
- call init_sdram;
- /* relocate into to RAM */
-sdram_initialized:
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(IMDMA_D0_IRQ_STATUS);
- p0.l = lo(IMDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end: nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
+++ /dev/null
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n", addr,
- last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data)
- addr = *pDCPLB_FAULT_ADDR;
- else
- addr = *pICPLB_FAULT_ADDR;
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
-trap_c_return:
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", fp->rete,
- fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", fp->r0,
- fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", fp->r4,
- fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", fp->p0,
- fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0,
- fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1,
- fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0,
- fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1,
- fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2,
- fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3,
- fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
+++ /dev/null
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
--- /dev/null
+bootrom-asm-offsets.[chs]
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Licensed under the GPL-2 or later.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+EXTRA :=
+CEXTRA := initcode.o
+SEXTRA := start.o
+SOBJS := interrupt.o cache.o flush.o
+COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
+
+ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+COBJS += initcode.o
+endif
+
+SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+EXTRA := $(addprefix $(obj),$(EXTRA))
+CEXTRA := $(addprefix $(obj),$(CEXTRA))
+SEXTRA := $(addprefix $(obj),$(SEXTRA))
+
+all: $(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(OBJS): $(obj)bootrom-asm-offsets.h
+$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
+ echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp
+ mv $@.tmp $@
+$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c
+ $(CC) $(CFLAGS) -S $^ -o $@.tmp
+ mv $@.tmp $@
+$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s
+ sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@
+
+# make sure our initcode (which goes into LDR) does not
+# have relocs or external references
+READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
+check_initcode: $(obj)initcode.o
+ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+ @if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
+ echo "$< contains external references!" 1>&2 ; \
+ exit 1 ; \
+ fi
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#!/usr/bin/gawk -f
+BEGIN {
+ print "/* DO NOT EDIT: AUTOMATICALLY GENERATED"
+ print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in"
+ print " * DO NOT EDIT: AUTOMATICALLY GENERATED"
+ print " */"
+ print ""
+ system("cat bootrom-asm-offsets.c.in")
+ print "{"
+}
+
+{
+ /* find a structure definition */
+ if ($0 ~ /typedef struct .* {/) {
+ delete members;
+ i = 0;
+
+ /* extract each member of the structure */
+ while (1) {
+ getline
+ if ($1 == "}")
+ break;
+ gsub(/[*;]/, "");
+ members[i++] = $NF;
+ }
+
+ /* grab the structure's name */
+ struct = $NF;
+ sub(/;$/, "", struct);
+
+ /* output the DEFINE() macros */
+ while (i-- > 0)
+ print "\tDEFINE(" struct ", " members[i] ");"
+ print ""
+ }
+}
+
+END {
+ print "\treturn 0;"
+ print "}"
+}
--- /dev/null
+/* A little trick taken from the kernel asm-offsets.h where we convert
+ * the C structures automatically into a bunch of defines for use in
+ * the assembly files.
+ */
+
+#include <linux/stddef.h>
+#include <asm/mach-common/bits/bootrom.h>
+
+#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
+
+int main(int argc, char *argv[])
--- /dev/null
+/* cache.S - low level cache handling routines
+ * Copyright (C) 2003-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+.align 2
+ENTRY(_blackfin_icache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ IFLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ IFLUSH[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_icache_flush_range)
+
+ENTRY(_blackfin_dcache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ FLUSH[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_dcache_flush_range)
+
+ENTRY(_blackfin_dcache_invalidate_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSHINV[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+
+ /*
+ * If the data crosses a cache line, then we'll be pointing to
+ * the last cache line, but won't have flushed/invalidated it yet, so do
+ * one more.
+ */
+ FLUSHINV[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_dcache_invalidate_range)
--- /dev/null
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <asm/mach-common/bits/trace.h>
+
+#include "cpu.h"
+#include "serial.h"
+
+void icache_enable(void)
+{
+ bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
+ SSYNC();
+}
+
+void icache_disable(void)
+{
+ bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
+ SSYNC();
+}
+
+int icache_status(void)
+{
+ return bfin_read_IMEM_CONTROL() & ENICPLB;
+}
+
+void dcache_enable(void)
+{
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
+ SSYNC();
+}
+
+void dcache_disable(void)
+{
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
+ SSYNC();
+}
+
+int dcache_status(void)
+{
+ return bfin_read_DMEM_CONTROL() & ENDCPLB;
+}
+
+__attribute__ ((__noreturn__))
+void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
+{
+ /* Build a NOP slide over the LDR jump block. Whee! */
+ serial_early_puts("NOP Slide\n");
+ char nops[0xC];
+ memset(nops, 0x00, sizeof(nops));
+ extern char _stext_l1;
+ memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
+
+ if (!loaded_from_ldr) {
+ /* Relocate sections into L1 if the LDR didn't do it -- don't
+ * check length because the linker script does the size
+ * checking at build time.
+ */
+ serial_early_puts("L1 Relocate\n");
+ extern char _stext_l1, _etext_l1, _stext_l1_lma;
+ memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
+ extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
+ memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
+ }
+#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+ /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
+ * after it has finished loading the LDR. So configure it again.
+ */
+ else
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+#endif
+
+#ifdef CONFIG_DEBUG_DUMP
+ /* Turn on hardware trace buffer */
+ bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
+#endif
+
+#ifndef CONFIG_PANIC_HANG
+ /* Reset upon a double exception rather than just hanging.
+ * Do not do bfin_read on SWRST as that will reset status bits.
+ */
+ bfin_write_SWRST(DOUBLE_FAULT);
+#endif
+
+ serial_early_puts("Board init flash\n");
+ board_init_f(bootflag);
+}
+
+int exception_init(void)
+{
+ bfin_write_EVT3(trap);
+ return 0;
+}
+
+int irq_init(void)
+{
+#ifdef SIC_IMASK0
+ bfin_write_SIC_IMASK0(0);
+ bfin_write_SIC_IMASK1(0);
+# ifdef SIC_IMASK2
+ bfin_write_SIC_IMASK2(0);
+# endif
+#elif defined(SICA_IMASK0)
+ bfin_write_SICA_IMASK0(0);
+ bfin_write_SICA_IMASK1(0);
+#else
+ bfin_write_SIC_IMASK(0);
+#endif
+ bfin_write_EVT2(evt_default); /* NMI */
+ bfin_write_EVT5(evt_default); /* hardware error */
+ bfin_write_EVT6(evt_default); /* core timer */
+ bfin_write_EVT7(evt_default);
+ bfin_write_EVT8(evt_default);
+ bfin_write_EVT9(evt_default);
+ bfin_write_EVT10(evt_default);
+ bfin_write_EVT11(evt_default);
+ bfin_write_EVT12(evt_default);
+ bfin_write_EVT13(evt_default);
+ bfin_write_EVT14(evt_default);
+ bfin_write_EVT15(evt_default);
+ bfin_write_ILAT(0);
+ CSYNC();
+ /* enable all interrupts except for core timer */
+ irq_flags = 0xffffffbf;
+ local_irq_enable();
+ CSYNC();
+ return 0;
+}
/*
- * U-boot - start1.S Code running out of RAM after relocation
+ * U-boot - cpu.h
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02110-1301 USA
*/
-#define ASSEMBLY
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
+#ifndef _CPU_H_
+#define _CPU_H_
-.global start1;
-.global _start1;
+#include <command.h>
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
+void board_reset(void) __attribute__((__weak__));
+void bfin_reset_or_hang(void) __attribute__((__noreturn__));
+void bfin_panic(struct pt_regs *reg);
+void dump(struct pt_regs *regs);
+
+asmlinkage void trap(void);
+asmlinkage void evt_default(void);
+
+#endif
--- /dev/null
+/* flush.S - low level cache flushing routines
+ * Copyright (C) 2003-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/mpu.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(_flush_data_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = HI(DCPLB_ADDR0);
+ P5.L = LO(DCPLB_ADDR0);
+ P4.H = HI(DCPLB_DATA0);
+ P4.L = LO(DCPLB_DATA0);
+ R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+ R6 = 16;
+.Lnext: R0 = [P5++];
+ R1 = [P4++];
+ CC = BITTST(R1, 14); /* Is it write-through?*/
+ IF CC JUMP .Lskip; /* If so, ignore it.*/
+ R2 = R1 & R7; /* Is it a dirty, cached page?*/
+ CC = R2;
+ IF !CC JUMP .Lskip; /* If not, ignore it.*/
+ [--SP] = RETS;
+ CALL _dcplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+.Lskip: R6 += -1;
+ CC = R6;
+ IF CC JUMP .Lnext;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+ENDPROC(_flush_data_cache)
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(_dcplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP .Ldflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* The page could be mapped into Bank A or Bank B, depending
+ * on (a) whether both banks are configured as cache, and
+ * (b) on whether address bit A[x] is set. x is determined
+ * by DCBS in DMEM_CONTROL
+ */
+
+ R2 = 0; /* Default to Bank A (Bank B would be 1)*/
+
+ P0.L = LO(DMEM_CONTROL);
+ P0.H = HI(DMEM_CONTROL);
+
+ R3 = [P0]; /* If Bank B is not enabled as cache*/
+ CC = BITTST(R3, 2); /* then Bank A is our only option.*/
+ IF CC JUMP .Lbank_chosen;
+
+ R4 = 1<<14; /* If DCBS==0, use A[14].*/
+ R5 = R4 << 7; /* If DCBS==1, use A[23];*/
+ CC = BITTST(R3, 4);
+ IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
+ R5 = R0 & R4; /* Use it to test the Page address*/
+ CC = R5; /* and if that bit is set, we use Bank B,*/
+ R2 = CC; /* else we use Bank A.*/
+ R2 <<= 23; /* The Bank selection's at posn 23.*/
+
+.Lbank_chosen:
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /*Anamoly 05000209*/
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
+ /* Save in extraction pattern for later deposit.*/
+ R3.H = R4.L << 0;
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R2 = Bank select mask
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = LO(DTEST_COMMAND);
+ P5.H = HI(DTEST_COMMAND);
+ P4.L = LO(DTEST_DATA0);
+ P4.H = HI(DTEST_DATA0);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 2;
+ LSETUP (.Lfs1, .Lfe1) LC1 = P2;
+.Lfs1: P0 = 64; /* iterate over all sets*/
+ LSETUP (.Lfs0, .Lfe0) LC0 = P0;
+.Lfs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
+ BITSET(R6,14);
+ [P5] = R6; /* Issue Command*/
+ SSYNC;
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP .Lfskip; /* and skip if not.*/
+ CC = BITTST(R7, 1); /* Check if dirty*/
+ IF !CC JUMP .Lfskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ SSYNC;
+ FLUSHINV [P3]; /* And flush the entry*/
+.Lfskip:
+.Lfe0: R5 += 1; /* Advance to next Set*/
+.Lfe1: BITSET(R2, 26); /* Go to next Way.*/
+
+.Ldfinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+.Ldflush_whole_page:
+
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (.Leall, .Leall) LC0 = P1;
+.Leall: FLUSHINV [P0++];
+ SSYNC;
+ JUMP .Ldfinished;
+ENDPROC(_dcplb_flush)
+
+.align 4;
+page_prefix_table:
+.byte4 0xFFFFFC00; /* 1K */
+.byte4 0xFFFFF000; /* 4K */
+.byte4 0xFFF00000; /* 1M */
+.byte4 0xFFC00000; /* 4M */
+.page_prefix_table.end:
-/****************************************************************
- * $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
- * *
- * Description: *
- * *
- * Maintainer: sonicz <sonic.zhang@analog.com> *
- * *
- * CopyRight (c) 2006 Analog Device *
- * All rights reserved. *
- * *
- * This file is free software; *
- * you are free to modify and/or redistribute it *
- * under the terms of the GNU General Public Licence (GPL).*
- * *
- ****************************************************************/
+/*
+ * i2c.c - driver for Blackfin on-chip TWI/I2C
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
#include <common.h>
#include <asm/io.h>
#include <asm/mach-common/bits/twi.h>
-DECLARE_GLOBAL_DATA_PTR;
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#ifdef TWI0_CLKDIV
+#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV()
+#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
+#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL()
+#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
+#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL()
+#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val)
+#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT()
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val)
+#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR()
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val)
+#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
+#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
+#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR()
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
+#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
+#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
+#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK()
+#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
+#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL()
+#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
+#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT()
+#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val)
+#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8()
+#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
+#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16()
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val)
+#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
+#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val)
+#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16()
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val)
+#endif
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
+ DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)
/**
* i2c_reset: - reset the host controller
- *
*/
-
static void i2c_reset(void)
{
/* Disable TWI */
bfin_write_TWI_CONTROL(0);
- sync();
+ SSYNC();
/* Set TWI internal clock as 10MHz */
bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
/* Enable TWI */
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
- sync();
+ SSYNC();
}
int wait_for_completion(struct i2c_msg *msg, int timeout_count)
} else if (msg->flags & I2C_M_STOP)
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
- sync();
+ SSYNC();
/* Clear status */
bfin_write_TWI_INT_STAT(XMTSERV);
- sync();
+ SSYNC();
i = 0;
}
if (RCVSERV & twi_int_stat) {
} else if (msg->flags & I2C_M_STOP) {
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
- sync();
+ SSYNC();
}
/* Clear interrupt source */
bfin_write_TWI_INT_STAT(RCVSERV);
- sync();
+ SSYNC();
i = 0;
}
if (MERR & twi_int_stat) {
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_STAT(0x3e);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
/*
* if both err and complete int stats are set,
* return proper results.
bfin_write_TWI_INT_STAT(MCOMP);
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
/*
* If it is a quick transfer,
* only address bug no data, not an err.
}
if (MCOMP & twi_int_stat) {
bfin_write_TWI_INT_STAT(MCOMP);
- sync();
+ SSYNC();
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
return 0;
}
}
goto transfer_error;
}
- while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
+ while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
+ continue;
/* Set Transmit device address */
bfin_write_TWI_MASTER_ADDR(msg->addr);
* Data in FIFO should be discarded before start a new operation.
*/
bfin_write_TWI_FIFO_CTL(0x3);
- sync();
+ SSYNC();
bfin_write_TWI_FIFO_CTL(0);
- sync();
+ SSYNC();
if (!(msg->flags & I2C_M_RD)) {
/* Transmit first data */
len);
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
msg->len--;
- sync();
+ SSYNC();
}
}
/* Interrupt mask . Enable XMT, RCV interrupt */
bfin_write_TWI_INT_MASK(MCOMP | MERR |
((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
- sync();
+ SSYNC();
if (len > 0 && len <= 255)
bfin_write_TWI_MASTER_CTL((len << 6));
((msg->flags & I2C_M_RD)
? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
100) ? FAST : 0));
- sync();
+ SSYNC();
ret = wait_for_completion(msg, timeout_count);
PRINTD("3 in i2c_transfer: ret=%d\n", ret);
-transfer_error:
+ transfer_error:
switch (ret) {
case 1:
PRINTD(("i2c_transfer: error: transfer fail\n"));
i2c_write(chip, reg, 0, &val, 1);
}
-#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * initcode.c - Initialize the processor. This is usually entails things
+ * like external memory, voltage regulators, etc... Note that this file
+ * cannot make any function calls as it may be executed all by itself by
+ * the Blackfin's bootrom in LDR format.
+ *
+ * Copyright (c) 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
+
+#define BFIN_IN_INITCODE
+#include "serial.h"
+
+__attribute__((always_inline))
+static inline uint32_t serial_init(void)
+{
+#ifdef __ADSPBF54x__
+# ifdef BFIN_BOOT_UART_USE_RTS
+# define BFIN_UART_USE_RTS 1
+# else
+# define BFIN_UART_USE_RTS 0
+# endif
+ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ size_t i;
+
+ /* force RTS rather than relying on auto RTS */
+ bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
+
+ /* Wait for the line to clear up. We cannot rely on UART
+ * registers as none of them reflect the status of the RSR.
+ * Instead, we'll sleep for ~10 bit times at 9600 baud.
+ * We can precalc things here by assuming boot values for
+ * PLL rather than loading registers and calculating.
+ * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
+ * EDB0 = 0
+ * Divisor = (SCLK / baud) / 16
+ * SCLK = baud * 16 * Divisor
+ * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
+ * CCLK = (16 * Divisor * 5) * (9600 / 10)
+ * In reality, this will probably be just about 1 second delay,
+ * so assuming 9600 baud is OK (both as a very low and too high
+ * speed as this will buffer things enough).
+ */
+#define _NUMBITS (10) /* how many bits to delay */
+#define _LOWBAUD (9600) /* low baud rate */
+#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
+#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
+#define _NUMINS (3) /* how many instructions in loop */
+#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
+ i = _CCLK;
+ while (i--)
+ asm volatile("" : : : "memory");
+ }
+#endif
+
+ uint32_t old_baud = serial_early_get_baud();
+
+ if (BFIN_DEBUG_EARLY_SERIAL) {
+ serial_early_init();
+
+ /* If the UART is off, that means we need to program
+ * the baud rate ourselves initially.
+ */
+ if (!old_baud) {
+ old_baud = CONFIG_BAUDRATE;
+ serial_early_set_baud(CONFIG_BAUDRATE);
+ }
+ }
+
+ return old_baud;
+}
+
+__attribute__((always_inline))
+static inline void serial_deinit(void)
+{
+#ifdef __ADSPBF54x__
+ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ /* clear forced RTS rather than relying on auto RTS */
+ bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
+ }
+#endif
+}
+
+/* We need to reset the baud rate when we have early debug turned on
+ * or when we are booting over the UART.
+ * XXX: we should fix this to calc the old baud and restore it rather
+ * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
+ * to figure out how to avoid the division in the baud calc ...
+ */
+__attribute__((always_inline))
+static inline void serial_reset_baud(uint32_t baud)
+{
+ if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+ return;
+
+#ifndef CONFIG_LDR_LOAD_BAUD
+# define CONFIG_LDR_LOAD_BAUD 115200
+#endif
+
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+ serial_early_set_baud(baud);
+ else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+ serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
+ else
+ serial_early_set_baud(CONFIG_BAUDRATE);
+}
+
+__attribute__((always_inline))
+static inline void serial_putc(char c)
+{
+ if (!BFIN_DEBUG_EARLY_SERIAL)
+ return;
+
+ if (c == '\n')
+ *pUART_THR = '\r';
+
+ *pUART_THR = c;
+
+ while (!(*pUART_LSR & TEMT))
+ continue;
+}
+
+
+/* Max SCLK can be 133MHz ... dividing that by 4 gives
+ * us a freq of 33MHz for SPI which should generally be
+ * slow enough for the slow reads the bootrom uses.
+ */
+#ifndef CONFIG_SPI_BAUD_INITBLOCK
+# define CONFIG_SPI_BAUD_INITBLOCK 4
+#endif
+
+/* PLL_DIV defines */
+#ifndef CONFIG_PLL_DIV_VAL
+# if (CONFIG_CCLK_DIV == 1)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+# elif (CONFIG_CCLK_DIV == 2)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+# elif (CONFIG_CCLK_DIV == 4)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+# elif (CONFIG_CCLK_DIV == 8)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+# else
+# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+# endif
+# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
+#endif
+
+#ifndef CONFIG_PLL_LOCKCNT_VAL
+# define CONFIG_PLL_LOCKCNT_VAL 0x0300
+#endif
+
+#ifndef CONFIG_PLL_CTL_VAL
+# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9))
+#endif
+
+#ifndef CONFIG_EBIU_RSTCTL_VAL
+# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
+#endif
+
+#ifndef CONFIG_EBIU_MBSCTL_VAL
+# define CONFIG_EBIU_MBSCTL_VAL 0
+#endif
+
+/* Make sure our voltage value is sane so we don't blow up! */
+#ifndef CONFIG_VR_CTL_VAL
+# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
+# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
+# define CCLK_VLEV_120 400000000
+# define CCLK_VLEV_125 533000000
+# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+# define CCLK_VLEV_120 401000000
+# define CCLK_VLEV_125 401000000
+# elif defined(__ADSPBF561__)
+# define CCLK_VLEV_120 300000000
+# define CCLK_VLEV_125 501000000
+# endif
+# if BFIN_CCLK < CCLK_VLEV_120
+# define CONFIG_VR_CTL_VLEV VLEV_120
+# elif BFIN_CCLK < CCLK_VLEV_125
+# define CONFIG_VR_CTL_VLEV VLEV_125
+# else
+# define CONFIG_VR_CTL_VLEV VLEV_130
+# endif
+# if defined(__ADSPBF52x__) /* TBD; use default */
+# undef CONFIG_VR_CTL_VLEV
+# define CONFIG_VR_CTL_VLEV VLEV_110
+# elif defined(__ADSPBF54x__) /* TBD; use default */
+# undef CONFIG_VR_CTL_VLEV
+# define CONFIG_VR_CTL_VLEV VLEV_120
+# endif
+
+# ifdef CONFIG_BFIN_MAC
+# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
+# else
+# define CONFIG_VR_CTL_CLKBUF 0
+# endif
+
+# if defined(__ADSPBF52x__)
+# define CONFIG_VR_CTL_FREQ FREQ_1000
+# else
+# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
+# endif
+
+# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
+#endif
+
+__attribute__((saveall))
+void initcode(ADI_BOOT_DATA *bootstruct)
+{
+ uint32_t old_baud = serial_init();
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
+# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
+# endif
+ /* Program the watchdog with an initial timeout of ~20 seconds.
+ * Hopefully that should be long enough to load the u-boot LDR
+ * (from wherever) and then the common u-boot code can take over.
+ * In bypass mode, the start.S would have already set a much lower
+ * timeout, so don't clobber that.
+ */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
+ bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
+ bfin_write_WDOG_CTL(0);
+ }
+#endif
+
+ serial_putc('S');
+
+ /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
+ * fast read, so we need to slow down the SPI clock a lot more during
+ * boot. Once we switch over to u-boot's SPI flash driver, we'll
+ * increase the speed appropriately.
+ */
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#ifdef SPI0_BAUD
+ bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
+#else
+ bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
+#endif
+
+ serial_putc('B');
+
+ /* Disable all peripheral wakeups except for the PLL event. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(1);
+ bfin_write_SIC_IWR1(0);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(0);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(1);
+ bfin_write_SICA_IWR1(0);
+#else
+ bfin_write_SIC_IWR(1);
+#endif
+
+ serial_putc('L');
+
+ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
+
+ serial_putc('A');
+
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
+ asm("idle;");
+ }
+
+ serial_putc('C');
+
+ bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
+
+ serial_putc('K');
+
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
+ asm("idle;");
+ }
+
+ /* Since we've changed the SCLK above, we may need to update
+ * the UART divisors (UART baud rates are based on SCLK).
+ */
+ serial_reset_baud(old_baud);
+
+ serial_putc('F');
+
+ /* Program the async banks controller. */
+ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+ bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+#ifdef EBIU_MODE
+ /* Not all parts have these additional MMRs. */
+ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+ bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+ bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+#endif
+
+ serial_putc('I');
+
+ /* Program the external memory controller. */
+#ifdef EBIU_RSTCTL
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
+ bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
+ bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
+ bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
+# ifdef CONFIG_EBIU_DDRCTL3_VAL
+ /* default is disable, so don't need to force this */
+ bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
+# endif
+#else
+ bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
+ bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
+ bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+#endif
+
+ serial_putc('N');
+
+ /* Restore all peripheral wakeups. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(-1);
+ bfin_write_SIC_IWR1(-1);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(-1);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(-1);
+ bfin_write_SICA_IWR1(-1);
+#else
+ bfin_write_SIC_IWR(-1);
+#endif
+
+ serial_putc('>');
+ serial_putc('\n');
+
+ serial_deinit();
+}
--- /dev/null
+/*
+ * interrupt.S - trampoline default exceptions/interrupts to C handlers
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/blackfin.h>
+#include <asm/entry.h>
+
+.text
+
+/* default entry point for exceptions */
+ENTRY(_trap)
+ SAVE_ALL_SYS
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
+ sp += -12;
+ call _trap_c;
+ sp += 12;
+ RESTORE_ALL_SYS
+ rtx;
+ENDPROC(_trap)
+
+/* default entry point for interrupts */
+ENTRY(_evt_default)
+ SAVE_ALL_SYS
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
+ sp += -12;
+ call _bfin_panic;
+ sp += 12;
+ RESTORE_ALL_SYS
+ rti;
+ENDPROC(_evt_default)
/*
* U-boot - interrupts.c Interrupt related routines
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* This file is based on interrupts.c
* Copyright 1996 Roman Zippel
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
#include <common.h>
/*
* This function is derived from PowerPC code (read timebase as long long).
- * On BF561 it just returns the timer value.
+ * On Blackfin it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
/*
* This function is derived from PowerPC code (timebase clock frequency).
- * On BF561 it returns the number of timer ticks per second.
+ * On Blackfin it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
void enable_interrupts(void)
{
+ local_irq_restore(int_flag);
}
int disable_interrupts(void)
{
+ local_irq_save(int_flag);
return 1;
}
-int interrupt_init(void)
-{
- return (0);
-}
-
void udelay(unsigned long usec)
{
unsigned long delay, start, stop;
usec -= 1000;
}
- asm volatile (" %0 = CYCLES;":"=r" (start));
+ asm volatile (" %0 = CYCLES;" : "=r" (start));
do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
+ asm volatile (" %0 = CYCLES; " : "=r" (stop));
} while (stop - start < delay);
}
return;
}
-void timer_init(void)
+#define MAX_TIM_LOAD 0xFFFFFFFF
+int timer_init(void)
{
*pTCNTL = 0x1;
*pTSCALE = 0x0;
timestamp = 0;
last_time = 0;
+
+ return 0;
}
/*
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
/*
- * Find the number of millisonds
- * that got elapsed before this TCOUNT
- * cycle
+ * Find the number of millisonds that
+ * got elapsed before this TCOUNT cycle
*/
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
return (milisec - base);
}
+
+void reset_timer(void)
+{
+ timestamp = 0;
+}
--- /dev/null
+/*
+ * reset.c - logic for resetting the cpu
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+/* A system soft reset makes external memory unusable so force
+ * this function into L1. We use the compiler ssync here rather
+ * than SSYNC() because it's safe (no interrupts and such) and
+ * we save some L1. We do not need to force sanity in the SYSCR
+ * register as the BMODE selection bit is cleared by the soft
+ * reset while the Core B bit (on dual core parts) is cleared by
+ * the core reset.
+ */
+__attribute__ ((__l1_text__, __noreturn__))
+void bfin_reset(void)
+{
+ /* Wait for completion of "system" events such as cache line
+ * line fills so that we avoid infinite stalls later on as
+ * much as possible. This code is in L1, so it won't trigger
+ * any such event after this point in time.
+ */
+ __builtin_bfin_ssync();
+
+ while (1) {
+ /* Initiate System software reset. */
+ bfin_write_SWRST(0x7);
+
+ /* Due to the way reset is handled in the hardware, we need
+ * to delay for 7 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 7. For now,
+ * we'll assume worse case which is a 1:15 ratio.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC0 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 7)
+ : "LC0", "LB0", "LT0"
+ );
+
+ /* Clear System software reset */
+ bfin_write_SWRST(0);
+
+ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
+ * though as the System state is all reset now.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC1 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 1)
+ : "LC1", "LB1", "LT1"
+ );
+
+ /* Issue core reset */
+ asm("raise 1");
+ }
+}
+
+/* We need to trampoline ourselves up into L1 since our linker
+ * does not have relaxtion support and will only generate a
+ * PC relative call with a 25 bit immediate. This is not enough
+ * to get us from the top of SDRAM into L1.
+ */
+__attribute__ ((__noreturn__))
+static inline void bfin_reset_trampoline(void)
+{
+ if (board_reset)
+ board_reset();
+ while (1)
+ asm("jump (%0);" : : "a" (bfin_reset));
+}
+
+__attribute__ ((__noreturn__))
+void bfin_reset_or_hang(void)
+{
+#ifdef CONFIG_PANIC_HANG
+ hang();
+#else
+ bfin_reset_trampoline();
+#endif
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ bfin_reset_trampoline();
+ return 0;
+}
--- /dev/null
+/*
+ * U-boot - serial.c Blackfin Serial Driver
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
+ * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
+ * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0)
+# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+#endif
+
+#include "serial.h"
+
+/* Symbol for our assembly to call. */
+void serial_set_baud(uint32_t baud)
+{
+ serial_early_set_baud(baud);
+}
+
+/* Symbol for common u-boot code to call.
+ * Setup the baudrate (brg: baudrate generator).
+ */
+void serial_setbrg(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ serial_set_baud(gd->baudrate);
+}
+
+/* Symbol for our assembly to call. */
+void serial_initialize(void)
+{
+ serial_early_init();
+}
+
+/* Symbol for common u-boot code to call. */
+int serial_init(void)
+{
+ serial_initialize();
+ serial_setbrg();
+ return 0;
+}
+
+void serial_putc(const char c)
+{
+ /* send a \r for compatibility */
+ if (c == '\n')
+ serial_putc('\r');
+
+ WATCHDOG_RESET();
+
+ /* wait for the hardware fifo to clear up */
+ while (!(*pUART_LSR & THRE))
+ continue;
+
+ /* queue the character for transmission */
+ *pUART_THR = c;
+ SSYNC();
+
+ WATCHDOG_RESET();
+
+ /* wait for the byte to be shifted over the line */
+ while (!(*pUART_LSR & TEMT))
+ continue;
+}
+
+int serial_tstc(void)
+{
+ WATCHDOG_RESET();
+ return (*pUART_LSR & DR) ? 1 : 0;
+}
+
+int serial_getc(void)
+{
+ uint16_t uart_lsr_val, uart_rbr_val;
+
+ /* wait for data ! */
+ while (!serial_tstc())
+ continue;
+
+ /* clear the status and grab the new byte */
+ uart_lsr_val = *pUART_LSR;
+ uart_rbr_val = *pUART_RBR;
+
+ if (uart_lsr_val & (OE|PE|FE|BI)) {
+ /* Some parts are read-to-clear while others are
+ * write-to-clear. Just do the write for everyone
+ * since it cant hurt (other than code size).
+ */
+ *pUART_LSR = (OE|PE|FE|BI);
+ return -1;
+ }
+
+ return uart_rbr_val & 0xFF;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL_H__
+#define __BFIN_CPU_SERIAL_H__
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define BFIN_DEBUG_EARLY_SERIAL 1
+#else
+# define BFIN_DEBUG_EARLY_SERIAL 0
+#endif
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+#ifndef UART_LSR
+# if (CONFIG_UART_CONSOLE == 3)
+# define pUART_DLH pUART3_DLH
+# define pUART_DLL pUART3_DLL
+# define pUART_GCTL pUART3_GCTL
+# define pUART_IER pUART3_IER
+# define pUART_IERC pUART3_IER_CLEAR
+# define pUART_LCR pUART3_LCR
+# define pUART_LSR pUART3_LSR
+# define pUART_RBR pUART3_RBR
+# define pUART_THR pUART3_THR
+# define UART_THR UART3_THR
+# define UART_LSR UART3_LSR
+# elif (CONFIG_UART_CONSOLE == 2)
+# define pUART_DLH pUART2_DLH
+# define pUART_DLL pUART2_DLL
+# define pUART_GCTL pUART2_GCTL
+# define pUART_IER pUART2_IER
+# define pUART_IERC pUART2_IER_CLEAR
+# define pUART_LCR pUART2_LCR
+# define pUART_LSR pUART2_LSR
+# define pUART_RBR pUART2_RBR
+# define pUART_THR pUART2_THR
+# define UART_THR UART2_THR
+# define UART_LSR UART2_LSR
+# elif (CONFIG_UART_CONSOLE == 1)
+# define pUART_DLH pUART1_DLH
+# define pUART_DLL pUART1_DLL
+# define pUART_GCTL pUART1_GCTL
+# define pUART_IER pUART1_IER
+# define pUART_IERC pUART1_IER_CLEAR
+# define pUART_LCR pUART1_LCR
+# define pUART_LSR pUART1_LSR
+# define pUART_RBR pUART1_RBR
+# define pUART_THR pUART1_THR
+# define UART_THR UART1_THR
+# define UART_LSR UART1_LSR
+# elif (CONFIG_UART_CONSOLE == 0)
+# define pUART_DLH pUART0_DLH
+# define pUART_DLL pUART0_DLL
+# define pUART_GCTL pUART0_GCTL
+# define pUART_IER pUART0_IER
+# define pUART_IERC pUART0_IER_CLEAR
+# define pUART_LCR pUART0_LCR
+# define pUART_LSR pUART0_LSR
+# define pUART_RBR pUART0_RBR
+# define pUART_THR pUART0_THR
+# define UART_THR UART0_THR
+# define UART_LSR UART0_LSR
+# endif
+#endif
+
+#ifndef __ASSEMBLY__
+
+/* We cannot use get_sclk() in initcode as it is defined elsewhere. */
+#ifdef BFIN_IN_INITCODE
+# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
+#endif
+
+#ifdef __ADSPBF54x__
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+# define CLEAR_IER() (*pUART_IERC = 0)
+#else
+# define ACCESS_LATCH() (*pUART_LCR |= DLAB)
+# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB)
+# define CLEAR_IER() (*pUART_IER = 0)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_do_portmux(void)
+{
+#ifdef __ADSPBF52x__
+# define DO_MUX(port, mux, tx, rx) \
+ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
+ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
+ case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
+ }
+ SSYNC();
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+# define DO_MUX(func, tx, rx) \
+ bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(PFDE, 0, 1); break;
+ case 1: DO_MUX(PFTE, 2, 3); break;
+ }
+ SSYNC();
+#elif defined(__ADSPBF54x__)
+# define DO_MUX(port, tx, rx) \
+ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
+ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
+ case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
+ case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
+ case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
+ }
+ SSYNC();
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_early_init(void)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ /* Enable UART */
+ *pUART_GCTL = UCEN;
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ *pUART_LCR = WLS_8;
+
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_baud(void)
+{
+ /* If the UART isnt enabled, then we are booting an LDR
+ * from a non-UART source (so like flash) which means
+ * the baud rate here is meaningless.
+ */
+ if ((*pUART_GCTL & UCEN) != UCEN)
+ return 0;
+
+#if (0) /* See comment for serial_reset_baud() in initcode.c */
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ uint8_t dll = *pUART_DLL;
+ uint8_t dlh = *pUART_DLH;
+ uint16_t divisor = (dlh << 8) | dll;
+ uint32_t baud = get_sclk() / (divisor * 16);
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+
+ return baud;
+#else
+ return CONFIG_BAUDRATE;
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t baud)
+{
+ /* Translate from baud into divisor in terms of SCLK.
+ * The +1 is to make sure we over sample just a little
+ * rather than under sample the incoming signals.
+ */
+ uint16_t divisor = (get_sclk() / (baud * 16)) + 1;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ *pUART_DLL = LOB(divisor);
+ *pUART_DLH = HIB(divisor);
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+#ifndef BFIN_IN_INITCODE
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+ if (BFIN_DEBUG_EARLY_SERIAL) {
+ serial_puts("Early: ");
+ serial_puts(s);
+ }
+}
+#endif
+
+#else
+
+.macro serial_early_init
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ call _serial_initialize;
+#endif
+.endm
+
+.macro serial_early_set_baud
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ R0.L = LO(CONFIG_BAUDRATE);
+ R0.H = HI(CONFIG_BAUDRATE);
+ call _serial_set_baud;
+#endif
+.endm
+
+/* Recursively expand calls to _serial_putc for every byte
+ * passed to us. Append a newline when we're all done.
+ */
+.macro _serial_early_putc byte:req morebytes:vararg
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ R0 = \byte;
+ call _serial_putc;
+.ifnb \morebytes
+ _serial_early_putc \morebytes
+.else
+.if (\byte != '\n')
+ _serial_early_putc '\n'
+.endif
+.endif
+#endif
+.endm
+
+/* Wrapper around recurisve _serial_early_putc macro which
+ * simply prepends the string "Early: "
+ */
+.macro serial_early_putc byte:req morebytes:vararg
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ _serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes
+#endif
+.endm
+
+/* Since we embed the string right into our .text section, we need
+ * to find its address. We do this by getting our PC and adding 2
+ * bytes (which is the length of the jump instruction). Then we
+ * pass this address to serial_puts().
+ */
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define serial_early_puts(str) \
+ call _get_pc; \
+ jump 1f; \
+ .ascii "Early:"; \
+ .ascii __FILE__; \
+ .ascii ": "; \
+ .ascii str; \
+ .asciz "\n"; \
+ .align 4; \
+1: \
+ R0 += 2; \
+ call _serial_puts;
+#else
+# define serial_early_puts(str)
+#endif
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - start.S Startup file for Blackfin u-boot
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003 Metrowerks/Motorola
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
+#include "serial.h"
+
+/* It may seem odd that we make calls to functions even though we haven't
+ * relocated ourselves yet out of {flash,ram,wherever}. This is OK because
+ * the "call" instruction in the Blackfin architecture is actually PC
+ * relative. So we can call functions all we want and not worry about them
+ * not being relocated yet.
+ */
+
+.text
+ENTRY(_start)
+
+ /* Set our initial stack to L1 scratch space */
+ sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+ sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
+# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
+# endif
+ /* Program the watchdog with an initial timeout of ~5 seconds.
+ * That should be long enough to bootstrap ourselves up and
+ * then the common u-boot code can take over.
+ */
+ P0.L = LO(WDOG_CNT);
+ P0.H = HI(WDOG_CNT);
+ R0.L = 0;
+ R0.H = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
+ [P0] = R0;
+ /* fire up the watchdog - R0.L above needs to be 0x0000 */
+ W[P0 + (WDOG_CTL - WDOG_CNT)] = R0;
+#endif
+
+ /* Turn on the serial for debugging the init process */
+ serial_early_init
+ serial_early_set_baud
+
+ serial_early_puts("Init Registers");
+
+ /* Disable nested interrupts and enable CYCLES for udelay() */
+ R0 = CCEN | 0x30;
+ SYSCFG = R0;
+
+ /* Zero out registers required by Blackfin ABI.
+ * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
+ */
+ r1 = 0 (x);
+ /* Disable circular buffers */
+ l0 = r1;
+ l1 = r1;
+ l2 = r1;
+ l3 = r1;
+ /* Disable hardware loops in case we were started by 'go' */
+ lc0 = r1;
+ lc1 = r1;
+
+ /* Save RETX so we can pass it while booting Linux */
+ r7 = RETX;
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+ /* In bypass mode, we don't have an LDR with an init block
+ * so we need to explicitly call it ourselves. This will
+ * reprogram our clocks and setup our async banks.
+ */
+ /* XXX: we should DMA this into L1, put external memory into
+ * self refresh, and then jump there ...
+ */
+ call _get_pc;
+ r3 = 0x0;
+ r3.h = 0x2000;
+ cc = r0 < r3 (iu);
+ if cc jump .Lproc_initialized;
+
+ serial_early_puts("Program Clocks");
+
+ call _initcode;
+
+ /* Since we reprogrammed SCLK, we need to update the serial divisor */
+ serial_early_set_baud
+
+.Lproc_initialized:
+#endif
+
+ /* Inform upper layers if we had to do the relocation ourselves.
+ * This allows us to detect whether we were loaded by 'go 0x1000'
+ * or by the bootrom from an LDR. "r6" is "loaded_from_ldr".
+ */
+ r6 = 1 (x);
+
+ /* Relocate from wherever are (FLASH/RAM/etc...) to the
+ * hardcoded monitor location in the end of RAM.
+ */
+ serial_early_puts("Relocate");
+ call _get_pc;
+.Loffset:
+ r2.l = .Loffset;
+ r2.h = .Loffset;
+ r3.l = _start;
+ r3.h = _start;
+ r1 = r2 - r3;
+
+ r0 = r0 - r1;
+
+ cc = r0 == r3;
+ if cc jump .Lnorelocate;
+
+ r6 = 0 (x);
+ p1 = r0;
+
+ p2.l = LO(CFG_MONITOR_BASE);
+ p2.h = HI(CFG_MONITOR_BASE);
+
+ p3 = 0x04;
+ p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
+ p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
+.Lloop1:
+ r1 = [p1 ++ p3];
+ [p2 ++ p3] = r1;
+ cc=p2==p4;
+ if !cc jump .Lloop1;
+
+ /* Initialize BSS section ... we know that memset() does not
+ * use the BSS, so it is safe to call here. The bootrom LDR
+ * takes care of clearing things for us.
+ */
+ serial_early_puts("Zero BSS");
+ r0.l = __bss_start;
+ r0.h = __bss_start;
+ r1 = 0 (x);
+ r2.l = __bss_end;
+ r2.h = __bss_end;
+ r2 = r2 - r0;
+ call _memset;
+
+.Lnorelocate:
+
+ /* Setup the actual stack in external memory */
+ r0.h = HI(CONFIG_STACKBASE);
+ r0.l = LO(CONFIG_STACKBASE);
+ sp = r0;
+ fp = sp;
+
+ /* Now lower ourselves from the highest interrupt level to
+ * the lowest. We do this by masking all interrupts but 15,
+ * setting the 15 handler to "board_init_f", raising the 15
+ * interrupt, and then returning from the highest interrupt
+ * level to the dummy "jump" until the interrupt controller
+ * services the pending 15 interrupt.
+ */
+ serial_early_puts("Lower to 15");
+ r0 = r7;
+ r1 = r6;
+ p0.l = LO(EVT15);
+ p0.h = HI(EVT15);
+ p1.l = _cpu_init_f;
+ p1.h = _cpu_init_f;
+ [p0] = p1;
+ p2.l = LO(IMASK);
+ p2.h = HI(IMASK);
+ p3.l = LO(EVT_IVG15);
+ p3.h = HI(EVT_IVG15);
+ [p2] = p3;
+ raise 15;
+ p4.l = .LWAIT_HERE;
+ p4.h = .LWAIT_HERE;
+ reti = p4;
+ rti;
+
+.LWAIT_HERE:
+ jump .LWAIT_HERE;
+ENDPROC(_start)
+
+LENTRY(_get_pc)
+ r0 = rets;
+#if ANOMALY_05000371
+ NOP;
+ NOP;
+ NOP;
+#endif
+ rts;
+ENDPROC(_get_pc)
--- /dev/null
+/*
+ * system_map.S - optional symbol lookup for debugging
+ *
+ * Copyright (c) 2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_DEBUG_DUMP_SYMS
+.data
+.global _system_map
+.type _system_map,@object
+_system_map:
+#include SYM_FILE
+.asciz ""
+.size _system_map,.-_system_map
+#endif
--- /dev/null
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/traps.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <asm/mach-common/bits/trace.h>
+#include "cpu.h"
+
+#define trace_buffer_save(x) \
+ do { \
+ (x) = bfin_read_TBUFCTL(); \
+ bfin_write_TBUFCTL((x) & ~TBUFEN); \
+ } while (0)
+
+#define trace_buffer_restore(x) \
+ bfin_write_TBUFCTL((x))
+
+/* The purpose of this map is to provide a mapping of address<->cplb settings
+ * rather than an exact map of what is actually addressable on the part. This
+ * map covers all current Blackfin parts. If you try to access an address that
+ * is in this map but not actually on the part, you won't get an exception and
+ * reboot, you'll get an external hardware addressing error and reboot. Since
+ * only the ends matter (you did something wrong and the board reset), the means
+ * are largely irrelevant.
+ */
+struct memory_map {
+ uint32_t start, end;
+ uint32_t data_flags, inst_flags;
+};
+const struct memory_map const bfin_memory_map[] = {
+ { /* external memory */
+ .start = 0x00000000,
+ .end = 0x20000000,
+ .data_flags = SDRAM_DGENERIC,
+ .inst_flags = SDRAM_IGENERIC,
+ },
+ { /* async banks */
+ .start = 0x20000000,
+ .end = 0x30000000,
+ .data_flags = SDRAM_EBIU,
+ .inst_flags = SDRAM_INON_CHBL,
+ },
+ { /* everything on chip */
+ .start = 0xE0000000,
+ .end = 0xFFFFFFFF,
+ .data_flags = L1_DMEMORY,
+ .inst_flags = L1_IMEMORY,
+ }
+};
+
+void trap_c(struct pt_regs *regs)
+{
+ uint32_t trapnr = (regs->seqstat & EXCAUSE);
+ bool data = false;
+
+ switch (trapnr) {
+ /* 0x26 - Data CPLB Miss */
+ case VEC_CPLB_M:
+
+ if (ANOMALY_05000261) {
+ static uint32_t last_cplb_fault_retx;
+ /*
+ * Work around an anomaly: if we see a new DCPLB fault,
+ * return without doing anything. Then,
+ * if we get the same fault again, handle it.
+ */
+ if (last_cplb_fault_retx != regs->retx) {
+ last_cplb_fault_retx = regs->retx;
+ return;
+ }
+ }
+
+ data = true;
+ /* fall through */
+
+ /* 0x27 - Instruction CPLB Miss */
+ case VEC_CPLB_I_M: {
+ volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
+ uint32_t new_cplb_addr = 0, new_cplb_data = 0;
+ static size_t last_evicted;
+ size_t i;
+
+ new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
+
+ for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
+ /* if the exception is inside this range, lets use it */
+ if (new_cplb_addr >= bfin_memory_map[i].start &&
+ new_cplb_addr < bfin_memory_map[i].end)
+ break;
+ }
+ if (i == ARRAY_SIZE(bfin_memory_map)) {
+ printf("%cCPLB exception outside of memory map at 0x%p\n",
+ (data ? 'D' : 'I'), new_cplb_addr);
+ bfin_panic(regs);
+ } else
+ debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
+ new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
+
+ /* Turn the cache off */
+ SSYNC();
+ if (data) {
+ asm(" .align 8; ");
+ *pDMEM_CONTROL &= ~ENDCPLB;
+ } else {
+ asm(" .align 8; ");
+ *pIMEM_CONTROL &= ~ENICPLB;
+ }
+ SSYNC();
+
+ if (data) {
+ CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
+ CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
+ } else {
+ CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
+ CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
+ }
+
+ /* find the next unlocked entry and evict it */
+ i = last_evicted & 0xF;
+ debug("last evicted = %i\n", i);
+ CPLB_DATA = CPLB_DATA_BASE + i;
+ while (*CPLB_DATA & CPLB_LOCK) {
+ debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
+ i = (i + 1) & 0xF; /* wrap around */
+ CPLB_DATA = CPLB_DATA_BASE + i;
+ }
+ CPLB_ADDR = CPLB_ADDR_BASE + i;
+
+ debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
+ last_evicted = i + 1;
+ *CPLB_ADDR = new_cplb_addr;
+ *CPLB_DATA = new_cplb_data;
+
+ /* dump current table for debugging purposes */
+ CPLB_ADDR = CPLB_ADDR_BASE;
+ CPLB_DATA = CPLB_DATA_BASE;
+ for (i = 0; i < 16; ++i)
+ debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
+
+ /* Turn the cache back on */
+ SSYNC();
+ if (data) {
+ asm(" .align 8; ");
+ *pDMEM_CONTROL |= ENDCPLB;
+ } else {
+ asm(" .align 8; ");
+ *pIMEM_CONTROL |= ENICPLB;
+ }
+ SSYNC();
+
+ break;
+ }
+
+ default:
+ /* All traps come here */
+ bfin_panic(regs);
+ }
+}
+
+#ifdef CONFIG_DEBUG_DUMP
+# define ENABLE_DUMP 1
+#else
+# define ENABLE_DUMP 0
+#endif
+
+#ifdef CONFIG_DEBUG_DUMP_SYMS
+# define ENABLE_DUMP_SYMS 1
+#else
+# define ENABLE_DUMP_SYMS 0
+#endif
+
+static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+{
+ if (!ENABLE_DUMP_SYMS)
+ return NULL;
+
+ extern const char system_map[] __attribute__((__weak__));
+ const char *sym, *csym;
+ char *esym;
+ unsigned long sym_addr;
+
+ sym = system_map;
+ csym = NULL;
+ *caddr = 0;
+
+ while (*sym) {
+ sym_addr = simple_strtoul(sym, &esym, 16);
+ sym = esym + 1;
+ if (sym_addr > addr)
+ break;
+ *caddr = sym_addr;
+ csym = sym;
+ sym += strlen(sym) + 1;
+ }
+
+ return csym;
+}
+
+static void decode_address(char *buf, unsigned long address)
+{
+ unsigned long sym_addr;
+ const char *sym = symbol_lookup(address, &sym_addr);
+
+ if (sym) {
+ sprintf(buf, "<0x%p> { %s + 0x%x }", address, sym, address - sym_addr);
+ return;
+ }
+
+ if (!address)
+ sprintf(buf, "<0x%p> /* Maybe null pointer? */", address);
+ else if (address >= CFG_MONITOR_BASE &&
+ address < CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ sprintf(buf, "<0x%p> /* somewhere in u-boot */", address);
+ else
+ sprintf(buf, "<0x%p> /* unknown address */", address);
+}
+
+void dump(struct pt_regs *fp)
+{
+ char buf[150];
+ size_t i;
+
+ if (!ENABLE_DUMP)
+ return;
+
+ printf("SEQUENCER STATUS:\n");
+ printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
+ fp->seqstat, fp->ipend, fp->syscfg);
+ printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P);
+ printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P);
+ for (i = 6; i <= 15; ++i) {
+ if (fp->ipend & (1 << i)) {
+ decode_address(buf, bfin_read32(EVT0 + 4*i));
+ printf(" physical IVG%i asserted : %s\n", i, buf);
+ }
+ }
+ decode_address(buf, fp->rete);
+ printf(" RETE: %s\n", buf);
+ decode_address(buf, fp->retn);
+ printf(" RETN: %s\n", buf);
+ decode_address(buf, fp->retx);
+ printf(" RETX: %s\n", buf);
+ decode_address(buf, fp->rets);
+ printf(" RETS: %s\n", buf);
+ decode_address(buf, fp->pc);
+ printf(" PC : %s\n", buf);
+
+ if (fp->seqstat & EXCAUSE) {
+ decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
+ printf("DCPLB_FAULT_ADDR: %s\n", buf);
+ decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
+ printf("ICPLB_FAULT_ADDR: %s\n", buf);
+ }
+
+ printf("\nPROCESSOR STATE:\n");
+ printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
+ fp->r0, fp->r1, fp->r2, fp->r3);
+ printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
+ fp->r4, fp->r5, fp->r6, fp->r7);
+ printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
+ fp->p0, fp->p1, fp->p2, fp->p3);
+ printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
+ fp->p4, fp->p5, fp->fp, fp);
+ printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
+ fp->lb0, fp->lt0, fp->lc0);
+ printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
+ fp->lb1, fp->lt1, fp->lc1);
+ printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
+ fp->b0, fp->l0, fp->m0, fp->i0);
+ printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
+ fp->b1, fp->l1, fp->m1, fp->i1);
+ printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
+ fp->b2, fp->l2, fp->m2, fp->i2);
+ printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
+ fp->b3, fp->l3, fp->m3, fp->i3);
+ printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
+ fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+ printf("USP : %08lx ASTAT: %08lx\n",
+ fp->usp, fp->astat);
+
+ printf("\n");
+}
+
+void dump_bfin_trace_buffer(void)
+{
+ char buf[150];
+ unsigned long tflags;
+ size_t i = 0;
+
+ if (!ENABLE_DUMP)
+ return;
+
+ trace_buffer_save(tflags);
+
+ printf("Hardware Trace:\n");
+
+ if (bfin_read_TBUFSTAT() & TBUFCNT) {
+ for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
+ decode_address(buf, bfin_read_TBUF());
+ printf("%4i Target : %s\n", i, buf);
+ decode_address(buf, bfin_read_TBUF());
+ printf(" Source : %s\n", buf);
+ }
+ }
+
+ trace_buffer_restore(tflags);
+}
+
+void bfin_panic(struct pt_regs *regs)
+{
+ if (ENABLE_DUMP) {
+ unsigned long tflags;
+ trace_buffer_save(tflags);
+ }
+
+ puts(
+ "\n"
+ "\n"
+ "\n"
+ "Ack! Something bad happened to the Blackfin!\n"
+ "\n"
+ );
+ dump(regs);
+ dump_bfin_trace_buffer();
+ printf(
+ "\n"
+ "Please reset the board\n"
+ "\n"
+ );
+ bfin_reset_or_hang();
+}
--- /dev/null
+/*
+ * watchdog.c - driver for Blackfin on-chip watchdog
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ bfin_write_WDOG_STAT(0);
+}
+
+void hw_watchdog_init(void)
+{
+ bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */
+ hw_watchdog_reset();
+ bfin_write_WDOG_CTL(0x0);
+}
+#endif
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#endif /* #ifdef CONFIG_M5272 */
+#ifdef CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+ udelay(1000);
+
+ rcm->rcr = RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
+ return 0;
+};
+
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->wsr = 0x5555;
+ wdt->wsr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+ wdt->wcr = 0; /* disable watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wcr = 0; /* disable watchdog */
+
+ /* set timeout and enable watchdog */
+ wdt->wmr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+
+ puts("WATCHDOG:enabled\n");
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+
+#endif /* #ifdef CONFIG_M5275 */
+
#ifdef CONFIG_M5282
int checkcpu(void)
{
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
}
#endif /* #if defined(CONFIG_M5272) */
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ /* if we come from RAM we assume the CPU is
+ * already initialized.
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+
+ /* Kill watchdog so we can initialize the PLL */
+ wdog_reg->wcr = 0;
+
+ /* Memory Controller: */
+ /* Flash */
+ csctrl_reg->ar0 = CFG_AR0_PRELIM;
+ csctrl_reg->cr0 = CFG_CR0_PRELIM;
+ csctrl_reg->mr0 = CFG_MR0_PRELIM;
+
+#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
+ csctrl_reg->ar1 = CFG_AR1_PRELIM;
+ csctrl_reg->cr1 = CFG_CR1_PRELIM;
+ csctrl_reg->mr1 = CFG_MR1_PRELIM;
+#endif
+
+#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
+ csctrl_reg->ar2 = CFG_AR2_PRELIM;
+ csctrl_reg->cr2 = CFG_CR2_PRELIM;
+ csctrl_reg->mr2 = CFG_MR2_PRELIM;
+#endif
+
+#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
+ csctrl_reg->ar3 = CFG_AR3_PRELIM;
+ csctrl_reg->cr3 = CFG_CR3_PRELIM;
+ csctrl_reg->mr3 = CFG_MR3_PRELIM;
+#endif
+
+#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
+ csctrl_reg->ar4 = CFG_AR4_PRELIM;
+ csctrl_reg->cr4 = CFG_CR4_PRELIM;
+ csctrl_reg->mr4 = CFG_MR4_PRELIM;
+#endif
+
+#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
+ csctrl_reg->ar5 = CFG_AR5_PRELIM;
+ csctrl_reg->cr5 = CFG_CR5_PRELIM;
+ csctrl_reg->mr5 = CFG_MR5_PRELIM;
+#endif
+
+#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
+ csctrl_reg->ar6 = CFG_AR6_PRELIM;
+ csctrl_reg->cr6 = CFG_CR6_PRELIM;
+ csctrl_reg->mr6 = CFG_MR6_PRELIM;
+#endif
+
+#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
+ csctrl_reg->ar7 = CFG_AR7_PRELIM;
+ csctrl_reg->cr7 = CFG_CR7_PRELIM;
+ csctrl_reg->mr7 = CFG_MR7_PRELIM;
+#endif
+
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+ gpio_reg->par_feci2c = 0x000F;
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart |= UART0_ENABLE_MASK;
+ break;
+ case 1:
+ gpio->par_uart |= UART1_ENABLE_MASK;
+ break;
+ case 2:
+ gpio->par_uart |= UART2_ENABLE_MASK;
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5275) */
+
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
-#endif /* CONFIG_M5282 | CONFIG_M5271 */
+#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
+#if defined(CONFIG_M5275)
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+ /* Setup PLL */
+ pll->syncr = 0x01080000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+ pll->syncr = 0x01000000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+#endif
+
gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_R5200)
-.long 0x400
-#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
nop
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
movec %d0, %VBR
#endif
-#ifdef CONFIG_R5200
- move.l #(_flash_setup-CFG_FLASH_BASE), %a0
- move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
-_copy_flash:
- move.l (%a0)+, (%a2)+
- cmp.l %a0, %a1
- bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
-_after_flash_copy:
+#ifdef CONFIG_M5275
+ /* Initialize IPSBAR */
+ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l %d0, 0x40000000
+/* movec %d0, %MBAR */
+
+ /* Initialize RAMBAR: locate SRAM and validate it */
+ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ movec %d0, %RAMBAR1
#endif
#if 0
/*------------------------------------------------------------------------------*/
-#ifdef CONFIG_R5200
-_flash_setup:
- /* CSAR0 */
- move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
- move.w %d0, 0x40000080
-
- /* CSCR0 */
- move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
- move.w %d0, 0x4000008A
-
- /* CSMR0 */
- move.l #0x001f0001, %d0 /* 2 MB, valid */
- move.l %d0, 0x40000084
-
- jmp _after_flash_copy.L
-_flash_setup_end:
-#endif
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
rts
#endif
+#if defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01400000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0x0000c000, %d0 /* Setup SDRAM caching */
+ movec %d0, %ACR0 /* Enable cache */
+ move.l #0x00000000, %d0 /* No other caching */
+ movec %d0, %ACR1 /* Enable cache */
+ move.l #0x80400100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ moveq #1, %d0
+ move.l %d0, icache_state
+ rts
+#endif
+
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--- /dev/null
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+void dspi_init(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
+ GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+
+ dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+ DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+ DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+ DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+ dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA |
+ DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) |
+ DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) |
+ DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) |
+ DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1);
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+ dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x000000F0) == 0) ;
+
+ return (dspi->drfr & 0xFFFF);
+}
+
+#endif /* CONFIG_HARD_SPI */
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
u32 pvr = get_pvr();
u32 spridr;
char buf[32];
+ int i;
+
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+ const struct cpu_type {
+ char name[15];
+ u32 partid;
+ } cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8311),
+ CPU_TYPE_ENTRY(8313),
+ CPU_TYPE_ENTRY(8314),
+ CPU_TYPE_ENTRY(8315),
+ CPU_TYPE_ENTRY(8321),
+ CPU_TYPE_ENTRY(8323),
+ CPU_TYPE_ENTRY(8343),
+ CPU_TYPE_ENTRY(8347_TBGA_),
+ CPU_TYPE_ENTRY(8347_PBGA_),
+ CPU_TYPE_ENTRY(8349),
+ CPU_TYPE_ENTRY(8358_TBGA_),
+ CPU_TYPE_ENTRY(8358_PBGA_),
+ CPU_TYPE_ENTRY(8360),
+ CPU_TYPE_ENTRY(8377),
+ CPU_TYPE_ENTRY(8378),
+ CPU_TYPE_ENTRY(8379),
+ };
immr = (immap_t *)CFG_IMMR;
}
spridr = immr->sysconf.spridr;
- switch(spridr) {
- case SPR_8349E_REV10:
- case SPR_8349E_REV11:
- case SPR_8349E_REV31:
- puts("MPC8349E, ");
- break;
- case SPR_8349_REV10:
- case SPR_8349_REV11:
- case SPR_8349_REV31:
- puts("MPC8349, ");
- break;
- case SPR_8347E_REV10_TBGA:
- case SPR_8347E_REV11_TBGA:
- case SPR_8347E_REV31_TBGA:
- case SPR_8347E_REV10_PBGA:
- case SPR_8347E_REV11_PBGA:
- case SPR_8347E_REV31_PBGA:
- puts("MPC8347E, ");
- break;
- case SPR_8347_REV10_TBGA:
- case SPR_8347_REV11_TBGA:
- case SPR_8347_REV31_TBGA:
- case SPR_8347_REV10_PBGA:
- case SPR_8347_REV11_PBGA:
- case SPR_8347_REV31_PBGA:
- puts("MPC8347, ");
- break;
- case SPR_8343E_REV10:
- case SPR_8343E_REV11:
- case SPR_8343E_REV31:
- puts("MPC8343E, ");
- break;
- case SPR_8343_REV10:
- case SPR_8343_REV11:
- case SPR_8343_REV31:
- puts("MPC8343, ");
- break;
- case SPR_8360E_REV10:
- case SPR_8360E_REV11:
- case SPR_8360E_REV12:
- case SPR_8360E_REV20:
- case SPR_8360E_REV21:
- puts("MPC8360E, ");
- break;
- case SPR_8360_REV10:
- case SPR_8360_REV11:
- case SPR_8360_REV12:
- case SPR_8360_REV20:
- case SPR_8360_REV21:
- puts("MPC8360, ");
- break;
- case SPR_8323E_REV10:
- case SPR_8323E_REV11:
- puts("MPC8323E, ");
- break;
- case SPR_8323_REV10:
- case SPR_8323_REV11:
- puts("MPC8323, ");
- break;
- case SPR_8321E_REV10:
- case SPR_8321E_REV11:
- puts("MPC8321E, ");
- break;
- case SPR_8321_REV10:
- case SPR_8321_REV11:
- puts("MPC8321, ");
- break;
- case SPR_8311_REV10:
- puts("MPC8311, ");
- break;
- case SPR_8311E_REV10:
- puts("MPC8311E, ");
- break;
- case SPR_8313_REV10:
- puts("MPC8313, ");
- break;
- case SPR_8313E_REV10:
- puts("MPC8313E, ");
- break;
- case SPR_8315E_REV10:
- puts("MPC8315E, ");
- break;
- case SPR_8315_REV10:
- puts("MPC8315, ");
- break;
- case SPR_8314E_REV10:
- puts("MPC8314E, ");
- break;
- case SPR_8314_REV10:
- puts("MPC8314, ");
- break;
- case SPR_8379E_REV10:
- puts("MPC8379E, ");
- break;
- case SPR_8379_REV10:
- puts("MPC8379, ");
- break;
- case SPR_8378E_REV10:
- puts("MPC8378E, ");
- break;
- case SPR_8378_REV10:
- puts("MPC8378, ");
- break;
- case SPR_8377E_REV10:
- puts("MPC8377E, ");
- break;
- case SPR_8377_REV10:
- puts("MPC8377, ");
- break;
- default:
- printf("Rev: Unknown revision number:%08x\n"
- "Warning: Unsupported cpu revision!\n",spridr);
- return 0;
- }
-#if defined(CONFIG_MPC834X)
- /* Multiple revisons of 834x processors may have the same SPRIDR value.
- * So use PVR to identify the revision number.
- */
- printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
-#else
- printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
-#endif
- printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+ if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
+ puts("MPC");
+ puts(cpu_type_list[i].name);
+ if (IS_E_PROCESSOR(spridr))
+ puts("E");
+ if (REVID_MAJOR(spridr) >= 2)
+ puts("A");
+ printf(", Rev: %d.%d", REVID_MAJOR(spridr),
+ REVID_MINOR(spridr));
+ break;
+ }
+
+ if (i == ARRAY_SIZE(cpu_type_list))
+ printf("(SPRIDR %08x unknown), ", spridr);
+
+ printf(" at %s MHz, ", strmhz(buf, clock));
+
+ printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
return 0;
}
#include <asm/mmu.h>
#include <spd_sdram.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void board_add_ram_info(int use_default)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
+ char buf[32];
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
puts(", 64-bit");
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
- puts(", ECC on)");
+ puts(", ECC on");
else
- puts(", ECC off)");
+ puts(", ECC off");
+
+ printf(", %s MHz)", strmhz(buf, gd->mem_clk));
#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
#ifdef CONFIG_SPD_EEPROM
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void dma_init(void);
extern uint dma_check(void);
int
picos_to_clk(int picos)
{
- unsigned int ddr_bus_clk;
+ unsigned int mem_bus_clk;
int clks;
- ddr_bus_clk = gd->ddr_clk >> 1;
- clks = picos / (1000000000 / (ddr_bus_clk / 1000));
- if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
+ mem_bus_clk = gd->mem_clk >> 1;
+ clks = picos / (1000000000 / (mem_bus_clk / 1000));
+ if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
clks++;
return clks;
debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
- ddrc_clk = gd->ddr_clk / 1000000;
+ ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 ddr_clk;
+ u32 mem_clk;
#if defined(CONFIG_MPC8360)
- u32 ddr_sec_clk;
+ u32 mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
u32 qepmf;
return -12;
}
- ddr_clk = csb_clk *
+ mem_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
#if defined(CONFIG_MPC8360)
- ddr_sec_clk = csb_clk * (1 +
+ mem_sec_clk = csb_clk * (1 +
((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
#endif
gd->enc_clk = enc_clk;
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
- gd->ddr_clk = ddr_clk;
+ gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
- gd->ddr_sec_clk = ddr_sec_clk;
+ gd->mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
gd->qe_clk = qe_clk;
#endif
printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
- printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
+ printf(" DDR: %4d MHz\n", gd->mem_clk / 1000000);
#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
+ printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
#endif
printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
- lis r4, (CFG_MONITOR_BASE)@h
- ori r4, r4, (CFG_MONITOR_BASE)@l
+
+ GET_GOT /* initialize GOT access */
+ lwz r4, GOT(_start)
+ addi r4, r4, -EXC_OFF_SYS_RESET
+
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r4, GOT(_start)
+ addi r4, r4, -EXC_OFF_SYS_RESET
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
- uint32_t failsafe = 10000;
+ u32 val = 10000;
out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* wait for reset */
while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
+ val--;
+ if (val == 0)
break;
}
hw_p->print_speed = 1; /* print speed message again next time */
#endif
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+ mfsdr(SDR0_ETH_CFG, val);
+ val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+ mtsdr(SDR0_ETH_CFG, val);
+#endif
+
return;
}
u32 zmiifer; /* ZMII0_FER reg. */
u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
+ int mode;
zmiifer = 0;
rmiifer = 0;
rmiifer1 = 0;
+#if defined(CONFIG_460EX)
+ mode = 9;
+#else
+ mode = 10;
+#endif
+
/* TODO:
* NOTE: 460GT has 2 RGMII bridge cores:
* emac0 ------ RGMII0_BASE
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2008-02-19
*/
- switch (9) {
+ switch (mode) {
case 1:
/* 1 MII - 460EX */
/* GMC0 EMAC4_0, ZMII Bridge */
#ifdef CONFIG_4xx_DCACHE
static u32 last_used_ea = 0;
#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_405EX)
+ int rgmii_channel;
+#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
reg = CONFIG_PHY1_ADDR;
break;
#endif
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_PHY2_ADDR)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
case 3:
reg = CONFIG_PHY3_ADDR;
break;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
+ if (devnum >= 2)
+ rgmii_channel = devnum - 2;
+ else
+ rgmii_channel = devnum;
+
if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
else {
printf("Error in RGMII Speed\n");
return -1;
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- mtdcr (malrxctp8r, hw_p->rx);
+ mtdcr (malrxctp8r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
#else
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+ case 2:
+ /* setup MAL tx & rx channel pointers */
+ mtdcr (maltxbattr, 0x0);
+ mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp2r, hw_p->tx_phys);
+ mtdcr (malrxctp16r, hw_p->rx_phys);
+ /* set RX buffer size */
+ mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+ break;
+ case 3:
+ /* setup MAL tx & rx channel pointers */
+ mtdcr (maltxbattr, 0x0);
+ mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp3r, hw_p->tx_phys);
+ mtdcr (malrxctp24r, hw_p->rx_phys);
+ /* set RX buffer size */
+ mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+ break;
+#endif /* CONFIG_460GT */
case 0:
default:
/* setup MAL tx & rx channel pointers */
case 2:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+ hw_addr[eth_num] = 0x300;
+#else
hw_addr[eth_num] = 0x400;
+#endif
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+ hw_addr[eth_num] = 0x400;
+#else
hw_addr[eth_num] = 0x600;
+#endif
break;
#endif
}
# endif
#endif /* CFG_INIT_DCACHE_CS */
+#ifndef CFG_PLL_RECONFIG
+#define CFG_PLL_RECONFIG 0
+#endif
+
+void reconfigure_pll(u32 new_cpu_freq)
+{
+#if defined(CONFIG_440EPX)
+ int reset_needed = 0;
+ u32 reg, temp;
+ u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
+ fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
+ fbdv, target_fbdv, lfbdv, target_lfbdv,
+ perdv0, target_perdv0, /* CLK_PERD */
+ spcid0, target_spcid0; /* CLK_SPCID */
+
+ /* Reconfigure clocks if necessary.
+ * See PPC440EPx User's Manual, sections 8.2 and 14 */
+ if (new_cpu_freq == 667) {
+ target_prbdv0 = 2;
+ target_fwdva = 2;
+ target_fwdvb = 4;
+ target_fbdv = 20;
+ target_lfbdv = 1;
+ target_perdv0 = 4;
+ target_spcid0 = 4;
+
+ mfcpr(clk_primbd, reg);
+ temp = (reg & PRBDV_MASK) >> 24;
+ prbdv0 = temp ? temp : 8;
+ if (prbdv0 != target_prbdv0) {
+ reg &= ~PRBDV_MASK;
+ reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
+ mtcpr(clk_primbd, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_plld, reg);
+
+ temp = (reg & PLLD_FWDVA_MASK) >> 16;
+ fwdva = temp ? temp : 16;
+
+ temp = (reg & PLLD_FWDVB_MASK) >> 8;
+ fwdvb = temp ? temp : 8;
+
+ temp = (reg & PLLD_FBDV_MASK) >> 24;
+ fbdv = temp ? temp : 32;
+
+ temp = (reg & PLLD_LFBDV_MASK);
+ lfbdv = temp ? temp : 64;
+
+ if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
+ reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
+ PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
+ reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
+ ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
+ ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
+ (target_lfbdv == 64 ? 0 : target_lfbdv);
+ mtcpr(clk_plld, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_perd, reg);
+ perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
+ if (perdv0 != target_perdv0) {
+ reg &= ~CPR0_PERD_PERDV0_MASK;
+ reg |= (target_perdv0 << 24);
+ mtcpr(clk_perd, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_spcid, reg);
+ temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
+ spcid0 = temp ? temp : 4;
+ if (spcid0 != target_spcid0) {
+ reg &= ~CPR0_SPCID_SPCIDV0_MASK;
+ reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
+ mtcpr(clk_spcid, reg);
+ reset_needed = 1;
+ }
+
+ /* Set reload inhibit so configuration will persist across
+ * processor resets */
+ mfcpr(clk_icfg, reg);
+ reg &= ~CPR0_ICFG_RLI_MASK;
+ reg |= 1 << 31;
+ mtcpr(clk_icfg, reg);
+ }
+
+ /* Reset processor if configuration changed */
+ if (reset_needed) {
+ __asm__ __volatile__ ("sync; isync");
+ mtspr(dbcr0, 0x20000000);
+ }
+#endif
+}
+
/*
* Breath some life into the CPU...
*
- * Set up the memory map,
+ * Reconfigure PLL if necessary,
+ * set up the memory map,
* initialize a bunch of registers
*/
void
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#endif
+ reconfigure_pll(CFG_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
/*
#if defined (CFG_GPIO0_TCR)
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
#endif
+#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
#if defined (CONFIG_405EP)
/*
*/
mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */
-#endif /* CONFIG_405EP */
#if defined(CFG_4xx_GPIO_TABLE)
gpio_set_chip_configuration();
program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
- /*------------------------------------------------------------------
+ /*
* TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
- * board SDRAM, but may be overly concervate.
- *-----------------------------------------------------------------*/
+ * board SDRAM, but may be overly conservative.
+ */
mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
DDR0_07_TFAW_ENCODE(13) |
DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
denali_wait_for_dlllock();
#if defined(CONFIG_DDR_DATA_EYE)
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE);
+ /*
+ * Map the first 1 MiB of memory in the TLB, and perform the data eye
+ * search.
+ */
+ program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
denali_sdram_register_dump();
- remove_tlb(CFG_SDRAM_BASE, dram_size);
+ remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
sync();
- eieio();
/* Zero the memory */
debug("Zeroing SDRAM...");
- dcbz_area(CFG_SDRAM_BASE, dram_size);
+#if defined(CFG_MEM_TOP_HIDE)
+ dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#else
+#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#endif
dflush();
debug("Completed\n");
sync();
- eieio();
remove_tlb(CFG_SDRAM_BASE, dram_size);
#if defined(CONFIG_DDR_ECC)
u32 val;
sync();
- eieio();
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
print_mcsr();
#endif
sync();
- eieio();
}
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
} else {
set_dcr(uic_base + UIC_ER,
get_dcr(uic_base + UIC_ER) &
- ~(0x80000000 >> vec));
+ ~(0x80000000 >> (vec & 0x1f)));
printf("Masking bogus interrupt vector %d"
" (UIC_BASE=0x%x)\n", vec, uic_base);
}
/*
- * After servicing the interrupt, we have to remove the status indicator.
+ * After servicing the interrupt, we have to remove the
+ * status indicator
*/
- set_dcr(uic_base + UIC_SR, (0x80000000 >> vec));
+ set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f)));
}
/*
#include <common.h>
#include <command.h>
#include <asm/processor.h>
+#include <asm/cache.h>
int checkcpu(void)
{
void flush_cache (unsigned long addr, unsigned long size)
{
-
+ dcache_invalid_range( addr , addr + size );
}
void icache_enable (void)
--- /dev/null
+The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
+chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
+addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
+from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
+Bank #1 (with the starting address depending on the flash size detected at
+runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
+cannot be modified in the field. This also prevents FLASH0 from executing
+commands to return chip information, so its configuration is hard-coded in
+U-Boot.
+
+There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
+permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
+0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
+located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
+for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
+used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
+0xF7FDFFFF are used for the redundant copy of the parameters. These locations
+are used by both versions of U-Boot.
+
+On booting, the permanent U-Boot in FLASH0 begins executing. After performing
+minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
+the switch is sensed as open before a timeout period, then U-Boot branches to
+address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
+beginning. If the switch remains closed thoughout the timeout period, the
+permanent U-Boot activates the on-board buzzer until the switch is sensed as
+opened. It then continues to execute without branching to FLASH1. The effect
+of this is that normally the Korat board boots its upgradable U-Boot, but, if
+this has been corrupted, the user can boot the permanent U-Boot, which can then
+be used to erase and reload FLASH1 as needed.
+
+Note that it is not necessary for the permanent U-Boot to have all the latest
+features, but only that it have sufficient functionality (working "tftp",
+"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
+assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
+sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
+
+The build sequence:
+
+ make korat_config
+ make all perm=1
+
+builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
+preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
+
+ make korat_config
+ make all
+
+creates the upgradable U-Boot but selecting loader file "u-boot-F7FC.lds" and
+leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
+
+2008-02-22, Larry Johnson <lrj@acm.org>
U-Boot for Renesas SuperH
- Last update 08/10/2007 by Nobuhiro Iwamatsu
+ Last update 01/18/2008 by Nobuhiro Iwamatsu
================================================================================
0. What's this?
2. Supported CPUs
2.1. Renesas SH7750/SH7750R
+ This CPU has the SH4 core.
+
2.2. Renesas SH7722
+ This CPU has the SH4AL-DSP core.
+
+ 2.3. Renesas SH7720
+ This CPU has the SH3 core.
+
+ 2.4. Renesas SH7710/SH7712
+ This CPU has the SH3-DSP core and Ethernet controller.
+
+ 2.5. Renesas SH7780
+ This CPU has the SH4A core.
================================================================================
3. Supported Boards
3.1. Hitachi UL MS7750SE01/MS7750RSE01
Board specific code is in board/ms7750se
To use this board, type "make ms7750se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
3.2. Hitachi UL MS7722SE01
Board specific code is in board/ms7722se
To use this board, type "make ms7722se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+ - SMC91x ethernet
+
+ 3.2. Hitachi UL MS7720ERP01
+ Board specific code is in board/ms7720se
+ To use this board, type "make ms7720se_config".
+ Support devices are :
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+
+ 3.3. Renesas R7780MP
+ Board specific code is in board/r7780mp
+ To use this board, type "make r7780mp_config".
+ Support devices are :
+ - SCIF
+ - DDR-SDRAM
+ - NOR Flash
+ - Compact Flash
+ - ASIX ethernet
+ - SH7780 PCI bridge
+ - RTL8110 ethernet
** README **
In SuperH, S-record and binary of made u-boot work on the memory.
5. Future
I plan to support the following CPUs and boards.
5.1. CPUs
- - SH7710/SH7712 (SH3)
- - SH7780(SH4)
+ - SH7751R(SH4)
- SH7785(SH4)
5.2. Boards
- Many boards ;-)
================================================================================
-Copyright (c) 2007
+Copyright (c) 2007,2008
Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
COBJS-y += omap1510_i2c.o
COBJS-y += omap24xx_i2c.o
COBJS-y += tsi108_i2c.o
+COBJS-y += mxc_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * i2c driver for Freescale mx31
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_HARD_I2C) && defined(CONFIG_I2C_MXC)
+
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+#define IADR 0x00
+#define IFDR 0x04
+#define I2CR 0x08
+#define I2SR 0x0c
+#define I2DR 0x10
+
+#define I2CR_IEN (1 << 7)
+#define I2CR_IIEN (1 << 6)
+#define I2CR_MSTA (1 << 5)
+#define I2CR_MTX (1 << 4)
+#define I2CR_TX_NO_AK (1 << 3)
+#define I2CR_RSTA (1 << 2)
+
+#define I2SR_ICF (1 << 7)
+#define I2SR_IBB (1 << 5)
+#define I2SR_IIF (1 << 1)
+#define I2SR_RX_NO_AK (1 << 0)
+
+#ifdef CFG_I2C_MX31_PORT1
+#define I2C_BASE 0x43f80000
+#elif defined(CFG_I2C_MX31_PORT2)
+#define I2C_BASE 0x43f98000
+#elif defined(CFG_I2C_MX31_PORT3)
+#define I2C_BASE 0x43f84000
+#else
+#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver"
+#endif
+
+#ifdef DEBUG
+#define DPRINTF(args...) printf(args)
+#else
+#define DPRINTF(args...)
+#endif
+
+static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
+ 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
+ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
+
+void i2c_init(int speed, int unused)
+{
+ int freq = mx31_get_ipg_clk();
+ int i;
+
+ for (i = 0; i < 0x1f; i++)
+ if (freq / div[i] <= speed)
+ break;
+
+ DPRINTF("%s: speed: %d\n", __FUNCTION__, speed);
+
+ __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
+ __REG16(I2C_BASE + IFDR) = i;
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ __REG16(I2C_BASE + I2SR) = 0;
+}
+
+static int wait_busy(void)
+{
+ int timeout = 10000;
+
+ while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
+ udelay(1);
+ __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+
+ return timeout;
+}
+
+static int tx_byte(u8 byte)
+{
+ __REG16(I2C_BASE + I2DR) = byte;
+
+ if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
+ return -1;
+ return 0;
+}
+
+static int rx_byte(void)
+{
+ if (!wait_busy())
+ return -1;
+
+ return __REG16(I2C_BASE + I2DR);
+}
+
+int i2c_probe(uchar chip)
+{
+ int ret;
+
+ __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+ ret = tx_byte(chip << 1);
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
+
+ return ret;
+}
+
+static int i2c_addr(uchar chip, uint addr, int alen)
+{
+ __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+
+ if (tx_byte(chip << 1))
+ return -1;
+
+ while (alen--)
+ if (tx_byte((addr >> (alen * 8)) & 0xff))
+ return -1;
+ return 0;
+}
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int timeout = 10000;
+ int ret;
+
+ DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: +%d\n", \
+ __FUNCTION__, chip, addr, alen, len);
+
+ if (i2c_addr(chip, addr, alen)) {
+ printf("i2c_addr failed\n");
+ return -1;
+ }
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | \
+ I2CR_MTX | I2CR_RSTA;
+
+ if (tx_byte(chip << 1 | 1))
+ return -1;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) \
+ ? I2CR_TX_NO_AK : 0);
+
+ ret = __REG16(I2C_BASE + I2DR);
+
+ while (len--) {
+ if ((ret = rx_byte()) < 0)
+ return -1;
+ *buf++ = ret;
+ if (len <= 1)
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | \
+ I2CR_MSTA | I2CR_TX_NO_AK;
+ }
+
+ wait_busy();
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ udelay(1);
+
+ return 0;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int timeout = 10000;
+ DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", \
+ __FUNCTION__, chip, addr, alen, len);
+
+ if (i2c_addr(chip, addr, alen))
+ return -1;
+
+ while (len--)
+ if (tx_byte(*buf++))
+ return -1;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ udelay(1);
+
+ return 0;
+}
+
+#endif /* CONFIG_HARD_I2C */
return __raw_readl(addr);
}
-static u64 flash_read64(void *addr)
+static u64 __flash_read64(void *addr)
{
/* No architectures currently implement __raw_readq() */
return *(volatile u64 *)addr;
}
+u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
+
/*-----------------------------------------------------------------------
*/
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
}
/*-----------------------------------------------------------------------
+ * read a word at a port width address, assume 16bit bus
+ */
+static inline ushort flash_read_word (flash_info_t * info, uint offset)
+{
+ ushort *addr, retval;
+
+ addr = flash_map (info, 0, offset);
+ retval = flash_read16 (addr);
+ flash_unmap (info, 0, offset, addr);
+ return retval;
+}
+
+
+/*-----------------------------------------------------------------------
* read a long word by picking the least significant byte of each maximum
* port size word. Swap for ppc format.
*/
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
udelay(1000); /* some flash are slow to respond */
+
info->manufacturer_id = flash_read_uchar (info,
FLASH_OFFSET_MANUFACTURER_ID);
- info->device_id = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID);
- if (info->device_id == 0x7E) {
- /* AMD 3-byte (expanded) device ids */
- info->device_id2 = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID2);
- info->device_id2 <<= 8;
- info->device_id2 |= flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID3);
+
+ switch (info->chipwidth){
+ case FLASH_CFI_8BIT:
+ info->device_id = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID);
+ if (info->device_id == 0x7E) {
+ /* AMD 3-byte (expanded) device ids */
+ info->device_id2 = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID2);
+ info->device_id2 <<= 8;
+ info->device_id2 |= flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID3);
+ }
+ break;
+ case FLASH_CFI_16BIT:
+ info->device_id = flash_read_word (info,
+ FLASH_OFFSET_DEVICE_ID);
+ break;
+ default:
+ break;
}
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
}
}
},
#endif
+#ifdef CFG_FLASH_LEGACY_512Kx16
+ {
+ .mfr_id = MANUFACTURER_AMD,
+ .dev_id = AM29LV400BB,
+ .name = "AMD AM29LV400BB",
+ .uaddr = {
+ [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+ },
+ .DevSize = SIZE_512KiB,
+ .CmdSet = CFI_CMDSET_AMD_LEGACY,
+ .NumEraseRegions= 4,
+ .regions = {
+ ERASEINFO(0x04000,1),
+ ERASEINFO(0x02000,2),
+ ERASEINFO(0x08000,1),
+ ERASEINFO(0x10000,7),
+ }
+ },
+#endif
};
static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
COBJS-y += eepro100.o
COBJS-y += enc28j60.o
COBJS-y += fsl_mcdmafec.o
+COBJS-$(CONFIG_GRETH) += greth.o
COBJS-y += inca-ip_sw.o
COBJS-y += ks8695eth.o
COBJS-y += lan91c96.o
COBJS-y += rtl8169.o
COBJS-y += s3c4510b_eth.o
COBJS-y += smc91111.o
+COBJS-y += smc911x.o
COBJS-y += tigon3.o
COBJS-y += tsec.o
COBJS-y += tsi108_eth.o
/**************************************************************************
-Inter Pro 1000 for ppcboot/das-u-boot
+Intel Pro 1000 for ppcboot/das-u-boot
Drivers are port from Intel's Linux driver e1000-4.3.15
and from Etherboot pro 1000 driver by mrakes at vivato dot net
tested on both gig copper and gig fiber boards
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
};
/* Function forward declarations */
/* Invert the last bit if this is the second device */
nic->enetaddr[5] += 1;
}
+#ifdef CONFIG_E1000_FALLBACK_MAC
+ if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
+ for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
+ nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff;
+#endif
#else
/*
* The AP1000's e1000 has no eeprom; the MAC address is stored in the
case E1000_DEV_ID_82546EB_FIBER:
hw->mac_type = e1000_82546;
break;
+ case E1000_DEV_ID_82541ER:
+ hw->mac_type = e1000_82541_rev_2;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
return 0;
}
+static int
+e1000_set_phy_type(struct e1000_hw *hw)
+{
+ DEBUGFUNC();
+
+ if(hw->mac_type == e1000_undefined)
+ return -E1000_ERR_PHY_TYPE;
+
+ switch(hw->phy_id) {
+ case M88E1000_E_PHY_ID:
+ case M88E1000_I_PHY_ID:
+ case M88E1011_I_PHY_ID:
+ hw->phy_type = e1000_phy_m88;
+ break;
+ case IGP01E1000_I_PHY_ID:
+ if(hw->mac_type == e1000_82541 ||
+ hw->mac_type == e1000_82541_rev_2) {
+ hw->phy_type = e1000_phy_igp;
+ break;
+ }
+ /* Fall Through */
+ default:
+ /* Should never have loaded on this device */
+ hw->phy_type = e1000_phy_undefined;
+ return -E1000_ERR_PHY_TYPE;
+ }
+
+ return E1000_SUCCESS;
+}
+
/******************************************************************************
* Probes the expected PHY address for known PHY IDs
*
static int
e1000_detect_gig_phy(struct e1000_hw *hw)
{
+ int32_t phy_init_status;
uint16_t phy_id_high, phy_id_low;
int match = FALSE;
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82541_rev_2:
+ if(hw->phy_id == IGP01E1000_I_PHY_ID)
+ match = TRUE;
+
+ break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
}
- if (match) {
+
+ phy_init_status = e1000_set_phy_type(hw);
+
+ if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
return 0;
}
free(nic);
return 0;
}
-#ifndef CONFIG_AP1000
+#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
if (e1000_validate_eeprom_checksum(nic) < 0) {
printf("The EEPROM Checksum Is Not Valid\n");
free(hw);
e1000_82540,
e1000_82545,
e1000_82546,
+ e1000_82541,
+ e1000_82541_rev_2,
e1000_num_macs
} e1000_mac_type;
e1000_1000t_rx_status_undefined = 0xFF
} e1000_1000t_rx_status;
+typedef enum {
+ e1000_phy_m88 = 0,
+ e1000_phy_igp,
+ e1000_phy_igp_2,
+ e1000_phy_undefined = 0xFF
+} e1000_phy_type;
+
struct e1000_phy_info {
e1000_cable_length cable_length;
e1000_10bt_ext_dist_enable extended_10bt_distance;
};
/* Error Codes */
-#define E1000_SUCCESS 0
-#define E1000_ERR_EEPROM 1
-#define E1000_ERR_PHY 2
-#define E1000_ERR_CONFIG 3
-#define E1000_ERR_PARAM 4
-#define E1000_ERR_MAC_TYPE 5
-#define E1000_ERR_NOLINK 6
-#define E1000_ERR_TIMEOUT 7
+#define E1000_SUCCESS 0
+#define E1000_ERR_EEPROM 1
+#define E1000_ERR_PHY 2
+#define E1000_ERR_CONFIG 3
+#define E1000_ERR_PARAM 4
+#define E1000_ERR_MAC_TYPE 5
+#define E1000_ERR_PHY_TYPE 6
+#define E1000_ERR_NOLINK 7
+#define E1000_ERR_TIMEOUT 8
+#define E1000_ERR_RESET 9
+#define E1000_ERR_MASTER_REQUESTS_PENDING 10
+#define E1000_ERR_HOST_INTERFACE_COMMAND 11
+#define E1000_BLK_PHY_RESET 12
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
#define E1000_DEV_ID_82545EM_FIBER 0x1011
#define E1000_DEV_ID_82546EB_COPPER 0x1010
#define E1000_DEV_ID_82546EB_FIBER 0x1012
-#define NUM_DEV_IDS 13
+#define E1000_DEV_ID_82541ER 0x1078
+#define NUM_DEV_IDS 14
#define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6
pci_dev_t pdev;
uint8_t *hw_addr;
e1000_mac_type mac_type;
+ e1000_phy_type phy_type;
+ uint32_t phy_init_script;
e1000_media_type media_type;
e1000_lan_loc lan_loc;
e1000_fc_type fc;
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
-#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
+
+/* IGP01E1000 specifics */
+#define IGP01E1000_IEEE_REGS_PAGE 0x0000
+#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
+#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
+
+/* IGP01E1000 Specific Registers */
+#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
+#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
+#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
+#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
+#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
+#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
+#define IGP02E1000_PHY_POWER_MGMT 0x19
+#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define M88E1011_I_PHY_ID 0x01410C20
#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
+#define IGP01E1000_I_PHY_ID 0x02A80380
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
--- /dev/null
+/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
+ *
+ * Driver use polling mode (no Interrupt)
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <ambapp.h>
+#include <asm/leon.h>
+
+/* #define DEBUG */
+
+#include "greth.h"
+
+/* Default to 3s timeout on autonegotiation */
+#ifndef GRETH_PHY_TIMEOUT_MS
+#define GRETH_PHY_TIMEOUT_MS 3000
+#endif
+
+/* ByPass Cache when reading regs */
+#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
+/* Write-through cache ==> no bypassing needed on writes */
+#define GRETH_REGSAVE(addr,data) (*(unsigned int *)(addr) = (data))
+#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
+#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
+
+#define GRETH_RXBD_CNT 4
+#define GRETH_TXBD_CNT 1
+
+#define GRETH_RXBUF_SIZE 1540
+#define GRETH_BUF_ALIGN 4
+#define GRETH_RXBUF_EFF_SIZE \
+ ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
+
+typedef struct {
+ greth_regs *regs;
+ int irq;
+ struct eth_device *dev;
+
+ /* Hardware info */
+ unsigned char phyaddr;
+ int gbit_mac;
+
+ /* Current operating Mode */
+ int gb; /* GigaBit */
+ int fd; /* Full Duplex */
+ int sp; /* 10/100Mbps speed (1=100,0=10) */
+ int auto_neg; /* Auto negotiate done */
+
+ unsigned char hwaddr[6]; /* MAC Address */
+
+ /* Descriptors */
+ greth_bd *rxbd_base, *rxbd_max;
+ greth_bd *txbd_base, *txbd_max;
+
+ greth_bd *rxbd_curr;
+
+ /* rx buffers in rx descriptors */
+ void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
+
+ /* unused for gbit_mac, temp buffer for sending packets with unligned
+ * start.
+ * Pointer to packet allocated with malloc.
+ */
+ void *txbuf;
+
+ struct {
+ /* rx status */
+ unsigned int rx_packets,
+ rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
+
+ /* tx stats */
+ unsigned int tx_packets,
+ tx_latecol_errors,
+ tx_underrun_errors, tx_limit_errors, tx_errors;
+ } stats;
+} greth_priv;
+
+/* Read MII register 'addr' from core 'regs' */
+static int read_mii(int addr, volatile greth_regs * regs)
+{
+ while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
+ }
+
+ GRETH_REGSAVE(®s->mdio, (0 << 11) | ((addr & 0x1F) << 6) | 2);
+
+ while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
+ }
+
+ if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) {
+ return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF;
+ } else {
+ return -1;
+ }
+}
+
+static void write_mii(int addr, int data, volatile greth_regs * regs)
+{
+ while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
+ }
+
+ GRETH_REGSAVE(®s->mdio,
+ ((data & 0xFFFF) << 16) | (0 << 11) | ((addr & 0x1F) << 6)
+ | 1);
+
+ while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
+ }
+
+}
+
+/* init/start hardware and allocate descriptor buffers for rx side
+ *
+ */
+int greth_init(struct eth_device *dev, bd_t * bis)
+{
+ int i;
+
+ greth_priv *greth = dev->priv;
+ greth_regs *regs = greth->regs;
+#ifdef DEBUG
+ printf("greth_init\n");
+#endif
+
+ GRETH_REGSAVE(®s->control, 0);
+
+ if (!greth->rxbd_base) {
+
+ /* allocate descriptors */
+ greth->rxbd_base = (greth_bd *)
+ memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
+ greth->txbd_base = (greth_bd *)
+ memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
+
+ /* allocate buffers to all descriptors */
+ greth->rxbuf_base =
+ malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
+ }
+
+ /* initate rx decriptors */
+ for (i = 0; i < GRETH_RXBD_CNT; i++) {
+ greth->rxbd_base[i].addr = (unsigned int)
+ greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
+ /* enable desciptor & set wrap bit if last descriptor */
+ if (i >= (GRETH_RXBD_CNT - 1)) {
+ greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
+ } else {
+ greth->rxbd_base[i].stat = GRETH_BD_EN;
+ }
+ }
+
+ /* initiate indexes */
+ greth->rxbd_curr = greth->rxbd_base;
+ greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
+ greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
+ /*
+ * greth->txbd_base->addr = 0;
+ * greth->txbd_base->stat = GRETH_BD_WR;
+ */
+
+ /* initate tx decriptors */
+ for (i = 0; i < GRETH_TXBD_CNT; i++) {
+ greth->txbd_base[i].addr = 0;
+ /* enable desciptor & set wrap bit if last descriptor */
+ if (i >= (GRETH_RXBD_CNT - 1)) {
+ greth->txbd_base[i].stat = GRETH_BD_WR;
+ } else {
+ greth->txbd_base[i].stat = 0;
+ }
+ }
+
+ /**** SET HARDWARE REGS ****/
+
+ /* Set pointer to tx/rx descriptor areas */
+ GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
+ GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
+
+ /* Enable Transmitter, GRETH will now scan descriptors for packets
+ * to transmitt */
+#ifdef DEBUG
+ printf("greth_init: enabling receiver\n");
+#endif
+ GRETH_REGORIN(®s->control, GRETH_RXEN);
+
+ return 0;
+}
+
+/* Initiate PHY to a relevant speed
+ * return:
+ * - 0 = success
+ * - 1 = timeout/fail
+ */
+int greth_init_phy(greth_priv * dev, bd_t * bis)
+{
+ greth_regs *regs = dev->regs;
+ int tmp, tmp1, tmp2, i;
+ unsigned int start, timeout;
+
+ /* X msecs to ticks */
+ timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
+
+ /* Get system timer0 current value
+ * Total timeout is 5s
+ */
+ start = get_timer(0);
+
+ /* get phy control register default values */
+
+ while ((tmp = read_mii(0, regs)) & 0x8000) {
+ if (get_timer(start) > timeout)
+ return 1; /* Fail */
+ }
+
+ /* reset PHY and wait for completion */
+ write_mii(0, 0x8000 | tmp, regs);
+
+ while (((tmp = read_mii(0, regs))) & 0x8000) {
+ if (get_timer(start) > timeout)
+ return 1; /* Fail */
+ }
+
+ /* Check if PHY is autoneg capable and then determine operating
+ * mode, otherwise force it to 10 Mbit halfduplex
+ */
+ dev->gb = 0;
+ dev->fd = 0;
+ dev->sp = 0;
+ dev->auto_neg = 0;
+ if (!((tmp >> 12) & 1)) {
+ write_mii(0, 0, regs);
+ } else {
+ /* wait for auto negotiation to complete and then check operating mode */
+ dev->auto_neg = 1;
+ i = 0;
+ while (!(((tmp = read_mii(1, regs)) >> 5) & 1)) {
+ if (get_timer(start) > timeout) {
+ printf("Auto negotiation timed out. "
+ "Selecting default config\n");
+ tmp = read_mii(0, regs);
+ dev->gb = ((tmp >> 6) & 1)
+ && !((tmp >> 13) & 1);
+ dev->sp = !((tmp >> 6) & 1)
+ && ((tmp >> 13) & 1);
+ dev->fd = (tmp >> 8) & 1;
+ goto auto_neg_done;
+ }
+ }
+ if ((tmp >> 8) & 1) {
+ tmp1 = read_mii(9, regs);
+ tmp2 = read_mii(10, regs);
+ if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
+ (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
+ dev->gb = 1;
+ dev->fd = 1;
+ }
+ if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
+ (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
+ dev->gb = 1;
+ dev->fd = 0;
+ }
+ }
+ if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
+ tmp1 = read_mii(4, regs);
+ tmp2 = read_mii(5, regs);
+ if ((tmp1 & GRETH_MII_100TXFD) &&
+ (tmp2 & GRETH_MII_100TXFD)) {
+ dev->sp = 1;
+ dev->fd = 1;
+ }
+ if ((tmp1 & GRETH_MII_100TXHD) &&
+ (tmp2 & GRETH_MII_100TXHD)) {
+ dev->sp = 1;
+ dev->fd = 0;
+ }
+ if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
+ dev->fd = 1;
+ }
+ if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
+ dev->gb = 0;
+ dev->fd = 0;
+ write_mii(0, dev->sp << 13, regs);
+ }
+ }
+
+ }
+ auto_neg_done:
+#ifdef DEBUG
+ printf("%s GRETH Ethermac at [0x%x] irq %d. Running \
+ %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
+#endif
+ /* Read out PHY info if extended registers are available */
+ if (tmp & 1) {
+ tmp1 = read_mii(2, regs);
+ tmp2 = read_mii(3, regs);
+ tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
+ tmp = tmp2 & 0xF;
+
+ tmp2 = (tmp2 >> 4) & 0x3F;
+#ifdef DEBUG
+ printf("PHY: Vendor %x Device %x Revision %d\n", tmp1,
+ tmp2, tmp);
+#endif
+ } else {
+ printf("PHY info not available\n");
+ }
+
+ /* set speed and duplex bits in control register */
+ GRETH_REGORIN(®s->control,
+ (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
+
+ return 0;
+}
+
+void greth_halt(struct eth_device *dev)
+{
+ greth_priv *greth;
+ greth_regs *regs;
+ int i;
+#ifdef DEBUG
+ printf("greth_halt\n");
+#endif
+ if (!dev || !dev->priv)
+ return;
+
+ greth = dev->priv;
+ regs = greth->regs;
+
+ if (!regs)
+ return;
+
+ /* disable receiver/transmitter by clearing the enable bits */
+ GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN));
+
+ /* reset rx/tx descriptors */
+ if (greth->rxbd_base) {
+ for (i = 0; i < GRETH_RXBD_CNT; i++) {
+ greth->rxbd_base[i].stat =
+ (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
+ }
+ }
+
+ if (greth->txbd_base) {
+ for (i = 0; i < GRETH_TXBD_CNT; i++) {
+ greth->txbd_base[i].stat =
+ (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
+ }
+ }
+}
+
+int greth_send(struct eth_device *dev, volatile void *eth_data, int data_length)
+{
+ greth_priv *greth = dev->priv;
+ greth_regs *regs = greth->regs;
+ greth_bd *txbd;
+ void *txbuf;
+ unsigned int status;
+#ifdef DEBUG
+ printf("greth_send\n");
+#endif
+ /* send data, wait for data to be sent, then return */
+ if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
+ && !greth->gbit_mac) {
+ /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
+ * and copy data to before giving it to GRETH.
+ */
+ if (!greth->txbuf) {
+ greth->txbuf = malloc(GRETH_RXBUF_SIZE);
+#ifdef DEBUG
+ printf("GRETH: allocated aligned tx-buf\n");
+#endif
+ }
+
+ txbuf = greth->txbuf;
+
+ /* copy data info buffer */
+ memcpy((char *)txbuf, (char *)eth_data, data_length);
+
+ /* keep buffer to next time */
+ } else {
+ txbuf = (void *)eth_data;
+ }
+ /* get descriptor to use, only 1 supported... hehe easy */
+ txbd = greth->txbd_base;
+
+ /* setup descriptor to wrap around to it self */
+ txbd->addr = (unsigned int)txbuf;
+ txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
+
+ /* Remind Core which descriptor to use when sending */
+ GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd);
+
+ /* initate send by enabling transmitter */
+ GRETH_REGORIN(®s->control, GRETH_TXEN);
+
+ /* Wait for data to be sent */
+ while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
+ ;
+ }
+
+ /* was the packet transmitted succesfully? */
+ if (status & GRETH_TXBD_ERR_AL) {
+ greth->stats.tx_limit_errors++;
+ }
+
+ if (status & GRETH_TXBD_ERR_UE) {
+ greth->stats.tx_underrun_errors++;
+ }
+
+ if (status & GRETH_TXBD_ERR_LC) {
+ greth->stats.tx_latecol_errors++;
+ }
+
+ if (status &
+ (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
+ /* any error */
+ greth->stats.tx_errors++;
+ return -1;
+ }
+
+ /* bump tx packet counter */
+ greth->stats.tx_packets++;
+
+ /* return succefully */
+ return 0;
+}
+
+int greth_recv(struct eth_device *dev)
+{
+ greth_priv *greth = dev->priv;
+ greth_regs *regs = greth->regs;
+ greth_bd *rxbd;
+ unsigned int status, len = 0, bad;
+ unsigned char *d;
+ int enable = 0;
+ int i;
+#ifdef DEBUG
+/* printf("greth_recv\n"); */
+#endif
+ /* Receive One packet only, but clear as many error packets as there are
+ * available.
+ */
+ {
+ /* current receive descriptor */
+ rxbd = greth->rxbd_curr;
+
+ /* get status of next received packet */
+ status = GRETH_REGLOAD(&rxbd->stat);
+
+ bad = 0;
+
+ /* stop if no more packets received */
+ if (status & GRETH_BD_EN) {
+ goto done;
+ }
+#ifdef DEBUG
+ printf("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
+ (unsigned int)rxbd, status, status & GRETH_BD_LEN);
+#endif
+
+ /* Check status for errors.
+ */
+ if (status & GRETH_RXBD_ERR_FT) {
+ greth->stats.rx_length_errors++;
+ bad = 1;
+ }
+ if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
+ greth->stats.rx_frame_errors++;
+ bad = 1;
+ }
+ if (status & GRETH_RXBD_ERR_CRC) {
+ greth->stats.rx_crc_errors++;
+ bad = 1;
+ }
+ if (bad) {
+ greth->stats.rx_errors++;
+ printf
+ ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
+ greth->stats.rx_length_errors,
+ greth->stats.rx_frame_errors,
+ greth->stats.rx_crc_errors, status,
+ greth->stats.rx_packets);
+ /* print all rx descriptors */
+ for (i = 0; i < GRETH_RXBD_CNT; i++) {
+ printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
+ GRETH_REGLOAD(&greth->rxbd_base[i].stat),
+ GRETH_REGLOAD(&greth->rxbd_base[i].
+ addr));
+ }
+ } else {
+ /* Process the incoming packet. */
+ len = status & GRETH_BD_LEN;
+ d = (char *)rxbd->addr;
+#ifdef DEBUG
+ printf
+ ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
+ len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
+ d[7]);
+#endif
+ /* flush all data cache to make sure we're not reading old packet data */
+ sparc_dcache_flush_all();
+
+ /* pass packet on to network subsystem */
+ NetReceive((void *)d, len);
+
+ /* bump stats counters */
+ greth->stats.rx_packets++;
+
+ /* bad is now 0 ==> will stop loop */
+ }
+
+ /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
+ rxbd->stat =
+ GRETH_BD_EN |
+ (((unsigned int)greth->rxbd_curr >=
+ (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
+ enable = 1;
+
+ /* increase index */
+ greth->rxbd_curr =
+ ((unsigned int)greth->rxbd_curr >=
+ (unsigned int)greth->rxbd_max) ? greth->
+ rxbd_base : (greth->rxbd_curr + 1);
+
+ };
+
+ if (enable) {
+ GRETH_REGORIN(®s->control, GRETH_RXEN);
+ }
+ done:
+ /* return positive length of packet or 0 if non recieved */
+ return len;
+}
+
+void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
+{
+ /* save new MAC address */
+ greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
+ greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
+ greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
+ greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
+ greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
+ greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
+ greth->regs->esa_msb = (mac[0] << 8) | mac[1];
+ greth->regs->esa_lsb =
+ (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
+#ifdef DEBUG
+ printf("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+#endif
+}
+
+int greth_initialize(bd_t * bis)
+{
+ greth_priv *greth;
+ ambapp_apbdev apbdev;
+ struct eth_device *dev;
+ int i;
+ char *addr_str, *end;
+ unsigned char addr[6];
+#ifdef DEBUG
+ printf("Scanning for GRETH\n");
+#endif
+ /* Find Device & IRQ via AMBA Plug&Play information */
+ if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
+ return -1; /* GRETH not found */
+ }
+
+ greth = (greth_priv *) malloc(sizeof(greth_priv));
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(greth, 0, sizeof(greth_priv));
+
+ greth->regs = (greth_regs *) apbdev.address;
+ greth->irq = apbdev.irq;
+#ifdef DEBUG
+ printf("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
+#endif
+ dev->priv = (void *)greth;
+ dev->iobase = (unsigned int)greth->regs;
+ dev->init = greth_init;
+ dev->halt = greth_halt;
+ dev->send = greth_send;
+ dev->recv = greth_recv;
+ greth->dev = dev;
+
+ /* Reset Core */
+ GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
+
+ /* Wait for core to finish reset cycle */
+ while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
+
+ /* Get the phy address which assumed to have been set
+ correctly with the reset value in hardware */
+ greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
+
+ /* Check if mac is gigabit capable */
+ greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
+
+ /* Make descriptor string */
+ if (greth->gbit_mac) {
+ sprintf(dev->name, "GRETH 10/100/GB");
+ } else {
+ sprintf(dev->name, "GRETH 10/100");
+ }
+
+ /* initiate PHY, select speed/duplex depending on connected PHY */
+ if (greth_init_phy(greth, bis)) {
+ /* Failed to init PHY (timedout) */
+ return -1;
+ }
+
+ /* Register Device to EtherNet subsystem */
+ eth_register(dev);
+
+ /* Get MAC address */
+ if ((addr_str = getenv("ethaddr")) != NULL) {
+ for (i = 0; i < 6; i++) {
+ addr[i] =
+ addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
+ if (addr_str) {
+ addr_str = (*end) ? end + 1 : end;
+ }
+ }
+ } else {
+ /* HW Address not found in environment, Set default HW address */
+ addr[0] = GRETH_HWADDR_0; /* MSB */
+ addr[1] = GRETH_HWADDR_1;
+ addr[2] = GRETH_HWADDR_2;
+ addr[3] = GRETH_HWADDR_3;
+ addr[4] = GRETH_HWADDR_4;
+ addr[5] = GRETH_HWADDR_5; /* LSB */
+ }
+
+ /* set and remember MAC address */
+ greth_set_hwaddr(greth, addr);
+
+ return 1;
+}
--- /dev/null
+/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GRETH_FD 0x10
+#define GRETH_RESET 0x40
+#define GRETH_MII_BUSY 0x8
+#define GRETH_MII_NVALID 0x10
+
+/* MII registers */
+#define GRETH_MII_EXTADV_1000FD 0x00000200
+#define GRETH_MII_EXTADV_1000HD 0x00000100
+#define GRETH_MII_EXTPRT_1000FD 0x00000800
+#define GRETH_MII_EXTPRT_1000HD 0x00000400
+
+#define GRETH_MII_100T4 0x00000200
+#define GRETH_MII_100TXFD 0x00000100
+#define GRETH_MII_100TXHD 0x00000080
+#define GRETH_MII_10FD 0x00000040
+#define GRETH_MII_10HD 0x00000020
+
+#define GRETH_BD_EN 0x800
+#define GRETH_BD_WR 0x1000
+#define GRETH_BD_IE 0x2000
+#define GRETH_BD_LEN 0x7FF
+
+#define GRETH_TXEN 0x1
+#define GRETH_INT_TX 0x8
+#define GRETH_TXI 0x4
+#define GRETH_TXBD_STATUS 0x0001C000
+#define GRETH_TXBD_MORE 0x20000
+#define GRETH_TXBD_IPCS 0x40000
+#define GRETH_TXBD_TCPCS 0x80000
+#define GRETH_TXBD_UDPCS 0x100000
+#define GRETH_TXBD_ERR_LC 0x10000
+#define GRETH_TXBD_ERR_UE 0x4000
+#define GRETH_TXBD_ERR_AL 0x8000
+#define GRETH_TXBD_NUM 128
+#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
+#define GRETH_TX_BUF_SIZE 2048
+
+#define GRETH_INT_RX 0x4
+#define GRETH_RXEN 0x2
+#define GRETH_RXI 0x8
+#define GRETH_RXBD_STATUS 0xFFFFC000
+#define GRETH_RXBD_ERR_AE 0x4000
+#define GRETH_RXBD_ERR_FT 0x8000
+#define GRETH_RXBD_ERR_CRC 0x10000
+#define GRETH_RXBD_ERR_OE 0x20000
+#define GRETH_RXBD_ERR_LE 0x40000
+#define GRETH_RXBD_IP_DEC 0x80000
+#define GRETH_RXBD_IP_CSERR 0x100000
+#define GRETH_RXBD_UDP_DEC 0x200000
+#define GRETH_RXBD_UDP_CSERR 0x400000
+#define GRETH_RXBD_TCP_DEC 0x800000
+#define GRETH_RXBD_TCP_CSERR 0x1000000
+
+#define GRETH_RXBD_NUM 128
+#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
+#define GRETH_RX_BUF_SIZE 2048
+
+/* Ethernet configuration registers */
+typedef struct _greth_regs {
+ volatile unsigned int control;
+ volatile unsigned int status;
+ volatile unsigned int esa_msb;
+ volatile unsigned int esa_lsb;
+ volatile unsigned int mdio;
+ volatile unsigned int tx_desc_p;
+ volatile unsigned int rx_desc_p;
+} greth_regs;
+
+/* Ethernet buffer descriptor */
+typedef struct _greth_bd {
+ volatile unsigned int stat;
+ unsigned int addr; /* Buffer address not changed by HW */
+} greth_bd;
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
+ /* FEC fix for MCF5275, FEC unable to initial transmit data packet.
+ * A nop will ensure the descriptor polling active completed.
+ */
+#ifdef CONFIG_M5275
+ __asm__ ("nop");
+#endif
+
#ifdef CFG_UNIFY_CACHE
icache_invalid();
#endif
#ifdef CONFIG_XSENGINE
#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inb(p) ({ \
+#define SMC_inb(p) ({ \
unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
}; \
})
-#else /* if not CONFIG_PXA250 */
+#elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */
+
+#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
+
+#define SMC_LEON_SWAP32(_x_) \
+ ({ dword _x = (_x_); \
+ ((_x << 24) | \
+ ((0x0000FF00UL & _x) << 8) | \
+ ((0x00FF0000UL & _x) >> 8) | \
+ (_x >> 24)); })
+
+#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))))
+#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))
+#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))))
+#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))
+#define SMC_inb(p) ({ \
+ word ___v = SMC_inw((p) & ~1); \
+ if ((p) & 1) ___v >>= 8; \
+ else ___v &= 0xff; \
+ ___v; })
+
+#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d))
+#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
+#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d))
+#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
+#define SMC_outb(d,r) do{ word __d = (byte)(d); \
+ word __w = SMC_inw((r)&~1); \
+ __w &= ((r)&1) ? 0x00FF : 0xFF00; \
+ __w |= ((r)&1) ? __d<<8 : __d; \
+ SMC_outw(__w,(r)&~1); \
+ }while(0)
+#define SMC_outsl(r,b,l) do{ int __i; \
+ dword *__b2; \
+ __b2 = (dword *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ SMC_outl_nosw( *(__b2 + __i), r); \
+ } \
+ }while(0)
+#define SMC_outsw(r,b,l) do{ int __i; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ SMC_outw_nosw( *(__b2 + __i), r); \
+ } \
+ }while(0)
+#define SMC_insl(r,b,l) do{ int __i ; \
+ dword *__b2; \
+ __b2 = (dword *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inl_nosw(r); \
+ }; \
+ }while(0)
+
+#define SMC_insw(r,b,l) do{ int __i ; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inw_nosw(r); \
+ }; \
+ }while(0)
+
+#define SMC_insb(r,b,l) do{ int __i ; \
+ byte *__b2; \
+ __b2 = (byte *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = SMC_inb(r); \
+ }; \
+ }while(0)
+
+#else /* if not CONFIG_PXA250 and not CONFIG_LEON */
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
/*
--- /dev/null
+/*
+ * SMSC LAN9[12]1[567] Network driver
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_SMC911X
+
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+
+#define mdelay(n) udelay((n)*1000)
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+/* Below are the register offsets and bit definitions
+ * of the Lan911x memory space
+ */
+#define RX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x00)
+
+#define TX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x20)
+#define TX_CMD_A_INT_ON_COMP (0x80000000)
+#define TX_CMD_A_INT_BUF_END_ALGN (0x03000000)
+#define TX_CMD_A_INT_4_BYTE_ALGN (0x00000000)
+#define TX_CMD_A_INT_16_BYTE_ALGN (0x01000000)
+#define TX_CMD_A_INT_32_BYTE_ALGN (0x02000000)
+#define TX_CMD_A_INT_DATA_OFFSET (0x001F0000)
+#define TX_CMD_A_INT_FIRST_SEG (0x00002000)
+#define TX_CMD_A_INT_LAST_SEG (0x00001000)
+#define TX_CMD_A_BUF_SIZE (0x000007FF)
+#define TX_CMD_B_PKT_TAG (0xFFFF0000)
+#define TX_CMD_B_ADD_CRC_DISABLE (0x00002000)
+#define TX_CMD_B_DISABLE_PADDING (0x00001000)
+#define TX_CMD_B_PKT_BYTE_LENGTH (0x000007FF)
+
+#define RX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x40)
+#define RX_STS_PKT_LEN (0x3FFF0000)
+#define RX_STS_ES (0x00008000)
+#define RX_STS_BCST (0x00002000)
+#define RX_STS_LEN_ERR (0x00001000)
+#define RX_STS_RUNT_ERR (0x00000800)
+#define RX_STS_MCAST (0x00000400)
+#define RX_STS_TOO_LONG (0x00000080)
+#define RX_STS_COLL (0x00000040)
+#define RX_STS_ETH_TYPE (0x00000020)
+#define RX_STS_WDOG_TMT (0x00000010)
+#define RX_STS_MII_ERR (0x00000008)
+#define RX_STS_DRIBBLING (0x00000004)
+#define RX_STS_CRC_ERR (0x00000002)
+#define RX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x44)
+#define TX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x48)
+#define TX_STS_TAG (0xFFFF0000)
+#define TX_STS_ES (0x00008000)
+#define TX_STS_LOC (0x00000800)
+#define TX_STS_NO_CARR (0x00000400)
+#define TX_STS_LATE_COLL (0x00000200)
+#define TX_STS_MANY_COLL (0x00000100)
+#define TX_STS_COLL_CNT (0x00000078)
+#define TX_STS_MANY_DEFER (0x00000004)
+#define TX_STS_UNDERRUN (0x00000002)
+#define TX_STS_DEFERRED (0x00000001)
+#define TX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x4C)
+#define ID_REV __REG(CONFIG_DRIVER_SMC911X_BASE + 0x50)
+#define ID_REV_CHIP_ID (0xFFFF0000) /* RO */
+#define ID_REV_REV_ID (0x0000FFFF) /* RO */
+
+#define INT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x54)
+#define INT_CFG_INT_DEAS (0xFF000000) /* R/W */
+#define INT_CFG_INT_DEAS_CLR (0x00004000)
+#define INT_CFG_INT_DEAS_STS (0x00002000)
+#define INT_CFG_IRQ_INT (0x00001000) /* RO */
+#define INT_CFG_IRQ_EN (0x00000100) /* R/W */
+#define INT_CFG_IRQ_POL (0x00000010) /* R/W */
+ /* Not Affected by SW Reset */
+#define INT_CFG_IRQ_TYPE (0x00000001) /* R/W */
+ /* Not Affected by SW Reset */
+
+#define INT_STS __REG(CONFIG_DRIVER_SMC911X_BASE + 0x58)
+#define INT_STS_SW_INT (0x80000000) /* R/WC */
+#define INT_STS_TXSTOP_INT (0x02000000) /* R/WC */
+#define INT_STS_RXSTOP_INT (0x01000000) /* R/WC */
+#define INT_STS_RXDFH_INT (0x00800000) /* R/WC */
+#define INT_STS_RXDF_INT (0x00400000) /* R/WC */
+#define INT_STS_TX_IOC (0x00200000) /* R/WC */
+#define INT_STS_RXD_INT (0x00100000) /* R/WC */
+#define INT_STS_GPT_INT (0x00080000) /* R/WC */
+#define INT_STS_PHY_INT (0x00040000) /* RO */
+#define INT_STS_PME_INT (0x00020000) /* R/WC */
+#define INT_STS_TXSO (0x00010000) /* R/WC */
+#define INT_STS_RWT (0x00008000) /* R/WC */
+#define INT_STS_RXE (0x00004000) /* R/WC */
+#define INT_STS_TXE (0x00002000) /* R/WC */
+/*#define INT_STS_ERX (0x00001000)*/ /* R/WC */
+#define INT_STS_TDFU (0x00000800) /* R/WC */
+#define INT_STS_TDFO (0x00000400) /* R/WC */
+#define INT_STS_TDFA (0x00000200) /* R/WC */
+#define INT_STS_TSFF (0x00000100) /* R/WC */
+#define INT_STS_TSFL (0x00000080) /* R/WC */
+/*#define INT_STS_RXDF (0x00000040)*/ /* R/WC */
+#define INT_STS_RDFO (0x00000040) /* R/WC */
+#define INT_STS_RDFL (0x00000020) /* R/WC */
+#define INT_STS_RSFF (0x00000010) /* R/WC */
+#define INT_STS_RSFL (0x00000008) /* R/WC */
+#define INT_STS_GPIO2_INT (0x00000004) /* R/WC */
+#define INT_STS_GPIO1_INT (0x00000002) /* R/WC */
+#define INT_STS_GPIO0_INT (0x00000001) /* R/WC */
+#define INT_EN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x5C)
+#define INT_EN_SW_INT_EN (0x80000000) /* R/W */
+#define INT_EN_TXSTOP_INT_EN (0x02000000) /* R/W */
+#define INT_EN_RXSTOP_INT_EN (0x01000000) /* R/W */
+#define INT_EN_RXDFH_INT_EN (0x00800000) /* R/W */
+/*#define INT_EN_RXDF_INT_EN (0x00400000)*/ /* R/W */
+#define INT_EN_TIOC_INT_EN (0x00200000) /* R/W */
+#define INT_EN_RXD_INT_EN (0x00100000) /* R/W */
+#define INT_EN_GPT_INT_EN (0x00080000) /* R/W */
+#define INT_EN_PHY_INT_EN (0x00040000) /* R/W */
+#define INT_EN_PME_INT_EN (0x00020000) /* R/W */
+#define INT_EN_TXSO_EN (0x00010000) /* R/W */
+#define INT_EN_RWT_EN (0x00008000) /* R/W */
+#define INT_EN_RXE_EN (0x00004000) /* R/W */
+#define INT_EN_TXE_EN (0x00002000) /* R/W */
+/*#define INT_EN_ERX_EN (0x00001000)*/ /* R/W */
+#define INT_EN_TDFU_EN (0x00000800) /* R/W */
+#define INT_EN_TDFO_EN (0x00000400) /* R/W */
+#define INT_EN_TDFA_EN (0x00000200) /* R/W */
+#define INT_EN_TSFF_EN (0x00000100) /* R/W */
+#define INT_EN_TSFL_EN (0x00000080) /* R/W */
+/*#define INT_EN_RXDF_EN (0x00000040)*/ /* R/W */
+#define INT_EN_RDFO_EN (0x00000040) /* R/W */
+#define INT_EN_RDFL_EN (0x00000020) /* R/W */
+#define INT_EN_RSFF_EN (0x00000010) /* R/W */
+#define INT_EN_RSFL_EN (0x00000008) /* R/W */
+#define INT_EN_GPIO2_INT (0x00000004) /* R/W */
+#define INT_EN_GPIO1_INT (0x00000002) /* R/W */
+#define INT_EN_GPIO0_INT (0x00000001) /* R/W */
+
+#define BYTE_TEST __REG(CONFIG_DRIVER_SMC911X_BASE + 0x64)
+#define FIFO_INT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x68)
+#define FIFO_INT_TX_AVAIL_LEVEL (0xFF000000) /* R/W */
+#define FIFO_INT_TX_STS_LEVEL (0x00FF0000) /* R/W */
+#define FIFO_INT_RX_AVAIL_LEVEL (0x0000FF00) /* R/W */
+#define FIFO_INT_RX_STS_LEVEL (0x000000FF) /* R/W */
+
+#define RX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x6C)
+#define RX_CFG_RX_END_ALGN (0xC0000000) /* R/W */
+#define RX_CFG_RX_END_ALGN4 (0x00000000) /* R/W */
+#define RX_CFG_RX_END_ALGN16 (0x40000000) /* R/W */
+#define RX_CFG_RX_END_ALGN32 (0x80000000) /* R/W */
+#define RX_CFG_RX_DMA_CNT (0x0FFF0000) /* R/W */
+#define RX_CFG_RX_DUMP (0x00008000) /* R/W */
+#define RX_CFG_RXDOFF (0x00001F00) /* R/W */
+/*#define RX_CFG_RXBAD (0x00000001)*/ /* R/W */
+
+#define TX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x70)
+/*#define TX_CFG_TX_DMA_LVL (0xE0000000)*/ /* R/W */
+/*#define TX_CFG_TX_DMA_CNT (0x0FFF0000)*/ /* R/W */
+ /* Self Clearing */
+#define TX_CFG_TXS_DUMP (0x00008000)
+ /* Self Clearing */
+#define TX_CFG_TXD_DUMP (0x00004000)
+ /* Self Clearing */
+#define TX_CFG_TXSAO (0x00000004) /* R/W */
+#define TX_CFG_TX_ON (0x00000002) /* R/W */
+#define TX_CFG_STOP_TX (0x00000001)
+ /* Self Clearing */
+
+#define HW_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x74)
+#define HW_CFG_TTM (0x00200000) /* R/W */
+#define HW_CFG_SF (0x00100000) /* R/W */
+#define HW_CFG_TX_FIF_SZ (0x000F0000) /* R/W */
+#define HW_CFG_TR (0x00003000) /* R/W */
+#define HW_CFG_PHY_CLK_SEL (0x00000060) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_INT_PHY (0x00000000) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_EXT_PHY (0x00000020) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_CLK_DIS (0x00000040) /* R/W */
+#define HW_CFG_SMI_SEL (0x00000010) /* R/W */
+#define HW_CFG_EXT_PHY_DET (0x00000008) /* RO */
+#define HW_CFG_EXT_PHY_EN (0x00000004) /* R/W */
+#define HW_CFG_32_16_BIT_MODE (0x00000004) /* RO */
+#define HW_CFG_SRST_TO (0x00000002) /* RO */
+#define HW_CFG_SRST (0x00000001)
+ /* Self Clearing */
+
+#define RX_DP_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x78)
+#define RX_DP_CTRL_RX_FFWD (0x80000000) /* R/W */
+#define RX_DP_CTRL_FFWD_BUSY (0x80000000) /* RO */
+
+#define RX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x7C)
+#define RX_FIFO_INF_RXSUSED (0x00FF0000) /* RO */
+#define RX_FIFO_INF_RXDUSED (0x0000FFFF) /* RO */
+
+#define TX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x80)
+#define TX_FIFO_INF_TSUSED (0x00FF0000) /* RO */
+#define TX_FIFO_INF_TDFREE (0x0000FFFF) /* RO */
+
+#define PMT_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x84)
+#define PMT_CTRL_PM_MODE (0x00003000)
+ /* Self Clearing */
+#define PMT_CTRL_PHY_RST (0x00000400)
+ /* Self Clearing */
+#define PMT_CTRL_WOL_EN (0x00000200) /* R/W */
+#define PMT_CTRL_ED_EN (0x00000100) /* R/W */
+#define PMT_CTRL_PME_TYPE (0x00000040) /* R/W */
+ /* Not Affected by SW Reset */
+#define PMT_CTRL_WUPS (0x00000030) /* R/WC */
+#define PMT_CTRL_WUPS_NOWAKE (0x00000000) /* R/WC */
+#define PMT_CTRL_WUPS_ED (0x00000010) /* R/WC */
+#define PMT_CTRL_WUPS_WOL (0x00000020) /* R/WC */
+#define PMT_CTRL_WUPS_MULTI (0x00000030) /* R/WC */
+#define PMT_CTRL_PME_IND (0x00000008) /* R/W */
+#define PMT_CTRL_PME_POL (0x00000004) /* R/W */
+#define PMT_CTRL_PME_EN (0x00000002) /* R/W */
+ /* Not Affected by SW Reset */
+#define PMT_CTRL_READY (0x00000001) /* RO */
+
+#define GPIO_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x88)
+#define GPIO_CFG_LED3_EN (0x40000000) /* R/W */
+#define GPIO_CFG_LED2_EN (0x20000000) /* R/W */
+#define GPIO_CFG_LED1_EN (0x10000000) /* R/W */
+#define GPIO_CFG_GPIO2_INT_POL (0x04000000) /* R/W */
+#define GPIO_CFG_GPIO1_INT_POL (0x02000000) /* R/W */
+#define GPIO_CFG_GPIO0_INT_POL (0x01000000) /* R/W */
+#define GPIO_CFG_EEPR_EN (0x00700000) /* R/W */
+#define GPIO_CFG_GPIOBUF2 (0x00040000) /* R/W */
+#define GPIO_CFG_GPIOBUF1 (0x00020000) /* R/W */
+#define GPIO_CFG_GPIOBUF0 (0x00010000) /* R/W */
+#define GPIO_CFG_GPIODIR2 (0x00000400) /* R/W */
+#define GPIO_CFG_GPIODIR1 (0x00000200) /* R/W */
+#define GPIO_CFG_GPIODIR0 (0x00000100) /* R/W */
+#define GPIO_CFG_GPIOD4 (0x00000010) /* R/W */
+#define GPIO_CFG_GPIOD3 (0x00000008) /* R/W */
+#define GPIO_CFG_GPIOD2 (0x00000004) /* R/W */
+#define GPIO_CFG_GPIOD1 (0x00000002) /* R/W */
+#define GPIO_CFG_GPIOD0 (0x00000001) /* R/W */
+
+#define GPT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x8C)
+#define GPT_CFG_TIMER_EN (0x20000000) /* R/W */
+#define GPT_CFG_GPT_LOAD (0x0000FFFF) /* R/W */
+
+#define GPT_CNT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x90)
+#define GPT_CNT_GPT_CNT (0x0000FFFF) /* RO */
+
+#define ENDIAN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x98)
+#define FREE_RUN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x9C)
+#define RX_DROP __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA0)
+#define MAC_CSR_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA4)
+#define MAC_CSR_CMD_CSR_BUSY (0x80000000)
+ /* Self Clearing */
+#define MAC_CSR_CMD_R_NOT_W (0x40000000) /* R/W */
+#define MAC_CSR_CMD_CSR_ADDR (0x000000FF) /* R/W */
+
+#define MAC_CSR_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA8)
+#define AFC_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0xAC)
+#define AFC_CFG_AFC_HI (0x00FF0000) /* R/W */
+#define AFC_CFG_AFC_LO (0x0000FF00) /* R/W */
+#define AFC_CFG_BACK_DUR (0x000000F0) /* R/W */
+#define AFC_CFG_FCMULT (0x00000008) /* R/W */
+#define AFC_CFG_FCBRD (0x00000004) /* R/W */
+#define AFC_CFG_FCADD (0x00000002) /* R/W */
+#define AFC_CFG_FCANY (0x00000001) /* R/W */
+
+#define E2P_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB0)
+#define E2P_CMD_EPC_BUSY (0x80000000)
+ /* Self Clearing */
+#define E2P_CMD_EPC_CMD (0x70000000) /* R/W */
+#define E2P_CMD_EPC_CMD_READ (0x00000000) /* R/W */
+#define E2P_CMD_EPC_CMD_EWDS (0x10000000) /* R/W */
+#define E2P_CMD_EPC_CMD_EWEN (0x20000000) /* R/W */
+#define E2P_CMD_EPC_CMD_WRITE (0x30000000) /* R/W */
+#define E2P_CMD_EPC_CMD_WRAL (0x40000000) /* R/W */
+#define E2P_CMD_EPC_CMD_ERASE (0x50000000) /* R/W */
+#define E2P_CMD_EPC_CMD_ERAL (0x60000000) /* R/W */
+#define E2P_CMD_EPC_CMD_RELOAD (0x70000000) /* R/W */
+#define E2P_CMD_EPC_TIMEOUT (0x00000200) /* RO */
+#define E2P_CMD_MAC_ADDR_LOADED (0x00000100) /* RO */
+#define E2P_CMD_EPC_ADDR (0x000000FF) /* R/W */
+
+#define E2P_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB4)
+#define E2P_DATA_EEPROM_DATA (0x000000FF) /* R/W */
+/* end of LAN register offsets and bit definitions */
+
+/* MAC Control and Status registers */
+#define MAC_CR (0x01) /* R/W */
+
+/* MAC_CR - MAC Control Register */
+#define MAC_CR_RXALL (0x80000000)
+/* TODO: delete this bit? It is not described in the data sheet. */
+#define MAC_CR_HBDIS (0x10000000)
+#define MAC_CR_RCVOWN (0x00800000)
+#define MAC_CR_LOOPBK (0x00200000)
+#define MAC_CR_FDPX (0x00100000)
+#define MAC_CR_MCPAS (0x00080000)
+#define MAC_CR_PRMS (0x00040000)
+#define MAC_CR_INVFILT (0x00020000)
+#define MAC_CR_PASSBAD (0x00010000)
+#define MAC_CR_HFILT (0x00008000)
+#define MAC_CR_HPFILT (0x00002000)
+#define MAC_CR_LCOLL (0x00001000)
+#define MAC_CR_BCAST (0x00000800)
+#define MAC_CR_DISRTY (0x00000400)
+#define MAC_CR_PADSTR (0x00000100)
+#define MAC_CR_BOLMT_MASK (0x000000C0)
+#define MAC_CR_DFCHK (0x00000020)
+#define MAC_CR_TXEN (0x00000008)
+#define MAC_CR_RXEN (0x00000004)
+
+#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
+#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
+#define HASHH (0x04) /* R/W */
+#define HASHL (0x05) /* R/W */
+
+#define MII_ACC (0x06) /* R/W */
+#define MII_ACC_PHY_ADDR (0x0000F800)
+#define MII_ACC_MIIRINDA (0x000007C0)
+#define MII_ACC_MII_WRITE (0x00000002)
+#define MII_ACC_MII_BUSY (0x00000001)
+
+#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
+
+#define FLOW (0x08) /* R/W */
+#define FLOW_FCPT (0xFFFF0000)
+#define FLOW_FCPASS (0x00000004)
+#define FLOW_FCEN (0x00000002)
+#define FLOW_FCBSY (0x00000001)
+
+#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
+#define VLAN1_VTI1 (0x0000ffff)
+
+#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
+#define VLAN2_VTI2 (0x0000ffff)
+
+#define WUFF (0x0B) /* WO */
+
+#define WUCSR (0x0C) /* R/W */
+#define WUCSR_GUE (0x00000200)
+#define WUCSR_WUFR (0x00000040)
+#define WUCSR_MPR (0x00000020)
+#define WUCSR_WAKE_EN (0x00000004)
+#define WUCSR_MPEN (0x00000002)
+
+/* Chip ID values */
+#define CHIP_9115 0x115
+#define CHIP_9116 0x116
+#define CHIP_9117 0x117
+#define CHIP_9118 0x118
+#define CHIP_9215 0x115a
+#define CHIP_9216 0x116a
+#define CHIP_9217 0x117a
+#define CHIP_9218 0x118a
+
+struct chip_id {
+ u16 id;
+ char *name;
+};
+
+static const struct chip_id chip_ids[] = {
+ { CHIP_9115, "LAN9115" },
+ { CHIP_9116, "LAN9116" },
+ { CHIP_9117, "LAN9117" },
+ { CHIP_9118, "LAN9118" },
+ { CHIP_9215, "LAN9215" },
+ { CHIP_9216, "LAN9216" },
+ { CHIP_9217, "LAN9217" },
+ { CHIP_9218, "LAN9218" },
+ { 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+u32 smc911x_get_mac_csr(u8 reg)
+{
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+ MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg;
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+
+ return MAC_CSR_DATA;
+}
+
+void smc911x_set_mac_csr(u8 reg, u32 data)
+{
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+ MAC_CSR_DATA = data;
+ MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | reg;
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); }
+
+static int smx911x_handle_mac_address(bd_t *bd)
+{
+ unsigned long addrh, addrl;
+ unsigned char *m = bd->bi_enetaddr;
+
+ /* if the environment has a valid mac address then use it */
+ if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) {
+ addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24;
+ addrh = m[4] | m[5] << 8;
+ smc911x_set_mac_csr(ADDRH, addrh);
+ smc911x_set_mac_csr(ADDRL, addrl);
+ } else {
+ /* if not, try to get one from the eeprom */
+ addrh = smc911x_get_mac_csr(ADDRH);
+ addrl = smc911x_get_mac_csr(ADDRL);
+
+ m[0] = (addrl) & 0xff;
+ m[1] = (addrl >> 8) & 0xff;
+ m[2] = (addrl >> 16) & 0xff;
+ m[3] = (addrl >> 24) & 0xff;
+ m[4] = (addrh) & 0xff;
+ m[5] = (addrh >> 8) & 0xff;
+
+ /* we get 0xff when there is no eeprom connected */
+ if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
+ printf(DRIVERNAME ": no valid mac address "
+ "in environment "
+ "and no eeprom found\n");
+ return -1;
+ }
+ }
+
+ printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ m[0], m[1], m[2], m[3], m[4], m[5]);
+
+ return 0;
+}
+
+static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
+{
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
+
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ *val = smc911x_get_mac_csr(MII_DATA);
+
+ return 0;
+}
+
+static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val)
+{
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ smc911x_set_mac_csr(MII_DATA, val);
+ smc911x_set_mac_csr(MII_ACC,
+ phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
+
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+ return 0;
+}
+
+static int smc911x_phy_reset(void)
+{
+ u32 reg;
+
+ reg = PMT_CTRL;
+ reg &= ~0xfffff030;
+ reg |= PMT_CTRL_PHY_RST;
+ PMT_CTRL = reg;
+
+ mdelay(100);
+
+ return 0;
+}
+
+static void smc911x_phy_configure(void)
+{
+ int timeout;
+ u16 status;
+
+ smc911x_phy_reset();
+
+ smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
+ mdelay(1);
+ smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
+ smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ timeout = 5000;
+ do {
+ mdelay(1);
+ if ((timeout--) == 0)
+ goto err_out;
+
+ if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
+ goto err_out;
+ } while (!(status & PHY_BMSR_LS));
+
+ printf(DRIVERNAME ": phy initialized\n");
+
+ return;
+
+err_out:
+ printf(DRIVERNAME ": autonegotiation timed out\n"); }
+
+static void smc911x_reset(void)
+{
+ int timeout;
+
+ /* Take out of PM setting first */
+ if (PMT_CTRL & PMT_CTRL_READY) {
+ /* Write to the bytetest will take out of powerdown */
+ BYTE_TEST = 0x0;
+
+ timeout = 10;
+
+ while (timeout-- && !(PMT_CTRL & PMT_CTRL_READY))
+ udelay(10);
+ if (!timeout) {
+ printf(DRIVERNAME
+ ": timeout waiting for PM restore\n");
+ return;
+ }
+ }
+
+ /* Disable interrupts */
+ INT_EN = 0;
+
+ HW_CFG = HW_CFG_SRST;
+
+ timeout = 1000;
+ while (timeout-- && E2P_CMD & E2P_CMD_EPC_BUSY)
+ udelay(10);
+
+ if (!timeout) {
+ printf(DRIVERNAME ": reset timeout\n");
+ return;
+ }
+
+ /* Reset the FIFO level and flow control settings */
+ smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
+ AFC_CFG = 0x0050287F;
+
+ /* Set to LED outputs */
+ GPIO_CFG = 0x70070000;
+}
+
+static void smc911x_enable(void)
+{
+ /* Enable TX */
+ HW_CFG = 8 << 16 | HW_CFG_SF;
+
+ GPT_CFG = GPT_CFG_TIMER_EN | 10000;
+
+ TX_CFG = TX_CFG_TX_ON;
+
+ /* no padding to start of packets */
+ RX_CFG = 0;
+
+ smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
+
+}
+
+int eth_init(bd_t *bd)
+{
+ unsigned long val, i;
+
+ printf(DRIVERNAME ": initializing\n");
+
+ val = BYTE_TEST;
+ if (val != 0x87654321) {
+ printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val);
+ goto err_out;
+ }
+
+ val = ID_REV >> 16;
+ for (i = 0; chip_ids[i].id != 0; i++) {
+ if (chip_ids[i].id == val)
+ break;
+ }
+ if (!chip_ids[i].id) {
+ printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
+ goto err_out;
+ }
+
+ printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
+
+ smc911x_reset();
+
+ /* Configure the PHY, initialize the link state */
+ smc911x_phy_configure();
+
+ if (smx911x_handle_mac_address(bd))
+ goto err_out;
+
+ /* Turn on Tx + Rx */
+ smc911x_enable();
+
+ return 0;
+
+err_out:
+ return -1;
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ u32 *data = (u32 *)packet;
+ u32 tmplen;
+ u32 status;
+
+ TX_DATA_FIFO = TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length;
+ TX_DATA_FIFO = length;
+
+ tmplen = (length + 3) / 4;
+
+ while (tmplen--)
+ TX_DATA_FIFO = *data++;
+
+ /* wait for transmission */
+ while (!((TX_FIFO_INF & TX_FIFO_INF_TSUSED) >> 16));
+
+ /* get status. Ignore 'no carrier' error, it has no meaning for
+ * full duplex operation
+ */
+ status = TX_STATUS_FIFO & (TX_STS_LOC | TX_STS_LATE_COLL |
+ TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
+
+ if (!status)
+ return 0;
+
+ printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
+ status & TX_STS_LOC ? "TX_STS_LOC " : "",
+ status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
+ status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
+ status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
+ status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
+
+ return -1;
+}
+
+void eth_halt(void)
+{
+ smc911x_reset();
+}
+
+int eth_rx(void)
+{
+ u32 *data = (u32 *)NetRxPackets[0];
+ u32 pktlen, tmplen;
+ u32 status;
+
+ if ((RX_FIFO_INF & RX_FIFO_INF_RXSUSED) >> 16) {
+ status = RX_STATUS_FIFO;
+ pktlen = (status & RX_STS_PKT_LEN) >> 16;
+
+ RX_CFG = 0;
+
+ tmplen = (pktlen + 2 + 3) / 4;
+ while (tmplen--)
+ *data++ = RX_DATA_FIFO;
+
+ if (status & RX_STS_ES)
+ printf(DRIVERNAME
+ ": dropped bad packet. Status: 0x%08x\n",
+ status);
+ else
+ NetReceive(NetRxPackets[0], pktlen);
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_DRIVER_SMC911X */
},
};
+struct phy_info phy_info_VSC8601 = {
+ 0x00007042,
+ "Vitesse VSC8601",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+#ifdef CFG_VSC8601_SKEWFIX
+ {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read,
+ &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
+
struct phy_info phy_info_dm9161 = {
0x0181b88,
"Davicom DM9161E",
&phy_info_dm9161,
&phy_info_lxt971,
&phy_info_VSC8244,
+ &phy_info_VSC8601,
&phy_info_dp83865,
&phy_info_rtl8211b,
&phy_info_generic,
#define MIIM_VSC8244_LED_CON 0x1b
#define MIIM_VSC8244_LEDCON_INIT 0xF011
+/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON 0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
+
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
COBJS-y += pci_indirect.o
COBJS-y += tsi108_pci.o
COBJS-y += w83c553f.o
+COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
+COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
+COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/cpu/sh4/pci-sh4.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <pci.h>
+
+int pci_sh4_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->region_count = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+ hose->region_count++;
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count++;
+
+ udelay(1000);
+
+ pci_set_ops(hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ pci_sh4_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ pci_sh4_write_config_dword);
+
+ pci_register_hose(hose);
+
+ udelay(1000);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ hose->last_busno = pci_hose_scan(hose);
+ return 0;
+}
--- /dev/null
+/*
+ * SH7751 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* Register addresses and such */
+#define SH7751_BCR1 (vu_long *)0xFF800000
+#define SH7751_BCR2 (vu_short*)0xFF800004
+#define SH7751_WCR1 (vu_long *)0xFF800008
+#define SH7751_WCR2 (vu_long *)0xFF80000C
+#define SH7751_WCR3 (vu_long *)0xFF800010
+#define SH7751_MCR (vu_long *)0xFF800014
+#define SH7751_BCR3 (vu_short*)0xFF800050
+#define SH7751_PCICONF0 (vu_long *)0xFE200000
+#define SH7751_PCICONF1 (vu_long *)0xFE200004
+#define SH7751_PCICONF2 (vu_long *)0xFE200008
+#define SH7751_PCICONF3 (vu_long *)0xFE20000C
+#define SH7751_PCICONF4 (vu_long *)0xFE200010
+#define SH7751_PCICONF5 (vu_long *)0xFE200014
+#define SH7751_PCICONF6 (vu_long *)0xFE200018
+#define SH7751_PCICR (vu_long *)0xFE200100
+#define SH7751_PCILSR0 (vu_long *)0xFE200104
+#define SH7751_PCILSR1 (vu_long *)0xFE200108
+#define SH7751_PCILAR0 (vu_long *)0xFE20010C
+#define SH7751_PCILAR1 (vu_long *)0xFE200110
+#define SH7751_PCIMBR (vu_long *)0xFE2001C4
+#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
+#define SH7751_PCIPINT (vu_long *)0xFE2001CC
+#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
+#define SH7751_PCICLKR (vu_long *)0xFE2001D4
+#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
+#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
+#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
+#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
+#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
+#define SH7751_PCIMCR (vu_long *)0xFE2001F4
+#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
+
+#define BCR1_BREQEN 0x00080000
+#define PCI_SH7751_ID 0x35051054
+#define PCI_SH7751R_ID 0x350E1054
+#define SH7751_PCICONF1_WCC 0x00000080
+#define SH7751_PCICONF1_PER 0x00000040
+#define SH7751_PCICONF1_BUM 0x00000004
+#define SH7751_PCICONF1_MES 0x00000002
+#define SH7751_PCICONF1_CMDS 0x000000C6
+#define SH7751_PCI_HOST_BRIDGE 0x6
+#define SH7751_PCICR_PREFIX 0xa5000000
+#define SH7751_PCICR_PRST 0x00000002
+#define SH7751_PCICR_CFIN 0x00000001
+#define SH7751_PCIPINT_D3 0x00000002
+#define SH7751_PCIPINT_D0 0x00000001
+#define SH7751_PCICLKR_PREFIX 0xa5000000
+
+#define SH7751_PCI_MEM_BASE 0xFD000000
+#define SH7751_PCI_MEM_SIZE 0x01000000
+#define SH7751_PCI_IO_BASE 0xFE240000
+#define SH7751_PCI_IO_SIZE 0x00040000
+
+#define SH7751_CS3_BASE_ADDR 0x0C000000
+#define SH7751_P2CS3_BASE_ADDR 0xAC000000
+
+#define SH7751_PCIPAR (vu_long *)0xFE2001C0
+#define SH7751_PCIPDR (vu_long *)0xFE200220
+
+#define p4_in(addr) *(addr)
+#define p4_out(data,addr) *(addr) = (data)
+
+/* Double word */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+ *value = p4_in(SH7751_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+ p4_out(value, SH7751_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh7751_init(struct pci_controller *hose)
+{
+ /* Double-check that we're a 7751 or 7751R chip */
+ if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
+ && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
+ printf("PCI: Unknown PCI host bridge.\n");
+ return 1;
+ }
+ printf("PCI: SH7751 PCI host bridge found.\n");
+
+ /* Double-check some BSC config settings */
+ /* (Area 3 non-MPX 32-bit, PCI bus pins) */
+ if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
+ printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+ return 2;
+ }
+ if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
+ printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ return 3;
+ }
+ if (p4_in(SH7751_BCR2) & 0x01) {
+ printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ return 4;
+ }
+
+ /* Force BREQEN in BCR1 to allow PCIC access */
+ p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
+
+ /* Toggle PCI reset pin */
+ p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
+ udelay(32);
+ p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
+
+ /* Set cmd bits: WCC, PER, BUM, MES */
+ /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
+ p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
+
+ /* Define this host as the host bridge */
+ p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
+
+ /* Force PCI clock(s) on */
+ p4_out(0, SH7751_PCICLKR);
+ p4_out(0x03, SH7751_PCICLKR);
+
+ /* Clear powerdown IRQs, also mask them (unused) */
+ p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
+ p4_out(0, SH7751_PCIPINTM);
+
+ p4_out(0xab000001, SH7751_PCICONF4);
+
+ /* Set up target memory mappings (for external DMA access) */
+ /* Map both P0 and P2 range to Area 3 RAM for ease of use */
+ p4_out((64 - 1) << 20, SH7751_PCILSR0);
+ p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+ p4_out(0, SH7751_PCILSR1);
+ p4_out(0, SH7751_PCILAR1);
+ p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
+ p4_out(0xd0000000, SH7751_PCICONF6);
+
+ /* Map memory window to same address on PCI bus */
+ p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
+
+ /* Map IO window to same address on PCI bus */
+ p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+
+ /* set BREQEN */
+ p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
+
+ /* Copy BSC registers into PCI BSC */
+ p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
+ p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2);
+ p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3);
+ p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
+ p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
+ p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
+ p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
+
+ /* Finally, set central function init complete */
+ p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
+
+ pci_sh4_init(hose);
+
+ return 0;
+}
--- /dev/null
+/*
+ * SH7780 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define SH7780_VENDOR_ID 0x1912
+#define SH7780_DEVICE_ID 0x0002
+#define SH7780_PCICR_PREFIX 0xA5000000
+#define SH7780_PCICR_PFCS 0x00000800
+#define SH7780_PCICR_FTO 0x00000400
+#define SH7780_PCICR_PFE 0x00000200
+#define SH7780_PCICR_TBS 0x00000100
+#define SH7780_PCICR_ARBM 0x00000040
+#define SH7780_PCICR_IOCS 0x00000004
+#define SH7780_PCICR_PRST 0x00000002
+#define SH7780_PCICR_CFIN 0x00000001
+
+#define p4_in(addr) *((vu_long *)addr)
+#define p4_out(data,addr) *(vu_long *)(addr) = (data)
+#define p4_inw(addr) *((vu_short *)addr)
+#define p4_outw(data,addr) *(vu_short *)(addr) = (data)
+
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 *value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+ *value = p4_in(SH7780_PCIPDR);
+
+ return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value)
+{
+ u32 par_data = 0x80000000 | dev;
+
+ p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+ p4_out(value, SH7780_PCIPDR);
+ return 0;
+}
+
+int pci_sh7780_init(struct pci_controller *hose)
+{
+ p4_out(0x01, SH7780_PCIECR);
+
+ if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
+ && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+ printf("PCI: Unknown PCI host bridge.\n");
+ return;
+ }
+ printf("PCI: SH7780 PCI host bridge found.\n");
+
+ /* Toggle PCI reset pin */
+ p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
+ udelay(100000);
+ p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
+ p4_outw(0x0047, SH7780_PCICMD);
+
+ p4_out(0x07F00001, SH7780_PCILSR0);
+ p4_out(0x08000000, SH7780_PCILAR0);
+ p4_out(0x00000000, SH7780_PCILSR1);
+ p4_out(0, SH7780_PCILAR1);
+ p4_out(0x08000000, SH7780_PCIMBAR0);
+ p4_out(0x00000000, SH7780_PCIMBAR1);
+
+ p4_out(0xFD000000, SH7780_PCIMBR0);
+ p4_out(0x00FC0000, SH7780_PCIMBMR0);
+
+ /* if use Operand Cache then enable PCICSCR Soonp bits. */
+ p4_out(0x08000000, SH7780_PCICSAR0);
+ p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
+
+ p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
+ | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
+ SH7780_PCICR);
+
+ pci_sh4_init(hose);
+ return 0;
+}
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
-#define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
-#define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
+# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
+# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
#else
-#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
-#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
-#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
+# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
+# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
#endif
-#if defined(CONFIG_SH4A)
-#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
-#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
-#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
-#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
-#define LSR_ORER 1
-#elif defined (CONFIG_SH4)
-#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER 1
-#elif defined (CONFIG_SH3)
-#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER 0x0200
-#else
-#define SCLSR SCFSR /* SCSSR */
-#define LSR_ORER 1
-#endif
+#if defined(CONFIG_CPU_SH7780) || \
+ defined(CONFIG_CPU_SH7785)
+# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
+# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
+# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0xFF
+#elif defined(CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751) || \
+ defined(CONFIG_CPU_SH7722)
+# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0x1F
+#elif defined(CONFIG_CPU_SH7720)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER 0x0200
+# define FIFOLEVEL_MASK 0x1F
+#elif defined(CONFIG_CPU_SH7710)
+ defined(CONFIG_CPU_SH7712)
+# define SCLSR SCFSR /* SCSSR */
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0x1F
#endif
+/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
-#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#else /* Generic SuperH */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
#define SCR_RE (1 << 4)
return 0;
}
-static int serial_tx_fifo_level (void)
-{
- return (*SCFDR >> 8) & 0x1F;
-}
-
static int serial_rx_fifo_level (void)
{
- return (*SCFDR >> 0) & 0x1F;
+#if defined(CONFIG_SH4A)
+ return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+#else
+ return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+#endif
}
void serial_raw_putc (const char c)
#define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030)
+#define UART1_PWREMU_MGMT (0x01c20430)
+#define UART2_PWREMU_MGMT (0x01c20830)
#define PSC_SILVER_BULLET (0x01c41a20)
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX31_REGS_H
+#define __ASM_ARCH_MX31_REGS_H
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
+
+#define CCM_BASE 0x53f80000
+#define CCM_CCMR (CCM_BASE + 0x00)
+#define CCM_PDR0 (CCM_BASE + 0x04)
+#define CCM_PDR1 (CCM_BASE + 0x08)
+#define CCM_RCSR (CCM_BASE + 0x0c)
+#define CCM_MPCTL (CCM_BASE + 0x10)
+#define CCM_UPCTL (CCM_BASE + 0x10)
+#define CCM_SPCTL (CCM_BASE + 0x18)
+#define CCM_COSR (CCM_BASE + 0x1C)
+
+#define CCMR_MDS (1 << 7)
+#define CCMR_SBYCS (1 << 4)
+#define CCMR_MPE (1 << 3)
+#define CCMR_PRCS_MASK (3 << 1)
+#define CCMR_FPM (1 << 1)
+#define CCMR_CKIH (2 << 1)
+
+#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
+#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+#define PDR0_MCU_PODF(x) ((x) & 0x7)
+
+#define PLL_PD(x) (((x) & 0xf) << 26)
+#define PLL_MFD(x) (((x) & 0x3ff) << 16)
+#define PLL_MFI(x) (((x) & 0xf) << 10)
+#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+#define WEIM_BASE 0xb8002000
+#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
+#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
+#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+
+#define IOMUXC_BASE 0x43FAC000
+#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
+#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
+#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
+
+#define IPU_BASE 0x53fc0000
+#define IPU_CONF IPU_BASE
+
+#define IPU_CONF_PXL_ENDIAN (1<<8)
+#define IPU_CONF_DU_EN (1<<7)
+#define IPU_CONF_DI_EN (1<<6)
+#define IPU_CONF_ADC_EN (1<<5)
+#define IPU_CONF_SDC_EN (1<<4)
+#define IPU_CONF_PF_EN (1<<3)
+#define IPU_CONF_ROT_EN (1<<2)
+#define IPU_CONF_IC_EN (1<<1)
+#define IPU_CONF_SCI_EN (1<<0)
+
+#define WDOG_BASE 0x53FDC000
+
+/*
+ * Signal Multiplexing (IOMUX)
+ */
+
+/* bits in the SW_MUX_CTL registers */
+#define MUX_CTL_OUT_GPIO_DR (0 << 4)
+#define MUX_CTL_OUT_FUNC (1 << 4)
+#define MUX_CTL_OUT_ALT1 (2 << 4)
+#define MUX_CTL_OUT_ALT2 (3 << 4)
+#define MUX_CTL_OUT_ALT3 (4 << 4)
+#define MUX_CTL_OUT_ALT4 (5 << 4)
+#define MUX_CTL_OUT_ALT5 (6 << 4)
+#define MUX_CTL_OUT_ALT6 (7 << 4)
+#define MUX_CTL_IN_NONE (0 << 0)
+#define MUX_CTL_IN_GPIO (1 << 0)
+#define MUX_CTL_IN_FUNC (2 << 0)
+#define MUX_CTL_IN_ALT1 (4 << 0)
+#define MUX_CTL_IN_ALT2 (8 << 0)
+
+#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
+#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
+#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
+#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
+
+/* Register offsets based on IOMUXC_BASE */
+/* 0x00 .. 0x7b */
+#define MUX_CTL_RTS1 0x7c
+#define MUX_CTL_CTS1 0x7d
+#define MUX_CTL_DTR_DCE1 0x7e
+#define MUX_CTL_DSR_DCE1 0x7f
+#define MUX_CTL_CSPI2_SCLK 0x80
+#define MUX_CTL_CSPI2_SPI_RDY 0x81
+#define MUX_CTL_RXD1 0x82
+#define MUX_CTL_TXD1 0x83
+#define MUX_CTL_CSPI2_MISO 0x84
+/* 0x85 .. 0x8a */
+#define MUX_CTL_CSPI2_MOSI 0x8b
+
+/* The modes a specific pin can be in
+ * these macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
+#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
+#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
+#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
+#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE 0x70000000
+#define CSD0_BASE 0x80000000
+#define CSD1_BASE 0x90000000
+#define CS0_BASE 0xA0000000
+#define CS1_BASE 0xA8000000
+#define CS2_BASE 0xB0000000
+#define CS3_BASE 0xB2000000
+#define CS4_BASE 0xB4000000
+#define CS4_PSRAM_BASE 0xB5000000
+#define CS5_BASE 0xB6000000
+#define PCMCIA_MEM_BASE 0xC0000000
+
+#endif /* __ASM_ARCH_MX31_REGS_H */
/*
- * U-boot - start1.S Code running out of RAM after relocation
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
-#define ASSEMBLY
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
+#ifndef __ASM_ARCH_MX31_H
+#define __ASM_ARCH_MX31_H
-.global start1;
-.global _start1;
+u32 mx31_get_mpl_dpdgck_clk(void);
+u32 mx31_get_mcu_main_clk(void);
+u32 mx31_get_ipg_clk(void);
+void mx31_gpio_mux(unsigned long mode);
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
+#endif /* __ASM_ARCH_MX31_H */
# error Memory Map does not fit into configuration
#endif
-/* Sanity check BFIN_CPU */
-#ifndef BFIN_CPU
-# error BFIN_CPU: your board config needs to define this
+/* Sanity check CONFIG_BFIN_CPU */
+#ifndef CONFIG_BFIN_CPU
+# error CONFIG_BFIN_CPU: your board config needs to define this
#endif
/* Make sure the structure is properly aligned */
#define DSPI_DMCR_CTXF (0x00000800)
#define DSPI_DMCR_DRXF (0x00001000)
#define DSPI_DMCR_DTXF (0x00002000)
+#define DSPI_DMCR_MDIS (0x00004000)
#define DSPI_DMCR_CSIS0 (0x00010000)
+#define DSPI_DMCR_CSIS1 (0x00020000)
#define DSPI_DMCR_CSIS2 (0x00040000)
#define DSPI_DMCR_CSIS3 (0x00080000)
+#define DSPI_DMCR_CSIS4 (0x00100000)
#define DSPI_DMCR_CSIS5 (0x00200000)
+#define DSPI_DMCR_CSIS6 (0x00400000)
+#define DSPI_DMCR_CSIS7 (0x00800000)
#define DSPI_DMCR_ROOE (0x01000000)
#define DSPI_DMCR_PCSSE (0x02000000)
#define DSPI_DMCR_MTFE (0x04000000)
#define DSPI_DCTAR_CPHA (0x02000000)
#define DSPI_DCTAR_CPOL (0x04000000)
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_DBR (0x80000000)
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
/* Bit definitions and macros for DRFDR group */
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+void dspi_init(void);
+void dspi_tx(int chipsel, u8 attrib, u16 data);
+u16 dspi_rx(void);
+
#endif /* __DSPI_H__ */
#endif
#endif /* CONFIG_M5272 */
+#ifdef CONFIG_M5275
+#include <asm/immap_5275.h>
+#include <asm/m5275.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC0)
+#define CFG_FEC1_IOBASE (MMAP_FEC1)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (192)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5275 */
+
#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>
--- /dev/null
+/*
+ * MCF5274/5 Internal Memory Map
+ *
+ * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
+ * Based on work Copyright (c) 2003 Josef Baumgartner
+ * <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5275__
+#define __IMMAP_5275__
+
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
+#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_RCM (CFG_MBAR + 0x00110000)
+#define MMAP_CCM (CFG_MBAR + 0x00110004)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_USB (CFG_MBAR + 0x001C0000)
+#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
+
+/* System configuration registers
+*/
+typedef struct sys_ctrl {
+ u32 ipsbar;
+ u32 res1;
+ u32 rambar;
+ u32 res2;
+ u8 crsr;
+ u8 cwcr;
+ u8 lpicr;
+ u8 cwsr;
+ u8 res3[8];
+ u32 mpark;
+ u8 mpr;
+ u8 res4[3];
+ u8 pacr0;
+ u8 pacr1;
+ u8 pacr2;
+ u8 pacr3;
+ u8 pacr4;
+ u8 res5;
+ u8 pacr5;
+ u8 pacr6;
+ u8 pacr7;
+ u8 res6;
+ u8 pacr8;
+ u8 res7;
+ u8 gpacr;
+ u8 res8[3];
+} sysctrl_t;
+/* SDRAM controller registers, offset: 0x040
+ */
+typedef struct sdram_ctrl {
+ u32 sdmr;
+ u32 sdcr;
+ u32 sdcfg1;
+ u32 sdcfg2;
+ u32 sdbar0;
+ u32 sdbmr0;
+ u32 sdbar1;
+ u32 sdbmr1;
+} sdramctrl_t;
+
+/* Chip select module registers, offset: 0x080
+*/
+typedef struct cs_ctlr {
+ u16 ar0;
+ u16 res1;
+ u32 mr0;
+ u16 res2;
+ u16 cr0;
+ u16 ar1;
+ u16 res3;
+ u32 mr1;
+ u16 res4;
+ u16 cr1;
+ u16 ar2;
+ u16 res5;
+ u32 mr2;
+ u16 res6;
+ u16 cr2;
+ u16 ar3;
+ u16 res7;
+ u32 mr3;
+ u16 res8;
+ u16 cr3;
+ u16 ar4;
+ u16 res9;
+ u32 mr4;
+ u16 res10;
+ u16 cr4;
+ u16 ar5;
+ u16 res11;
+ u32 mr5;
+ u16 res12;
+ u16 cr5;
+ u16 ar6;
+ u16 res13;
+ u32 mr6;
+ u16 res14;
+ u16 cr6;
+ u16 ar7;
+ u16 res15;
+ u32 mr7;
+ u16 res16;
+ u16 cr7;
+} csctrl_t;
+
+/* DMA module registers, offset 0x100
+ */
+typedef struct dma_ctrl {
+ u32 sar;
+ u32 dar;
+ u32 dsrbcr;
+ u32 dcr;
+} dma_t;
+
+/* QSPI module registers, offset 0x340
+ */
+typedef struct qspi_ctrl {
+ u16 qmr;
+ u8 res1[2];
+ u16 qdlyr;
+ u8 res2[2];
+ u16 qwr;
+ u8 res3[2];
+ u16 qir;
+ u8 res4[2];
+ u16 qar;
+ u8 res5[2];
+ u16 qdr;
+ u8 res6[2];
+} qspi_t;
+
+/* Interrupt module registers, offset 0xc00
+*/
+typedef struct int_ctrl {
+ u32 iprh0;
+ u32 iprl0;
+ u32 imrh0;
+ u32 imrl0;
+ u32 frch0;
+ u32 frcl0;
+ u8 irlr;
+ u8 iacklpr;
+ u8 res1[0x26];
+ u8 icr0[64]; /* No ICR0, done this way for readability */
+ u8 res2[0x60];
+ u8 swiack0;
+ u8 res3[3];
+ u8 Lniack0_1;
+ u8 res4[3];
+ u8 Lniack0_2;
+ u8 res5[3];
+ u8 Lniack0_3;
+ u8 res6[3];
+ u8 Lniack0_4;
+ u8 res7[3];
+ u8 Lniack0_5;
+ u8 res8[3];
+ u8 Lniack0_6;
+ u8 res9[3];
+ u8 Lniack0_7;
+ u8 res10[3];
+} int0_t;
+
+/* GPIO port registers
+*/
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_res1[4];
+ u8 podr_busctl;
+ u8 podr_addr;
+ u8 podr_res2[2];
+ u8 podr_cs;
+ u8 podr_res3;
+ u8 podr_fec0h;
+ u8 podr_fec0l;
+ u8 podr_feci2c;
+ u8 podr_qspi;
+ u8 podr_sdram;
+ u8 podr_timerh;
+ u8 podr_timerl;
+ u8 podr_uartl;
+ u8 podr_fec1h;
+ u8 podr_fec1l;
+ u8 podr_bs;
+ u8 podr_res4;
+ u8 podr_usbh;
+ u8 podr_usbl;
+ u8 podr_uarth;
+ u8 podr_res5[3];
+ /* Port Data Direction Registers */
+ u8 pddr_res1[4];
+ u8 pddr_busctl;
+ u8 pddr_addr;
+ u8 pddr_res2[2];
+ u8 pddr_cs;
+ u8 pddr_res3;
+ u8 pddr_fec0h;
+ u8 pddr_fec0l;
+ u8 pddr_feci2c;
+ u8 pddr_qspi;
+ u8 pddr_sdram;
+ u8 pddr_timerh;
+ u8 pddr_timerl;
+ u8 pddr_uartl;
+ u8 pddr_fec1h;
+ u8 pddr_fec1l;
+ u8 pddr_bs;
+ u8 pddr_res4;
+ u8 pddr_usbh;
+ u8 pddr_usbl;
+ u8 pddr_uarth;
+ u8 pddr_res5[3];
+ /* Port Pin Data/Set Registers */
+ u8 ppdsdr_res1[4];
+ u8 ppdsdr_busctl;
+ u8 ppdsdr_addr;
+ u8 ppdsdr_res2[2];
+ u8 ppdsdr_cs;
+ u8 ppdsdr_res3;
+ u8 ppdsdr_fec0h;
+ u8 ppdsdr_fec0l;
+ u8 ppdsdr_feci2c;
+ u8 ppdsdr_qspi;
+ u8 ppdsdr_sdram;
+ u8 ppdsdr_timerh;
+ u8 ppdsdr_timerl;
+ u8 ppdsdr_uartl;
+ u8 ppdsdr_fec1h;
+ u8 ppdsdr_fec1l;
+ u8 ppdsdr_bs;
+ u8 ppdsdr_res4;
+ u8 ppdsdr_usbh;
+ u8 ppdsdr_usbl;
+ u8 ppdsdr_uarth;
+ u8 ppdsdr_res5[3];
+ /* Port Clear Output Data Registers */
+ u8 pclrr_res1[4];
+ u8 pclrr_busctl;
+ u8 pclrr_addr;
+ u8 pclrr_res2[2];
+ u8 pclrr_cs;
+ u8 pclrr_res3;
+ u8 pclrr_fec0h;
+ u8 pclrr_fec0l;
+ u8 pclrr_feci2c;
+ u8 pclrr_qspi;
+ u8 pclrr_sdram;
+ u8 pclrr_timerh;
+ u8 pclrr_timerl;
+ u8 pclrr_uartl;
+ u8 pclrr_fec1h;
+ u8 pclrr_fec1l;
+ u8 pclrr_bs;
+ u8 pclrr_res4;
+ u8 pclrr_usbh;
+ u8 pclrr_usbl;
+ u8 pclrr_uarth;
+ u8 pclrr_res5[3];
+ /* Pin Assignment Registers */
+ u8 par_addr;
+ u8 par_cs;
+ u16 par_busctl;
+ u8 par_res1[2];
+ u16 par_usb;
+ u8 par_fec0hl;
+ u8 par_fec1hl;
+ u16 par_timer;
+ u16 par_uart;
+ u16 par_qspi;
+ u16 par_sdram;
+ u16 par_feci2c;
+ u8 par_bs;
+ u8 par_res2[3];
+} gpio_t;
+
+
+/* PWM module registers
+ */
+typedef struct pwm_ctrl {
+ u8 pwcr0;
+ u8 res1[3];
+ u8 pwcr1;
+ u8 res2[3];
+ u8 pwcr2;
+ u8 res3[7];
+ u8 pwwd0;
+ u8 res4[3];
+ u8 pwwd1;
+ u8 res5[3];
+ u8 pwwd2;
+ u8 res6[7];
+} pwm_t;
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+ u16 wcr;
+ u16 wmr;
+ u16 wcntr;
+ u16 wsr;
+ u8 res4[114];
+} wdog_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+ u16 res1;
+ u16 fnr;
+ u16 res2;
+ u16 fnmr;
+ u16 res3;
+ u16 rfmr;
+ u16 res4;
+ u16 rfmmr;
+ u8 res5[3];
+ u8 far;
+ u32 asr;
+ u32 drr1;
+ u32 drr2;
+ u16 res6;
+ u16 specr;
+ u16 res7;
+ u16 ep0sr;
+ u32 iep0cfg;
+ u32 oep0cfg;
+ u32 ep1cfg;
+ u32 ep2cfg;
+ u32 ep3cfg;
+ u32 ep4cfg;
+ u32 ep5cfg;
+ u32 ep6cfg;
+ u32 ep7cfg;
+ u32 ep0ctl;
+ u16 res8;
+ u16 ep1ctl;
+ u16 res9;
+ u16 ep2ctl;
+ u16 res10;
+ u16 ep3ctl;
+ u16 res11;
+ u16 ep4ctl;
+ u16 res12;
+ u16 ep5ctl;
+ u16 res13;
+ u16 ep6ctl;
+ u16 res14;
+ u16 ep7ctl;
+ u32 ep0isr;
+ u16 res15;
+ u16 ep1isr;
+ u16 res16;
+ u16 ep2isr;
+ u16 res17;
+ u16 ep3isr;
+ u16 res18;
+ u16 ep4isr;
+ u16 res19;
+ u16 ep5isr;
+ u16 res20;
+ u16 ep6isr;
+ u16 res21;
+ u16 ep7isr;
+ u32 ep0imr;
+ u16 res22;
+ u16 ep1imr;
+ u16 res23;
+ u16 ep2imr;
+ u16 res24;
+ u16 ep3imr;
+ u16 res25;
+ u16 ep4imr;
+ u16 res26;
+ u16 ep5imr;
+ u16 res27;
+ u16 ep6imr;
+ u16 res28;
+ u16 ep7imr;
+ u32 ep0dr;
+ u32 ep1dr;
+ u32 ep2dr;
+ u32 ep3dr;
+ u32 ep4dr;
+ u32 ep5dr;
+ u32 ep6dr;
+ u32 ep7dr;
+ u16 res29;
+ u16 ep0dpr;
+ u16 res30;
+ u16 ep1dpr;
+ u16 res31;
+ u16 ep2dpr;
+ u16 res32;
+ u16 ep3dpr;
+ u16 res33;
+ u16 ep4dpr;
+ u16 res34;
+ u16 ep5dpr;
+ u16 res35;
+ u16 ep6dpr;
+ u16 res36;
+ u16 ep7dpr;
+ u8 res37[788];
+ u8 cfgram[1024];
+} usb_t;
+
+/* PLL module registers
+ */
+typedef struct pll_ctrl {
+ u32 syncr;
+ u32 synsr;
+} pll_t;
+
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+#endif /* __IMMAP_5275__ */
--- /dev/null
+/*
+ * MCF5275 Internal Memory Map
+ *
+ * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M5275_H__
+#define __M5275_H__
+
+/*
+ * Define the 5275 SIM register set addresses. These are similar,
+ * but not quite identical to the 5282 registers and offsets.
+ */
+#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCF_GPIO_PAR_UART 0x10007c
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+
+#define MCF_GPIO_PAR_FECI2C 0x100082
+#define PAR_SDA_ENABLE_MASK 0x0003
+#define PAR_SCL_ENABLE_MASK 0x000c
+
+#define MCFSIM_WRRR 0x140000
+#define MCFSIM_SDCR 0x40
+
+/*********************************************************************
+ * SDRAM Controller (SDRAMC)
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
+#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
+#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
+#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
+#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
+#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
+#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
+#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD (0x00010000)
+#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
+#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
+#define MCF_SDRAMC_SDCR_IREF (0x00000004)
+#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
+#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
+#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_REF (0x10000000)
+#define MCF_SDRAMC_SDCR_CKE (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
+#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
+#define MCF_SDRAMC_SDMRn_V (0x00000001)
+#define MCF_SDRAMC_SDMRn_WP (0x00000080)
+#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
+#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
+#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
+#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
+#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
+#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
+
+/*********************************************************************
+ * Interrupt Controller (INTC)
+ ********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC0_TXF (23)
+#define INT0_LO_FEC0_TXB (24)
+#define INT0_LO_FEC0_UN (25)
+#define INT0_LO_FEC0_RL (26)
+#define INT0_LO_FEC0_RXF (27)
+#define INT0_LO_FEC0_RXB (28)
+#define INT0_LO_FEC0_MII (29)
+#define INT0_LO_FEC0_LC (30)
+#define INT0_LO_FEC0_HBERR (31)
+#define INT0_HI_FEC0_GRA (32)
+#define INT0_HI_FEC0_EBERR (33)
+#define INT0_HI_FEC0_BABT (34)
+#define INT0_HI_FEC0_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_USB (43)
+#define INT0_HI_USB_EP0 (44)
+#define INT0_HI_USB_EP1 (45)
+#define INT0_HI_USB_EP2 (46)
+#define INT0_HI_USB_EP3 (47)
+/* 48-63 Reserved */
+
+/* 0-22 Reserved */
+#define INT1_LO_FEC1_TXF (23)
+#define INT1_LO_FEC1_TXB (24)
+#define INT1_LO_FEC1_UN (25)
+#define INT1_LO_FEC1_RL (26)
+#define INT1_LO_FEC1_RXF (27)
+#define INT1_LO_FEC1_RXB (28)
+#define INT1_LO_FEC1_MII (29)
+#define INT1_LO_FEC1_LC (30)
+#define INT1_LO_FEC1_HBERR (31)
+#define INT1_HI_FEC1_GRA (32)
+#define INT1_HI_FEC1_EBERR (33)
+#define INT1_HI_FEC1_BABT (34)
+#define INT1_HI_FEC1_BABR (35)
+/* 36-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+#define FMPLL_SYNSR_LOCK (0x00000008)
+
+#endif /* __M5275_H__ */
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
- u32 ddr_sec_clk;
+ u32 mem_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
--- /dev/null
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+
+#define L1_CACHE_BYTES 32
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+void dcache_wback_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbwb %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void dcache_invalid_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES-1);
+ for (v = start; v < end; v+=L1_CACHE_BYTES) {
+ asm volatile("ocbi %0"
+ : /* no output */
+ : "m" (__m(v)));
+ }
+}
+#endif /* CONFIG_SH4 || CONFIG_SH4A */
+
+#endif /* __ASM_SH_CACHE_H */
/*
- * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
-#if defined (CONFIG_CPU_SH7750)
-#include <asm/cpu_sh7750.h>
+#if defined (CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751)
+# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
-#include <asm/cpu_sh7722.h>
+# include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7780)
+# include <asm/cpu_sh7780.h>
#else
-#error "Unknown SH4 variant"
+# error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */
/*
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyright 2007 (C)
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright 2008 (C)
+ * Mark Jonas <mark.jonas@de.bosch.com>
*
* SH7720 Internal I/O register
*
#define PSELD (PFC_BASE + 0x2A)
/* I/O Port */
+#define PORT_BASE 0xA4050100
+#define PADR (PORT_BASE + 0x40)
+#define PBDR (PORT_BASE + 0x42)
+#define PCDR (PORT_BASE + 0x44)
+#define PDDR (PORT_BASE + 0x46)
+#define PEDR (PORT_BASE + 0x48)
+#define PFDR (PORT_BASE + 0x4A)
+#define PGDR (PORT_BASE + 0x4C)
+#define PHDR (PORT_BASE + 0x4E)
+#define PJDR (PORT_BASE + 0x50)
+#define PKDR (PORT_BASE + 0x52)
+#define PLDR (PORT_BASE + 0x54)
+#define PMDR (PORT_BASE + 0x56)
+#define PPDR (PORT_BASE + 0x58)
+#define PRDR (PORT_BASE + 0x5A)
+#define PSDR (PORT_BASE + 0x5C)
+#define PTDR (PORT_BASE + 0x5E)
+#define PUDR (PORT_BASE + 0x60)
+#define PVDR (PORT_BASE + 0x62)
/* H-UDI */
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
-#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
+#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */
--- /dev/null
+#ifndef _ASM_CPU_SH7780_H_
+#define _ASM_CPU_SH7780_H_
+
+/*
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#define CACHE_OC_NUM_WAYS 1
+#define CCR_CACHE_INIT 0x0000090b
+
+/* Exceptions */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* Memory Management Unit */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* Cache Controller */
+#define CCR 0xFF00001C
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
+#define RAMCR 0xFF000074
+
+/* L Memory */
+#define RAMCR 0xFF000074
+#define LSA0 0xFF000050
+#define LSA1 0xFF000054
+#define LDA0 0xFF000058
+#define LDA1 0xFF00005C
+
+/* Interrupt Controller */
+#define ICR0 0xFFD00000
+#define ICR1 0xFFD0001C
+#define INTPRI 0xFFD00010
+#define INTREQ 0xFFD00024
+#define INTMSK0 0xFFD00044
+#define INTMSK1 0xFFD00048
+#define INTMSK2 0xFFD40080
+#define INTMSKCLR0 0xFFD00064
+#define INTMSKCLR1 0xFFD00068
+#define INTMSKCLR2 0xFFD40084
+#define NMIFCR 0xFFD000C0
+#define USERIMASK 0xFFD30000
+#define INT2PRI0 0xFFD40000
+#define INT2PRI1 0xFFD40004
+#define INT2PRI2 0xFFD40008
+#define INT2PRI3 0xFFD4000C
+#define INT2PRI4 0xFFD40010
+#define INT2PRI5 0xFFD40014
+#define INT2PRI6 0xFFD40018
+#define INT2PRI7 0xFFD4001C
+#define INT2A0 0xFFD40030
+#define INT2A1 0xFFD40034
+#define INT2MSKR 0xFFD40038
+#define INT2MSKCR 0xFFD4003C
+#define INT2B0 0xFFD40040
+#define INT2B1 0xFFD40044
+#define INT2B2 0xFFD40048
+#define INT2B3 0xFFD4004C
+#define INT2B4 0xFFD40050
+#define INT2B5 0xFFD40054
+#define INT2B6 0xFFD40058
+#define INT2B7 0xFFD4005C
+#define INT2GPIC 0xFFD40090
+
+/* local Bus State Controller */
+#define MMSELR 0xFF400020
+#define BCR 0xFF801000
+#define CS0BCR 0xFF802000
+#define CS1BCR 0xFF802010
+#define CS2BCR 0xFF802020
+#define CS4BCR 0xFF802040
+#define CS5BCR 0xFF802050
+#define CS6BCR 0xFF802060
+#define CS0WCR 0xFF802008
+#define CS1WCR 0xFF802018
+#define CS2WCR 0xFF802028
+#define CS4WCR 0xFF802048
+#define CS5WCR 0xFF802058
+#define CS6WCR 0xFF802068
+#define CS5PCR 0xFF802070
+#define CS6PCR 0xFF802080
+
+/* DDR-SDRAM I/F */
+#define MIM_1 0xFE800008
+#define MIM_2 0xFE80000C
+#define SCR_1 0xFE800010
+#define SCR_2 0xFE800014
+#define STR_1 0xFE800018
+#define STR_2 0xFE80001C
+#define SDR_1 0xFE800030
+#define SDR_2 0xFE800034
+#define DBK_1 0xFE800400
+#define DBK_2 0xFE800404
+
+/* PCI Controller */
+#define SH7780_PCIECR 0xFE000008
+#define SH7780_PCIVID 0xFE040000
+#define SH7780_PCIDID 0xFE040002
+#define SH7780_PCICMD 0xFE040004
+#define SH7780_PCISTATUS 0xFE040006
+#define SH7780_PCIRID 0xFE040008
+#define SH7780_PCIPIF 0xFE040009
+#define SH7780_PCISUB 0xFE04000A
+#define SH7780_PCIBCC 0xFE04000B
+#define SH7780_PCICLS 0xFE04000C
+#define SH7780_PCILTM 0xFE04000D
+#define SH7780_PCIHDR 0xFE04000E
+#define SH7780_PCIBIST 0xFE04000F
+#define SH7780_PCIIBAR 0xFE040010
+#define SH7780_PCIMBAR0 0xFE040014
+#define SH7780_PCIMBAR1 0xFE040018
+#define SH7780_PCISVID 0xFE04002C
+#define SH7780_PCISID 0xFE04002E
+#define SH7780_PCICP 0xFE040034
+#define SH7780_PCIINTLINE 0xFE04003C
+#define SH7780_PCIINTPIN 0xFE04003D
+#define SH7780_PCIMINGNT 0xFE04003E
+#define SH7780_PCIMAXLAT 0xFE04003F
+#define SH7780_PCICID 0xFE040040
+#define SH7780_PCINIP 0xFE040041
+#define SH7780_PCIPMC 0xFE040042
+#define SH7780_PCIPMCSR 0xFE040044
+#define SH7780_PCIPMCSRBSE 0xFE040046
+#define SH7780_PCI_CDD 0xFE040047
+#define SH7780_PCICR 0xFE040100
+#define SH7780_PCILSR0 0xFE040104
+#define SH7780_PCILSR1 0xFE040108
+#define SH7780_PCILAR0 0xFE04010C
+#define SH7780_PCILAR1 0xFE040110
+#define SH7780_PCIIR 0xFE040114
+#define SH7780_PCIIMR 0xFE040118
+#define SH7780_PCIAIR 0xFE04011C
+#define SH7780_PCICIR 0xFE040120
+#define SH7780_PCIAINT 0xFE040130
+#define SH7780_PCIAINTM 0xFE040134
+#define SH7780_PCIBMIR 0xFE040138
+#define SH7780_PCIPAR 0xFE0401C0
+#define SH7780_PCIPINT 0xFE0401CC
+#define SH7780_PCIPINTM 0xFE0401D0
+#define SH7780_PCIMBR0 0xFE0401E0
+#define SH7780_PCIMBMR0 0xFE0401E4
+#define SH7780_PCIMBR1 0xFE0401E8
+#define SH7780_PCIMBMR1 0xFE0401EC
+#define SH7780_PCIMBR2 0xFE0401F0
+#define SH7780_PCIMBMR2 0xFE0401F4
+#define SH7780_PCIIOBR 0xFE0401F8
+#define SH7780_PCIIOBMR 0xFE0401FC
+#define SH7780_PCICSCR0 0xFE040210
+#define SH7780_PCICSCR1 0xFE040214
+#define SH7780_PCICSAR0 0xFE040218
+#define SH7780_PCICSAR1 0xFE04021C
+#define SH7780_PCIPDR 0xFE040220
+
+/* DMAC */
+#define DMAC_SAR0 0xFC808020
+#define DMAC_DAR0 0xFC808024
+#define DMAC_TCR0 0xFC808028
+#define DMAC_CHCR0 0xFC80802C
+#define DMAC_SAR1 0xFC808030
+#define DMAC_DAR1 0xFC808034
+#define DMAC_TCR1 0xFC808038
+#define DMAC_CHCR1 0xFC80803C
+#define DMAC_SAR2 0xFC808040
+#define DMAC_DAR2 0xFC808044
+#define DMAC_TCR2 0xFC808048
+#define DMAC_CHCR2 0xFC80804C
+#define DMAC_SAR3 0xFC808050
+#define DMAC_DAR3 0xFC808054
+#define DMAC_TCR3 0xFC808058
+#define DMAC_CHCR3 0xFC80805C
+#define DMAC_DMAOR0 0xFC808060
+#define DMAC_SAR4 0xFC808070
+#define DMAC_DAR4 0xFC808074
+#define DMAC_TCR4 0xFC808078
+#define DMAC_CHCR4 0xFC80807C
+#define DMAC_SAR5 0xFC808080
+#define DMAC_DAR5 0xFC808084
+#define DMAC_TCR5 0xFC808088
+#define DMAC_CHCR5 0xFC80808C
+#define DMAC_SARB0 0xFC808120
+#define DMAC_DARB0 0xFC808124
+#define DMAC_TCRB0 0xFC808128
+#define DMAC_SARB1 0xFC808130
+#define DMAC_DARB1 0xFC808134
+#define DMAC_TCRB1 0xFC808138
+#define DMAC_SARB2 0xFC808140
+#define DMAC_DARB2 0xFC808144
+#define DMAC_TCRB2 0xFC808148
+#define DMAC_SARB3 0xFC808150
+#define DMAC_DARB3 0xFC808154
+#define DMAC_TCRB3 0xFC808158
+#define DMAC_DMARS0 0xFC809000
+#define DMAC_DMARS1 0xFC809004
+#define DMAC_DMARS2 0xFC809008
+#define DMAC_SAR6 0xFC818020
+#define DMAC_DAR6 0xFC818024
+#define DMAC_TCR6 0xFC818028
+#define DMAC_CHCR6 0xFC81802C
+#define DMAC_SAR7 0xFC818030
+#define DMAC_DAR7 0xFC818034
+#define DMAC_TCR7 0xFC818038
+#define DMAC_CHCR7 0xFC81803C
+#define DMAC_SAR8 0xFC818040
+#define DMAC_DAR8 0xFC818044
+#define DMAC_TCR8 0xFC818048
+#define DMAC_CHCR8 0xFC81804C
+#define DMAC_SAR9 0xFC818050
+#define DMAC_DAR9 0xFC818054
+#define DMAC_TCR9 0xFC818058
+#define DMAC_CHCR9 0xFC81805C
+#define DMAC_DMAOR1 0xFC818060
+#define DMAC_SAR10 0xFC818070
+#define DMAC_DAR10 0xFC818074
+#define DMAC_TCR10 0xFC818078
+#define DMAC_CHCR10 0xFC81807C
+#define DMAC_SAR11 0xFC818080
+#define DMAC_DAR11 0xFC818084
+#define DMAC_TCR11 0xFC818088
+#define DMAC_CHCR11 0xFC81808C
+#define DMAC_SARB6 0xFC818120
+#define DMAC_DARB6 0xFC818124
+#define DMAC_TCRB6 0xFC818128
+#define DMAC_SARB7 0xFC818130
+#define DMAC_DARB7 0xFC818134
+#define DMAC_TCRB7 0xFC818138
+#define DMAC_SARB8 0xFC818140
+#define DMAC_DARB8 0xFC818144
+#define DMAC_TCRB8 0xFC818148
+#define DMAC_SARB9 0xFC818150
+#define DMAC_DARB9 0xFC818154
+#define DMAC_TCRB9 0xFC818158
+
+/* Clock Pulse Generator */
+#define FRQCR 0xFFC80000
+#define PLLCR 0xFFC80024
+#define MSTPCR 0xFFC80030
+
+/* Watchdog Timer and Reset */
+#define WTCNT WDTCNT
+#define WDTST 0xFFCC0000
+#define WDTCSR 0xFFCC0004
+#define WDTBST 0xFFCC0008
+#define WDTCNT 0xFFCC0010
+#define WDTBCNT 0xFFCC0018
+
+/* System Control */
+#define MSTPCR 0xFFC80030
+
+/* Timer Unit */
+#define TSTR TSTR0
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
+#define TSTR1 0xFFDC0004
+#define TCOR3 0xFFDC0008
+#define TCNT3 0xFFDC000C
+#define TCR3 0xFFDC0010
+#define TCOR4 0xFFDC0014
+#define TCNT4 0xFFDC0018
+#define TCR4 0xFFDC001C
+#define TCOR5 0xFFDC0020
+#define TCNT5 0xFFDC0024
+#define TCR5 0xFFDC0028
+
+/* Timer/Counter */
+#define CMTCFG 0xFFE30000
+#define CMTFRT 0xFFE30004
+#define CMTCTL 0xFFE30008
+#define CMTIRQS 0xFFE3000C
+#define CMTCH0T 0xFFE30010
+#define CMTCH0ST 0xFFE30020
+#define CMTCH0C 0xFFE30030
+#define CMTCH1T 0xFFE30014
+#define CMTCH1ST 0xFFE30024
+#define CMTCH1C 0xFFE30034
+#define CMTCH2T 0xFFE30018
+#define CMTCH2C 0xFFE30038
+#define CMTCH3T 0xFFE3001C
+#define CMTCH3C 0xFFE3003C
+
+/* Realtime Clock */
+#define R64CNT 0xFFE80000
+#define RSECCNT 0xFFE80004
+#define RMINCNT 0xFFE80008
+#define RHRCNT 0xFFE8000C
+#define RWKCNT 0xFFE80010
+#define RDAYCNT 0xFFE80014
+#define RMONCNT 0xFFE80018
+#define RYRCNT 0xFFE8001C
+#define RSECAR 0xFFE80020
+#define RMINAR 0xFFE80024
+#define RHRAR 0xFFE80028
+#define RWKAR 0xFFE8002C
+#define RDAYAR 0xFFE80030
+#define RMONAR 0xFFE80034
+#define RCR1 0xFFE80038
+#define RCR2 0xFFE8003C
+#define RCR3 0xFFE80050
+#define RYRAR 0xFFE80054
+
+/* Serial Communication Interface with FIFO */
+#define SCIF0_BASE SCSMR0
+#define SCSMR0 0xFFE00000
+#define SCBRR0 0xFFE00004
+#define SCSCR0 0xFFE00008
+#define SCFSR0 0xFFE00010
+#define SCFCR0 0xFFE00018
+#define SCTFDR0 0xFFE0001C
+#define SCRFDR0 0xFFE00020
+#define SCSPTR0 0xFFE00024
+#define SCLSR0 0xFFE00028
+#define SCRER0 0xFFE0002C
+#define SCSMR1 0xFFE10000
+#define SCBRR1 0xFFE10004
+#define SCSCR1 0xFFE10008
+#define SCFSR1 0xFFE10010
+#define SCFCR1 0xFFE10018
+#define SCTFDR1 0xFFE1001C
+#define SCRFDR1 0xFFE10020
+#define SCSPTR1 0xFFE10024
+#define SCLSR1 0xFFE10028
+#define SCRER1 0xFFE1002C
+
+/* Serial I/O with FIFO */
+#define SIMDR 0xFFE20000
+#define SISCR 0xFFE20002
+#define SITDAR 0xFFE20004
+#define SIRDAR 0xFFE20006
+#define SICDAR 0xFFE20008
+#define SICTR 0xFFE2000C
+#define SIFCTR 0xFFE20010
+#define SISTR 0xFFE20014
+#define SIIER 0xFFE20016
+#define SITCR 0xFFE20028
+#define SIRCR 0xFFE2002C
+#define SPICR 0xFFE20030
+
+/* Serial Protocol Interface */
+#define SPCR 0xFFE50000
+#define SPSR 0xFFE50004
+#define SPSCR 0xFFE50008
+#define SPTBR 0xFFE5000C
+#define SPRBR 0xFFE50010
+
+/* Multimedia Card Interface */
+#define CMDR0 0xFFE60000
+#define CMDR1 0xFFE60001
+#define CMDR2 0xFFE60002
+#define CMDR3 0xFFE60003
+#define CMDR4 0xFFE60004
+#define CMDR5 0xFFE60005
+#define CMDSTRT 0xFFE60006
+#define OPCR 0xFFE6000A
+#define CSTR 0xFFE6000B
+#define INTCR0 0xFFE6000C
+#define INTCR1 0xFFE6000D
+#define INTSTR0 0xFFE6000E
+#define INTSTR1 0xFFE6000F
+#define CLKON 0xFFE60010
+#define CTOCR 0xFFE60011
+#define TBCR 0xFFE60014
+#define MODER 0xFFE60016
+#define CMDTYR 0xFFE60018
+#define RSPTYR 0xFFE60019
+#define TBNCR 0xFFE6001A
+#define RSPR0 0xFFE60020
+#define RSPR1 0xFFE60021
+#define RSPR2 0xFFE60022
+#define RSPR3 0xFFE60023
+#define RSPR4 0xFFE60024
+#define RSPR5 0xFFE60025
+#define RSPR6 0xFFE60026
+#define RSPR7 0xFFE60027
+#define RSPR8 0xFFE60028
+#define RSPR9 0xFFE60029
+#define RSPR10 0xFFE6002A
+#define RSPR11 0xFFE6002B
+#define RSPR12 0xFFE6002C
+#define RSPR13 0xFFE6002D
+#define RSPR14 0xFFE6002E
+#define RSPR15 0xFFE6002F
+#define RSPR16 0xFFE60030
+#define RSPRD 0xFFE60031
+#define DTOUTR 0xFFE60032
+#define DR 0xFFE60040
+#define DMACR 0xFFE60044
+#define INTCR2 0xFFE60046
+#define INTSTR2 0xFFE60048
+
+/* Audio Codec Interface */
+#define HACCR 0xFFE40008
+#define HACCSAR 0xFFE40020
+#define HACCSDR 0xFFE40024
+#define HACPCML 0xFFE40028
+#define HACPCMR 0xFFE4002C
+#define HACTIER 0xFFE40050
+#define HACTSR 0xFFE40054
+#define HACRIER 0xFFE40058
+#define HACRSR 0xFFE4005C
+#define HACACR 0xFFE40060
+
+/* Serial Sound Interface */
+#define SSICR 0xFFE70000
+#define SSISR 0xFFE70004
+#define SSITDR 0xFFE70008
+#define SSIRDR 0xFFE7000C
+
+/* Flash memory Controller */
+#define FLCMNCR 0xFFE90000
+#define FLCMDCR 0xFFE90004
+#define FLCMCDR 0xFFE90008
+#define FLADR 0xFFE9000C
+#define FLDATAR 0xFFE90010
+#define FLDTCNTR 0xFFE90014
+#define FLINTDMACR 0xFFE90018
+#define FLBSYTMR 0xFFE9001C
+#define FLBSYCNT 0xFFE90020
+#define FLTRCR 0xFFE9002C
+
+/* General Purpose I/O */
+#define PACR 0xFFEA0000
+#define PBCR 0xFFEA0002
+#define PCCR 0xFFEA0004
+#define PDCR 0xFFEA0006
+#define PECR 0xFFEA0008
+#define PFCR 0xFFEA000A
+#define PGCR 0xFFEA000C
+#define PHCR 0xFFEA000E
+#define PJCR 0xFFEA0010
+#define PKCR 0xFFEA0012
+#define PLCR 0xFFEA0014
+#define PMCR 0xFFEA0016
+#define PADR 0xFFEA0020
+#define PBDR 0xFFEA0022
+#define PCDR 0xFFEA0024
+#define PDDR 0xFFEA0026
+#define PEDR 0xFFEA0028
+#define PFDR 0xFFEA002A
+#define PGDR 0xFFEA002C
+#define PHDR 0xFFEA002E
+#define PJDR 0xFFEA0030
+#define PKDR 0xFFEA0032
+#define PLDR 0xFFEA0034
+#define PMDR 0xFFEA0036
+#define PEPUPR 0xFFEA0048
+#define PHPUPR 0xFFEA004E
+#define PJPUPR 0xFFEA0050
+#define PKPUPR 0xFFEA0052
+#define PMPUPR 0xFFEA0056
+#define PPUPR1 0xFFEA0060
+#define PPUPR2 0xFFEA0062
+#define PMSELR 0xFFEA0080
+
+/* User Break Controller */
+#define CBR0 0xFF200000
+#define CRR0 0xFF200004
+#define CAR0 0xFF200008
+#define CAMR0 0xFF20000C
+#define CBR1 0xFF200020
+#define CRR1 0xFF200024
+#define CAR1 0xFF200028
+#define CAMR1 0xFF20002C
+#define CDR1 0xFF200030
+#define CDMR1 0xFF200034
+#define CETR1 0xFF200038
+#define CCMFR 0xFF200600
+#define CBCR 0xFF200620
+
+#endif /* _ASM_CPU_SH7780_H_ */
--- /dev/null
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/include/asm-sh/pci.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_PCI_H_
+#define _ASM_PCI_H_
+
+#include <pci.h>
+#if defined(CONFIG_SH7751_PCI)
+int pci_sh7751_init(struct pci_controller *hose);
+#elif defined(CONFIG_SH7780_PCI)
+int pci_sh7780_init(struct pci_controller *hose);
+#else
+#error "Not support PCI."
+#endif
+
+/* PCI dword read for sh4 */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 *value);
+
+/* PCI dword write for sh4 */
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value);
+
+#endif /* _ASM_PCI_H_ */
#define _ASM_SH_PROCESSOR_H_
#if defined CONFIG_SH3
# include <asm/cpu_sh3.h>
-#elif defined (CONFIG_SH4)
+#elif defined (CONFIG_SH4) || \
+ defined (CONFIG_SH4A)
# include <asm/cpu_sh4.h>
#endif
#endif
*/
#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#if 0
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#endif
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
""
-#if 0
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#endif
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
+#undef CONFIG_PHY_GIGE /* no GbE detection */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 128
#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_BSP
+#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-#if 0
-#define CONFIG_SHOW_ACTIVITY 1
-#endif
+#define CONFIG_AUTOSCRIPT 1
#endif /* __CONFIG_H */
"save\0" \
""
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
/*
- * Configuation settings for the R5200 board
+ * Configuation settings for the Motorola MC5275EVB board.
*
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * Based on Motorola MC5272C3 board config
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ * By Arthur Shipkowski <art@videon-central.com>
+ * Copyright (C) 2005 Videon Central, Inc.
+ *
+ * Based off of M5272C3 board code by Josef Baumgartner
+ * <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* board/config.h - configuration options, board specific
*/
-#ifndef _R5200_H
-#define _R5200_H
+#ifndef _M5275EVB_H
+#define _M5275EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_R5200 /* define board type */
+#define CONFIG_M5275 /* define processor type */
+#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define CONFIG_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 0xFFFF /* clock modulus */
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CFG_ENV_OFFSET 0x20000
-#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#else
-#define CFG_ENV_ADDR 0xf0020000
+#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
+/* Available command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1
-# define CFG_DISCOVER_PHY
-# define CFG_RX_ETH_BUFFER 8
-# define CFG_FAULT_ECHO_LINK_DOWN
-
-# define CFG_FEC0_PINMUX 0
-# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CFG_DISCOVER_PHY
+#define CFG_RX_ETH_BUFFER 8
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FEC0_PINMUX 0
+#define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+#define CFG_FEC1_PINMUX 0
+#define CFG_FEC1_MIIBASE CFG_FEC1_IOBASE
+#define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_HAS_ETH1
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CFG_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CFG_FAULT_ECHO_LINK_DOWN
-# define CFG_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CFG_DISCOVER_PHY */
+#ifndef CFG_DISCOVER_PHY
+#define FECDUPLEX FULL
+#define FECSPEED _100BASET
+#else
+#ifndef CFG_FAULT_ECHO_LINK_DOWN
+#define CFG_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
#endif
-/* Note: We only copy one sectors worth of application code from location
- * 10200000 for speed purposes. Increase the size if necessary */
-#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
-#define CONFIG_BOOTDELAY 1
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
-#define CFG_PROMPT "u-boot> "
-#define CFG_LONGHELP /* undef to save memory */
+#ifdef CONFIG_MCFFEC
+#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60
+#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if (CONFIG_CMD_KGDB)
+# define CFG_CBSIZE 1024
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+# define CFG_CBSIZE 256
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
-#define CFG_LOAD_ADDR 0x00002000
+#define CFG_LOAD_ADDR 0x800000
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-#define CFG_HZ 1000000
-#define CFG_CLK 100000000
+#define CFG_HZ 1000
+#define CFG_CLK 150000000
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
-#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-
-#define CFG_ENET_BD_BASE 0x480000
+#define CFG_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
-#define CFG_FLASH_BASE 0x10000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE 0xffe00000
-#ifdef CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
#else
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#endif
-#define CFG_MONITOR_LEN 0x20001
+#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial mmap for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_SIZE 0x800000
+#define CFG_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
+#define CFG_AR0_PRELIM (CFG_FLASH_BASE >> 16)
+#define CFG_CR0_PRELIM 0x1980
+#define CFG_MR0_PRELIM 0x001F0001
+
+#define CFG_AR1_PRELIM 0x3000
+#define CFG_CR1_PRELIM 0x1900
+#define CFG_MR1_PRELIM 0x00070001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CFG_FECI2C 0xF0
+#define CFG_FECI2C 0x0FA0
-#endif /* _R5200_H */
+#endif /* _M5275EVB_H */
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#else
-# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
# define CFG_ATMEL_REGION 4
# define CFG_ATMEL_TOTALSECT 11
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
+#ifdef CONFIG_SERIAL_FLASH
+# define CFG_FLASH2_BASE 0x01000000
+# define CFG_STM_SECT 32
+# define CFG_STM_SECTSZ 0x10000
+
+# undef CFG_FLASH_ERASE_TOUT
+# define CFG_FLASH_ERASE_TOUT 20000
+
+# define SER_WREN 0x06
+# define SER_WRDI 0x04
+# define SER_RDID 0x9F
+# define SER_RDSR 0x05
+# define SER_WRSR 0x01
+# define SER_READ 0x03
+# define SER_F_READ 0x0B
+# define SER_PAGE_PROG 0x02
+# define SER_SECT_ERASE 0xD8
+# define SER_BULK_ERASE 0xC7
+# define SER_DEEP_PWRDN 0xB9
+# define SER_RES 0xAB
+#endif
+
#endif
/*
#define CONFIG_ETHPRIME "eTSEC1"
/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Environment
*/
#ifndef CFG_RAMBOOT
/*
* Config on-board EEPROM
*/
-#define CFG_I2C_EEPROM_ADDR 0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*
* General PCI
#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
#ifdef CONFIG_PCI
-
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+#define CFG_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
+
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_GATEWAYIP 10.0.0.1
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC1"
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+#define CONFIG_FSL_SERDES2 0xe3100
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
/*
* Environment
*/
#endif
/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET 0x18000
+#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET 0x19000
+#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Environment
*/
#ifndef CFG_RAMBOOT
--- /dev/null
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7722 1
+#define CONFIG_MIGO_R 1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.10.100
+#define CONFIG_SERVERIP 192.168.10.77
+#define CONFIG_GATEWAYIP 192.168.10.77
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE (0x8C000000)
+#define MIGO_R_FLASH_BASE_1 (0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console
+ information at boot */
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (MIGO_R_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE (MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT 512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MIGO_R_H */
/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth3\0" \
"hostname=alpr\0" \
+ "fdt_file=alpr/alpr.dtb\0" \
+ "fdt_addr=400000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} ${init}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
"rootpath=/opt/projects/alpr/nfs_root\0" \
"bootfile=/alpr/uImage\0" \
"kernel_addr=fff00000\0" \
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#include <asm/blackfin-config-pre.h>
#define CONFIG_BAUDRATE 57600
-#define CONFIG_STAMP 1
#define CONFIG_BOOTDELAY 5
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
-
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 27000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
- ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
- B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
-
-#define CONFIG_VDSP 1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x398
+#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
+#define CONFIG_EBIU_SDBCTL_VAL 0x13
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
#endif
#include <asm/blackfin-config-pre.h>
-#define CONFIG_STAMP 1
#define CONFIG_RTC_BFIN 1
-#define CONFIG_BF533 1
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
/*
* Board settings
*/
*/
#define CONFIG_VIDEO 0
-#define CONFIG_VDSP 1
-
/*
* Clock settings
*/
/* Values can range from 2-65535 */
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
#define CONFIG_SPI_BAUD 2
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK 4
-#endif
/*
* Network settings
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x20004000
-#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#endif
#define CFG_ENV_SIZE 0x2000
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#endif
#define CFG_SDRAM_BASE 0x00000000
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
/*
* Command settings
*/
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
-#endif
/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP */
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_BOOTCOMMAND "run ramboot"
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
-#endif
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- "
-#endif
-
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
- ""
-#endif
#ifdef CONFIG_SOFT_I2C
#if (!CONFIG_SOFT_I2C)
#define CONFIG_CMD_I2C
#endif
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_CMD_DHCP
-#endif
/*
/*
* FLASH organization and environment definitions
*/
-#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
-
-/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
- B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
- B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
-*/
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0xBBC3BBC3
-#define AMBCTL1VAL 0x99B39983
-#define CF_AMBCTL1VAL 0x99B3ffc2
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+
+#define CONFIG_EBIU_SDRRC_VAL 0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
+#define CONFIG_EBIU_SDBCTL_VAL 0x37
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
+#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
+
+#include <asm/blackfin-config-post.h>
#endif
#define CONFIG_BAUDRATE 57600
/* Set default serial console for bf537 */
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BF537 1
#define CONFIG_BOOTDELAY 5
/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
-#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
-#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
-#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
-#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
-
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
#define CONFIG_BFIN_MAC
/* This sets the default state of the cache on U-Boot's boot */
/* Define if want to do post memory test */
#undef CONFIG_POST_TEST
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
/* Values can range from 2-65535 */
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
#define CONFIG_SPI_BAUD 2
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK 4
-#endif
#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC32M8A2_75 1
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND "run ramboot"
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
+#if defined(CONFIG_POST_TEST)
/* POST support */
#define CONFIG_POST ( CFG_POST_MEMORY | \
CFG_POST_UART | \
*/
#include <config_cmd_default.h>
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IDE
#endif
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-
#define CONFIG_CMD_DHCP
#if defined(CONFIG_POST)
#define CONFIG_CMD_NAND
#endif
-#endif
-
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR 0x1000000
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"protect off 0x20000000 0x2007FFFF;" \
"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-#endif
#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
-/* for bf537-stamp, usrt boot mode still store env in flash */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0x20004000
-#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
#endif
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
-/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
#define ENV_IS_EMBEDDED
-/* #endif */
/* JFFS Partition offset set */
#define CFG_JFFS2_FIRST_BANK 0
#define CONFIG_TWICLK_KHZ 50
#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x25
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
#if defined CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
#define AMBCTL0VAL 0x7BB07BB0
#define AMBCTL1VAL 0xFFC27BB0
-#define CONFIG_VDSP 1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
-
#if defined(CONFIG_BFIN_IDE)
#define CONFIG_DOS_PARTITION 1
#endif /*CONFIG_BFIN_IDE */
+#include <asm/blackfin-config-post.h>
+
#endif
#include <asm/blackfin-config-pre.h>
-#define CONFIG_VDSP 1
-#define CONFIG_BF561 1
-
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_BAUDRATE 57600
#define CONFIG_PANIC_HANG 1
#define CONFIG_BFIN_CPU bf561-0.3
-
-/*
-* Boot Mode Set
-* Blackfin can support several boot modes
-*/
-#define BF561_BYPASS_BOOT 0x21
-#define BF561_PARA_BOOT 0x22
-#define BF561_SPI_BOOT 0x24
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF561_BYPASS_BOOT
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
/*
* Board settings
*/
/*
* FLASH organization and environment definitions
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x15
-#define AMGCTLVAL 0x3F
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP 0x8
-#define SHT_STRTAB_VDSP 0x1
-#define ELFSHDRSIZE_VDSP 0x2C
-#define VDSP_ENTRY_ADDR 0xFFA00000
-#endif
+#include <asm/blackfin-config-post.h>
#endif /* __CONFIG_EZKIT561_H__ */
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
+/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
+#ifndef CONFIG_CANYONLANDS
+#define CONFIG_460GT 1 /* Specific PPC460GT */
+#else
+#define CONFIG_460EX 1 /* Specific PPC460EX */
+#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_460EX 1 /* Specific PPC460EX support */
#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
-#define CONFIG_HAS_ETH0 1
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+/* Only Glacier (460GT) has 4 EMAC interfaces */
+#ifdef CONFIG_460GT
+#define CONFIG_PHY2_ADDR 2
+#define CONFIG_PHY3_ADDR 3
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
/*-----------------------------------------------------------------------
* USB-OHCI
*----------------------------------------------------------------------*/
+/* Only Canyonlands (460EX) has USB */
+#ifdef CONFIG_460EX
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
#define CFG_USB_OHCI_SLOT_NAME "ppc440"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
/*-----------------------------------------------------------------------
* Default environment
#undef CONFIG_BOOTARGS
+/* Setup some board specific values for the default environment variables */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_HOSTNAME canyonlands
+#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
+#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
+#else
+#define CONFIG_HOSTNAME glacier
+#define CFG_BOOTFILE "bootfile=glacier/uImage\0"
+#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CFG_BOOTFILE \
+ CFG_DTBFILE \
"netdev=eth0\0" \
- "hostname=canyonlands\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
- "bootfile=canyonlands/uImage\0" \
- "fdt_file=canyonlands/canyonlands.dtb\0" \
"fdt_addr=400000\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc200000\0" \
"initrd_high=30000000\0" \
- "load=tftp 200000 canyonlands/u-boot.bin\0" \
+ "load=tftp 200000 ${hostname}/u-boot.bin\0" \
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
"cp.b ${fileaddr} fffa0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
- "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
+ "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
"setenv filesize;saveenv\0" \
"nupd=run nload nupdate\0" \
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
+#ifdef CONFIG_460EX
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
+#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
/*
* PPC4xx GPIO Configuration
*/
+#ifdef CONFIG_460EX
+/* 460EX: Use USB configuration */
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
+#else
+/* 460GT: Use EMAC2+3 configuration */
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define DV_EVM
#define CFG_NAND_SMALLPAGE
#define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
+ * flash instead of AMD flash
+ */
/*===================*/
/* SoC Configuration */
/*===================*/
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
#ifdef CFG_USE_NAND
#undef CFG_ENV_IS_IN_FLASH
#define CFG_NO_FLASH
-#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CFG_NAND_SMALLPAGE
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CFG_ENV_SIZE SZ_16K
#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CFG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CFG_NO_FLASH
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+#else
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#endif
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
+#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs), v3, tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; " \
+ "protect off all; erase 0xa00d0000 0xa01effff; " \
+ "cp.b 0x80000000 0xa00d0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_ENV_ADDR 0xa01f0000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (64 * 1024)
+#define CFG_ENV_SIZE (64 * 1024)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CFG_I2C_MX31_PORT2 1
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0xfe
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY 3
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 $(uimage); bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; " \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot); " \
+ "protect off 0xa0000000 +0x20000; " \
+ "erase 0xa0000000 +0x20000; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage); " \
+ "erase 0xa0040000 +0x180000; " \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2); " \
+ "erase 0xa01c0000 0xa1ffffff; " \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x00 /* environment starts here */
+#define CFG_ENV_SIZE 4096
+#define CFG_I2C_EEPROM_ADDR 0x52
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
* Manufacturer's information serial EEPROM parameters
*/
#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
-#define MAN_SERIAL_NO_FIELD 2
-#define MAN_SERIAL_NO_LENGTH 13
+#define MAN_INFO_FIELD 2
+#define MAN_INFO_LENGTH 9
#define MAN_MAC_ADDR_FIELD 3
-#define MAN_MAC_ADDR_LENGTH 17
+#define MAN_MAC_ADDR_LENGTH 12
/*
* Base addresses -- Note these are effective addresses where the actual
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_FLASH0_SIZE 0x01000000
+#define CFG_FLASH0_ADDR (-CFG_FLASH0_SIZE)
+#define CFG_FLASH1_TOP 0xF8000000
+#define CFG_FLASH1_MAX_SIZE 0x08000000
+#define CFG_FLASH1_ADDR (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
+#define CFG_FLASH_BASE CFG_FLASH1_ADDR /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
/*
* FLASH related
*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
/*
* DDR SDRAM
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
#define CFG_DRAM_TEST
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*
* I2C
#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
+/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "kernel_addr=FC000000\0" \
- "ramdisk_addr=FC180000\0" \
+ "kernel_addr=F4000000\0" \
+ "ramdisk_addr=F4400000\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 200000 FFFA0000 60000\0" \
#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
#define CONFIG_PHY_DYNAMIC_ANEG 1
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
+ * Korat-specific options
+ */
+#define CFG_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
+
+/*
* PCI stuff
*/
/* General PCI */
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
+#if CFG_FLASH0_SIZE == 0x01000000
+#define CFG_EBC_PB0AP 0x04017300
+#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x0009A000)
+#elif CFG_FLASH0_SIZE == 0x04000000
#define CFG_EBC_PB0AP 0x04017300
-#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000)
+#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x000DA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH0_SIZE
+#endif
/* Memory Bank 1 (NOR-FLASH) initialization */
+#if CFG_FLASH1_MAX_SIZE == 0x08000000
#define CFG_EBC_PB1AP 0x04017300
-#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000)
+#define CFG_EBC_PB1CR (CFG_FLASH1_ADDR | 0x000FA000)
+#else
+#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
+#endif
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04017300
* GPIO63 xxxx x x (reserved for trace port)
*/
+#define CFG_GPIO_ATMEGA_RESET_ 12
#define CFG_GPIO_ATMEGA_SS_ 13
#define CFG_GPIO_PHY0_FIBER_SEL 27
#define CFG_GPIO_PHY1_FIBER_SEL 28
#define CFG_GPIO_SFP1_TX_EN_ 33
#define CFG_GPIO_PHY0_EN 45
#define CFG_GPIO_PHY1_EN 46
+#define CFG_GPIO_RESET_PRESSED_ 47
/*
* PPC440 GPIO Configuration
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
/* unused GPT0 COMP reg */
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/* Additional registers for watchdog timer post test */
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
-#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
#define CFG_POST_ECC_ON CFG_POST_ECC
-#else
-#define CFG_POST_ECC_ON 0
-#endif
/* POST support */
#define CONFIG_POST (CFG_POST_CACHE | \
--- /dev/null
+/*
+ * Configuation settings for MPR2
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPR2_H
+#define __MPR2_H
+
+/* Supported commands */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+
+/* Default environment variables */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_BOOTFILE /boot/zImage
+#define CONFIG_LOADADDR 0x8E000000
+#define CONFIG_VERSION_VARIABLE
+
+/* CPU and platform */
+#define CONFIG_SH 1
+#define CONFIG_SH3 1
+#define CONFIG_CPU_SH7720 1
+#define CONFIG_MPR2 1
+
+/* U-Boot internals */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_GBL_DATA_SIZE 256
+
+/* Memory */
+#define CFG_SDRAM_BASE 0x8C000000
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_BASE 0xA0000000
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Clocks */
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* UART */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+
+#endif /* __MPR2_H */
--- /dev/null
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Disabled for now due to build problems under Debian and
+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " \
+ "protect off 0xa0000000 0xa001ffff; " \
+ "erase 0xa0000000 0xa001ffff; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0"
+
+#define CONFIG_DRIVER_CS8900 1
+#define CS8900_BASE 0xb4020300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR CSD0_BASE /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE CS0_BASE
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (32 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
+ * The rest of 32MiB is in 128KiB big sectors.
+ * U-Boot occupies the low 4 sectors,
+ * if we put environment next to it, we will have to occupy 128KiB for it.
+ * Putting it at the top of flash we use only 32KiB. */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#if 0 /* Doesn't work yet, work in progress */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes(~10x faster)*/
+#endif
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2008 Prodrive BV <pieter.voorthijsen@prodrive.nl>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define CFG_PMDRA
+#define CFG_NAND_LARGEPAGE
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x10000000
+#define CFG_DAVINCI_ACFG2 0x00460385 /* NOR CE Config */
+#define CFG_DAVINCI_ACFG3 0x0822218c /* NAND CE Config */
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 3 /* Use CE3 for NAND */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178832 /* 8 banks , CAS = 4*/
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x12
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_COM2 0x01c20800 /* Base address of UART2 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 50000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CFG_USE_NAND
+#define CFG_NAND_BASE 0x04000000
+#undef CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_ENV_OVERWRITE
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS \
+ "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "run nand"
+#define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7751 1
+#define CONFIG_CPU_SH_TYPE_R 1
+#define CONFIG_R2DPLUS 1
+#define __LITTLE_ENDIAN__ 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF1 1
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.51
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE (0x8C000000)
+#define CFG_SDRAM_SIZE (0x04000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/*
+ * NOR Flash
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_R2DPLUS_OLD)
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1) /* Max number of
+ * Flash memory banks
+ */
+#define CFG_MAX_FLASH_SECT 142
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#else /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+#endif /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ 60000000
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define CFG_PLL_SETTLING_TIME 100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+#define _IO_BASE 0x00000000
+#define KSEG1ADDR(x) (x)
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_CPU_SH7780 1
+#define CONFIG_R7780MP 1
+#define __LITTLE_ENDIAN 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_SCIF0 1
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* check for keypress on bootdelay==0 */
+/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+
+/* Network setting */
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_IPADDR 10.0.192.82
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+
+#define CFG_SDRAM_BASE (0x08000000)
+#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+/* NOR Flash (S29PL127J60TFI130) */
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT 270
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
+ CFG_FLASH_BASE + 0x100000,\
+ CFG_FLASH_BASE + 0x400000,\
+ CFG_FLASH_BASE + 0x700000, }
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN (112 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER (8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (16 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/* #define CONFIG_NET_MULTI
+ #define CONFIG_RTL8169 */
+/* AX88696L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xb4000000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
+#endif /* CONFIG_CMD_IDE */
+
+#endif /* __R7780RP_H */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
+#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*
* I2C
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
"flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty addmisc;" \
#endif /* __MIPS__ */
-#if defined(__AVR32__)
+#if defined(__AVR32__) || defined(__SH__)
struct stat {
unsigned long st_dev;
unsigned long __unused5;
};
-#endif /* __AVR32__ */
+#endif /* __AVR32__ || __SH__ */
#ifdef __cplusplus
}
/* SPRIDR - System Part and Revision ID Register
*/
-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
-
-#define SPR_8349E_REV10 0x80300100
-#define SPR_8349_REV10 0x80310100
-#define SPR_8347E_REV10_TBGA 0x80320100
-#define SPR_8347_REV10_TBGA 0x80330100
-#define SPR_8347E_REV10_PBGA 0x80340100
-#define SPR_8347_REV10_PBGA 0x80350100
-#define SPR_8343E_REV10 0x80360100
-#define SPR_8343_REV10 0x80370100
-
-#define SPR_8349E_REV11 0x80300101
-#define SPR_8349_REV11 0x80310101
-#define SPR_8347E_REV11_TBGA 0x80320101
-#define SPR_8347_REV11_TBGA 0x80330101
-#define SPR_8347E_REV11_PBGA 0x80340101
-#define SPR_8347_REV11_PBGA 0x80350101
-#define SPR_8343E_REV11 0x80360101
-#define SPR_8343_REV11 0x80370101
-
-#define SPR_8349E_REV31 0x80300300
-#define SPR_8349_REV31 0x80310300
-#define SPR_8347E_REV31_TBGA 0x80320300
-#define SPR_8347_REV31_TBGA 0x80330300
-#define SPR_8347E_REV31_PBGA 0x80340300
-#define SPR_8347_REV31_PBGA 0x80350300
-#define SPR_8343E_REV31 0x80360300
-#define SPR_8343_REV31 0x80370300
-
-#define SPR_8360E_REV10 0x80480010
-#define SPR_8360_REV10 0x80490010
-#define SPR_8360E_REV11 0x80480011
-#define SPR_8360_REV11 0x80490011
-#define SPR_8360E_REV12 0x80480012
-#define SPR_8360_REV12 0x80490012
-#define SPR_8360E_REV20 0x80480020
-#define SPR_8360_REV20 0x80490020
-#define SPR_8360E_REV21 0x80480021
-#define SPR_8360_REV21 0x80490021
-
-#define SPR_8323E_REV10 0x80620010
-#define SPR_8323_REV10 0x80630010
-#define SPR_8321E_REV10 0x80660010
-#define SPR_8321_REV10 0x80670010
-#define SPR_8323E_REV11 0x80620011
-#define SPR_8323_REV11 0x80630011
-#define SPR_8321E_REV11 0x80660011
-#define SPR_8321_REV11 0x80670011
-
-#define SPR_8313E_REV10 0x80B00010
-#define SPR_8313_REV10 0x80B10010
-#define SPR_8311E_REV10 0x80B20010
-#define SPR_8311_REV10 0x80B30010
-#define SPR_8315E_REV10 0x80B40010
-#define SPR_8315_REV10 0x80B50010
-#define SPR_8314E_REV10 0x80B60010
-#define SPR_8314_REV10 0x80B70010
-
-#define SPR_8379E_REV10 0x80C20010
-#define SPR_8379_REV10 0x80C30010
-#define SPR_8378E_REV10 0x80C40010
-#define SPR_8378_REV10 0x80C50010
-#define SPR_8377E_REV10 0x80C60010
-#define SPR_8377_REV10 0x80C70010
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
+
+#if defined(CONFIG_MPC834X)
+#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr) (spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr) (spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
+#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */
+
+#define SPR_8311 0x80B2
+#define SPR_8313 0x80B0
+#define SPR_8314 0x80B6
+#define SPR_8315 0x80B4
+#define SPR_8321 0x8066
+#define SPR_8323 0x8062
+#define SPR_8343 0x8036
+#define SPR_8347_TBGA_ 0x8032
+#define SPR_8347_PBGA_ 0x8034
+#define SPR_8349 0x8030
+#define SPR_8358_TBGA_ 0x804A
+#define SPR_8358_PBGA_ 0x804E
+#define SPR_8360 0x8048
+#define SPR_8377 0x80C6
+#define SPR_8378 0x80C4
+#define SPR_8379 0x80C2
/* SPCR - System Priority Configuration Register
*/
#define PCI_DEVICE_ID_INTEL_82434 0x04a3
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
+#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82542 0x1000
#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
+#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
+#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
#endif /* CONFIG_440GX */
#define RGMII_FER (RGMII_BASE + 0x00)
#define RGMII_SSR (RGMII_BASE + 0x04)
+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET 0x100
+#endif
+
/* RGMII Function Enable (FER) Register Bit Definitions */
/* Note: for EMAC 2 and 3 only, 440GX only */
#define RGMII_FER_DIS (0x00)
#
# U-boot Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
+# Copyright (c) 2005-2008 Analog Devices Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
include $(TOPDIR)/config.mk
+CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
+
LIB = $(obj)lib$(ARCH).a
SOBJS-y += memcmp.o
SOBJS-y += memmove.o
SOBJS-y += memset.o
-COBJS-y += bf533_string.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cache.o
COBJS-y += muldi3.o
COBJS-y += post.o
+COBJS-y += string.o
COBJS-y += tests.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+++ /dev/null
-/*
- * U-boot - bf533_string.c Contains library routines.
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include "cache.h"
-#include <asm/mach-common/bits/dma.h>
-
-char *strcpy(char *dest, const char *src)
-{
- char *xdest = dest;
- char temp = 0;
-
- __asm__ __volatile__
- ("1:\t%2 = B [%1++] (Z);\n\t"
- "B [%0++] = %2;\n\t"
- "CC = %2;\n\t"
- "if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
- :"0"(dest), "1"(src), "2"(temp):"memory");
-
- return xdest;
-}
-
-char *strncpy(char *dest, const char *src, size_t n)
-{
- char *xdest = dest;
- char temp = 0;
-
- if (n == 0)
- return xdest;
-
- __asm__ __volatile__
- ("1:\t%3 = B [%1++] (Z);\n\t"
- "B [%0++] = %3;\n\t"
- "CC = %3;\n\t"
- "if ! cc jump 2f;\n\t"
- "%2 += -1;\n\t"
- "CC = %2 == 0;\n\t"
- "if ! cc jump 1b (bp);\n"
- "2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
- :"0"(dest), "1"(src), "2"(n), "3"(temp)
- :"memory");
-
- return xdest;
-}
-
-int strcmp(const char *cs, const char *ct)
-{
- char __res1, __res2;
-
- __asm__("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
- "%3 = B[%1++] (Z);\n\t" /* get *ct */
- "CC = %2 == %3;\n\t" /* compare a byte */
- "if ! cc jump 2f;\n\t" /* not equal, break out */
- "CC = %2;\n\t" /* at end of cs? */
- "if cc jump 1b (bp);\n\t" /* no, keep going */
- "jump.s 3f;\n" /* strings are equal */
- "2:\t%2 = %2 - %3;\n" /* *cs - *ct */
- "3:\n": "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
- : "0"(cs), "1"(ct));
-
- return __res1;
-}
-
-int strncmp(const char *cs, const char *ct, size_t count)
-{
- char __res1, __res2;
-
- if (!count)
- return 0;
-
- __asm__("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
- "%4 = B[%1++] (Z);\n\t" /* get *ct */
- "CC = %3 == %4;\n\t" /* compare a byte */
- "if ! cc jump 3f;\n\t" /* not equal, break out */
- "CC = %3;\n\t" /* at end of cs? */
- "if ! cc jump 4f;\n\t" /* yes, all done */
- "%2 += -1;\n\t" /* no, adjust count */
- "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n" /* more to do, keep going */
- "2:\t%3 = 0;\n\t" /* strings are equal */
- "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
- "4:": "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
- "=d"(__res2)
- : "0"(cs), "1"(ct), "2"(count));
-
- return __res1;
-}
-
-#ifndef pMDMA_D0_IRQ_STATUS
-# define pMDMA_D0_IRQ_STATUS pMDMA1_D0_IRQ_STATUS
-# define pMDMA_D0_START_ADDR pMDMA1_D0_START_ADDR
-# define pMDMA_D0_X_COUNT pMDMA1_D0_X_COUNT
-# define pMDMA_D0_X_MODIFY pMDMA1_D0_X_MODIFY
-# define pMDMA_D0_CONFIG pMDMA1_D0_CONFIG
-# define pMDMA_S0_IRQ_STATUS pMDMA1_S0_IRQ_STATUS
-# define pMDMA_S0_START_ADDR pMDMA1_S0_START_ADDR
-# define pMDMA_S0_X_COUNT pMDMA1_S0_X_COUNT
-# define pMDMA_S0_X_MODIFY pMDMA1_S0_X_MODIFY
-# define pMDMA_S0_CONFIG pMDMA1_S0_CONFIG
-#endif
-
-static void *dma_memcpy(void *dest, const void *src, size_t count)
-{
- *pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
-
- /* Copy sram functions from sdram to sram */
- /* Setup destination start address */
- *pMDMA_D0_START_ADDR = (volatile void **)dest;
- /* Setup destination xcount */
- *pMDMA_D0_X_COUNT = count;
- /* Setup destination xmodify */
- *pMDMA_D0_X_MODIFY = 1;
-
- /* Setup Source start address */
- *pMDMA_S0_START_ADDR = (volatile void **)src;
- /* Setup Source xcount */
- *pMDMA_S0_X_COUNT = count;
- /* Setup Source xmodify */
- *pMDMA_S0_X_MODIFY = 1;
-
- /* Enable source DMA */
- *pMDMA_S0_CONFIG = (DMAEN);
- SSYNC();
-
- *pMDMA_D0_CONFIG = (WNR | DMAEN);
-
- while (*pMDMA_D0_IRQ_STATUS & DMA_RUN) {
- *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
- }
- *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
-
- dest += count;
- src += count;
- return dest;
-}
-
-/*
- * memcpy - Copy one area of memory to another
- * @dest: Where to copy to
- * @src: Where to copy from
- * @count: The size of the area.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-extern void *memcpy_ASM(void *dest, const void *src, size_t count);
-void *memcpy(void *dest, const void *src, size_t count)
-{
- char *tmp = (char *) dest, *s = (char *) src;
-
- if (dcache_status()) {
- blackfin_dcache_flush_range(src, src+count);
- }
- /* L1_INST_SRAM can only be accessed via dma */
- if ((tmp >= (char *)L1_INST_SRAM) && (tmp < (char *)L1_INST_SRAM_END)) {
- /* L1 is the destination */
- dma_memcpy(dest,src,count);
- } else if ((s >= (char *)L1_INST_SRAM) && (s < (char *)L1_INST_SRAM_END)) {
- /* L1 is the source */
- dma_memcpy(dest,src,count);
-
- if (icache_status()) {
- blackfin_icache_flush_range(dest, dest+count);
- }
- if (dcache_status()) {
- blackfin_dcache_invalidate_range(dest, dest+count);
- }
- } else {
- memcpy_ASM(dest,src,count);
- }
- return dest;
-}
+++ /dev/null
-/*
- * U-boot - blackfin_board.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __BLACKFIN_BOARD_H__
-#define __BLACKFIN_BOARD_H__
-
-#include <version.h>
-
-extern void timer_init(void);
-extern void init_IRQ(void);
-extern void rtc_init(void);
-
-extern ulong uboot_end_data;
-extern ulong uboot_end;
-
-ulong monitor_flash_len;
-
-
-#define VERSION_STRING_SIZE 150 /* including 40 bytes buffer to change any string */
-#define VERSION_STRING_FORMAT "%s (%s - %s)\n"
-#define VERSION_STRING U_BOOT_VERSION, __DATE__, __TIME__
-
-char version_string[VERSION_STRING_SIZE];
-
-int *g_addr;
-static ulong mem_malloc_start;
-static ulong mem_malloc_end;
-static ulong mem_malloc_brk;
-extern char _sram_in_sdram_start[];
-extern char _sram_inst_size[];
-#ifdef DEBUG
-static void display_global_data(void);
-#endif
-
-/* definitions used to check the SMC card availability */
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-#define UPPER_BYTE_MASK 0xFF00
-#define SMC_IDENT 0x3300
-
-#endif
/*
* U-boot - board.c First C file to be called contains init routines
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <command.h>
-#include <malloc.h>
#include <devices.h>
-#include <version.h>
-#include <net.h>
#include <environment.h>
#include <i2c.h>
-#include "blackfin_board.h"
+#include <malloc.h>
+#include <net.h>
+#include <version.h>
+
#include <asm/cplb.h>
-#include "../drivers/net/smc91111.h"
+#include <asm/mach-common/bits/mpu.h>
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+#ifdef CONFIG_CMD_NAND
+#include <nand.h> /* cannot even include nand.h if it isnt configured */
+#endif
+
+#if defined(CONFIG_POST)
#include <post.h>
int post_flag;
#endif
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CFG_NO_FLASH
-extern flash_info_t flash_info[];
+const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
+
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ serial_puts("Early: ");
+ serial_puts(s);
#endif
+}
-static inline u_long get_vco(void)
+/* Get the input voltage */
+static u_long get_vco(void)
{
u_long msel;
u_long vco;
return vco;
}
-/*Get the Core clock*/
+/* Get the Core clock */
u_long get_cclk(void)
{
u_long csel, ssel;
return get_vco() / ssel;
}
+static void *mem_malloc_start, *mem_malloc_end, *mem_malloc_brk;
+
static void mem_malloc_init(void)
{
- mem_malloc_start = CFG_MALLOC_BASE;
- mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
+ mem_malloc_start = (void *)CFG_MALLOC_BASE;
+ mem_malloc_end = (void *)(CFG_MALLOC_BASE + CFG_MALLOC_LEN);
mem_malloc_brk = mem_malloc_start;
- memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
+ memset(mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
}
void *sbrk(ptrdiff_t increment)
{
- ulong old = mem_malloc_brk;
- ulong new = old + increment;
+ void *old = mem_malloc_brk;
+ void *new = old + increment;
+
+ if (new < mem_malloc_start || new > mem_malloc_end)
+ return NULL;
- if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
- return (NULL);
- }
mem_malloc_brk = new;
- return ((void *)old);
+ return old;
}
static int display_banner(void)
{
- sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING);
- printf("%s\n", version_string);
+ printf("\n\n%s\n\n", version_string);
printf("CPU: ADSP " MK_STR(CONFIG_BFIN_CPU) " (Detected Rev: 0.%d)\n", bfin_revid());
- return (0);
-}
-
-static void display_flash_config(ulong size)
-{
- puts("FLASH: ");
- print_size(size, "\n");
- return;
+ return 0;
}
static int init_baudrate(void)
{
- char tmp[64];
- int i = getenv_r("baudrate", tmp, sizeof(tmp));
+ char baudrate[15];
+ int i = getenv_r("baudrate", baudrate, sizeof(baudrate));
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
- ? (int)simple_strtoul(tmp, NULL, 10)
+ ? simple_strtoul(baudrate, NULL, 10)
: CONFIG_BAUDRATE;
- return (0);
+ return 0;
}
-#ifdef DEBUG
static void display_global_data(void)
{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
bd_t *bd;
bd = gd->bd;
- printf("--flags:%x\n", gd->flags);
- printf("--board_type:%x\n", gd->board_type);
- printf("--baudrate:%x\n", gd->baudrate);
- printf("--have_console:%x\n", gd->have_console);
- printf("--ram_size:%x\n", gd->ram_size);
- printf("--reloc_off:%x\n", gd->reloc_off);
- printf("--env_addr:%x\n", gd->env_addr);
- printf("--env_valid:%x\n", gd->env_valid);
- printf("--bd:%x %x\n", gd->bd, bd);
- printf("---bi_baudrate:%x\n", bd->bi_baudrate);
- printf("---bi_ip_addr:%x\n", bd->bi_ip_addr);
- printf("---bi_enetaddr:%x %x %x %x %x %x\n",
- bd->bi_enetaddr[0],
- bd->bi_enetaddr[1],
- bd->bi_enetaddr[2],
- bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
- printf("---bi_arch_number:%x\n", bd->bi_arch_number);
- printf("---bi_boot_params:%x\n", bd->bi_boot_params);
- printf("---bi_memstart:%x\n", bd->bi_memstart);
- printf("---bi_memsize:%x\n", bd->bi_memsize);
- printf("---bi_flashstart:%x\n", bd->bi_flashstart);
- printf("---bi_flashsize:%x\n", bd->bi_flashsize);
- printf("---bi_flashoffset:%x\n", bd->bi_flashoffset);
- printf("--jt:%x *:%x\n", gd->jt, *(gd->jt));
-}
+ printf(" gd: %x\n", gd);
+ printf(" |-flags: %x\n", gd->flags);
+ printf(" |-board_type: %x\n", gd->board_type);
+ printf(" |-baudrate: %i\n", gd->baudrate);
+ printf(" |-have_console: %x\n", gd->have_console);
+ printf(" |-ram_size: %x\n", gd->ram_size);
+ printf(" |-reloc_off: %x\n", gd->reloc_off);
+ printf(" |-env_addr: %x\n", gd->env_addr);
+ printf(" |-env_valid: %x\n", gd->env_valid);
+ printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt));
+ printf(" \\-bd: %x\n", gd->bd);
+ printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
+ printf(" |-bi_ip_addr: %x\n", bd->bi_ip_addr);
+ printf(" |-bi_enetaddr: %x %x %x %x %x %x\n",
+ bd->bi_enetaddr[0], bd->bi_enetaddr[1],
+ bd->bi_enetaddr[2], bd->bi_enetaddr[3],
+ bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
+ printf(" |-bi_boot_params: %x\n", bd->bi_boot_params);
+ printf(" |-bi_memstart: %x\n", bd->bi_memstart);
+ printf(" |-bi_memsize: %x\n", bd->bi_memsize);
+ printf(" |-bi_flashstart: %x\n", bd->bi_flashstart);
+ printf(" |-bi_flashsize: %x\n", bd->bi_flashsize);
+ printf(" \\-bi_flashoffset: %x\n", bd->bi_flashoffset);
#endif
+}
-/* we cover everything with 4 meg pages, and need an extra for L1 */
-unsigned int icplb_table[page_descriptor_table_size][2];
-unsigned int dcplb_table[page_descriptor_table_size][2];
-
+#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
+#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
void init_cplbtables(void)
{
- int i, j;
-
- j = 0;
- icplb_table[j][0] = 0xFFA00000;
- icplb_table[j][1] = L1_IMEMORY;
- j++;
-
- for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
- icplb_table[j][0] = (i * 4 * 1024 * 1024);
- if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
- && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
- icplb_table[j][1] = SDRAM_IKERNEL;
- } else {
- icplb_table[j][1] = SDRAM_IGENERIC;
- }
- j++;
+ volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
+ volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA;
+ uint32_t extern_memory;
+ size_t i;
+
+ void icplb_add(uint32_t addr, uint32_t data)
+ {
+ *(ICPLB_ADDR + i) = addr;
+ *(ICPLB_DATA + i) = data;
}
-#if defined(CONFIG_BF561)
- /* MAC space */
- icplb_table[j][0] = 0x2C000000;
- icplb_table[j][1] = SDRAM_INON_CHBL;
- j++;
- /* Async Memory space */
- for (i = 0; i < 3; i++) {
- icplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
- icplb_table[j][1] = SDRAM_INON_CHBL;
- j++;
- }
-#else
- icplb_table[j][0] = 0x20000000;
- icplb_table[j][1] = SDRAM_INON_CHBL;
-#endif
- j = 0;
- dcplb_table[j][0] = 0xFF800000;
- dcplb_table[j][1] = L1_DMEMORY;
- j++;
-
- for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
- dcplb_table[j][0] = (i * 4 * 1024 * 1024);
- if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
- && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
- dcplb_table[j][1] = SDRAM_DKERNEL;
- } else {
- dcplb_table[j][1] = SDRAM_DGENERIC;
- }
- j++;
+ void dcplb_add(uint32_t addr, uint32_t data)
+ {
+ *(DCPLB_ADDR + i) = addr;
+ *(DCPLB_DATA + i) = data;
}
-#if defined(CONFIG_BF561)
- /* MAC space */
- dcplb_table[j][0] = 0x2C000000;
- dcplb_table[j][1] = SDRAM_EBIU;
- j++;
-
- /* Flash space */
- for (i = 0; i < 3; i++) {
- dcplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
- dcplb_table[j][1] = SDRAM_EBIU;
- j++;
+ /* populate a few common entries ... we'll let
+ * the memory map and cplb exception handler do
+ * the rest of the work.
+ */
+ i = 0;
+ ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
+ ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
+ DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
+ DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
+
+ icplb_add(0xFFA00000, L1_IMEMORY);
+ dcplb_add(0xFF800000, L1_DMEMORY);
+ ++i;
+
+ icplb_add(CFG_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_IKERNEL);
+ dcplb_add(CFG_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_DKERNEL);
+ ++i;
+
+ /* If the monitor crosses a 4 meg boundary, we'll need
+ * to lock two entries for it.
+ */
+ if ((CFG_MONITOR_BASE & CPLB_PAGE_MASK) != ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & CPLB_PAGE_MASK)) {
+ icplb_add((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_IKERNEL);
+ dcplb_add((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_DKERNEL);
+ ++i;
}
-#else
- dcplb_table[j][0] = 0x20000000;
- dcplb_table[j][1] = SDRAM_EBIU;
+
+ icplb_add(0x20000000, SDRAM_INON_CHBL);
+ dcplb_add(0x20000000, SDRAM_EBIU);
+ ++i;
+
+ /* Add entries for the rest of external RAM up to the bootrom */
+ extern_memory = 0;
+
+#ifdef CONFIG_DEBUG_NULL_PTR
+ icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+ dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+ ++i;
+ icplb_add(extern_memory, SDRAM_IKERNEL);
+ dcplb_add(extern_memory, SDRAM_DKERNEL);
+ extern_memory += CPLB_PAGE_SIZE;
+ ++i;
#endif
+
+ while (i < 16 && extern_memory < (CFG_MONITOR_BASE & CPLB_PAGE_MASK)) {
+ icplb_add(extern_memory, SDRAM_IGENERIC);
+ dcplb_add(extern_memory, SDRAM_DGENERIC);
+ extern_memory += CPLB_PAGE_SIZE;
+ ++i;
+ }
+ while (i < 16) {
+ icplb_add(0, 0);
+ dcplb_add(0, 0);
+ ++i;
+ }
}
/*
* "continue" and != 0 means "fatal error, hang the system".
*/
+extern int exception_init(void);
+extern int irq_init(void);
+extern int rtc_init(void);
+extern int timer_init(void);
+
void board_init_f(ulong bootflag)
{
ulong addr;
bd_t *bd;
- int i;
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+ serial_early_puts("Board early init flash\n");
+ board_early_init_f();
+#endif
+
+ serial_early_puts("Init CPLB tables\n");
init_cplbtables();
+ serial_early_puts("Exceptions setup\n");
+ exception_init();
+
+#ifndef CONFIG_ICACHE_OFF
+ serial_early_puts("Turn on ICACHE\n");
+ icache_enable();
+#endif
+#ifndef CONFIG_DCACHE_OFF
+ serial_early_puts("Turn on DCACHE\n");
+ dcache_enable();
+#endif
+
+ serial_early_puts("Init global data\n");
gd = (gd_t *) (CFG_GBL_DATA_ADDR);
memset((void *)gd, 0, sizeof(gd_t));
gd->bd = bd;
memset((void *)bd, 0, sizeof(bd_t));
+ bd->bi_r_version = version_string;
+ bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_board_name = BFIN_BOARD_NAME;
+ bd->bi_vco = get_vco();
+ bd->bi_cclk = get_cclk();
+ bd->bi_sclk = get_sclk();
+
/* Initialize */
- init_IRQ();
- env_init(); /* initialize environment */
- init_baudrate(); /* initialze baudrate settings */
- serial_init(); /* serial communications setup */
+ serial_early_puts("IRQ init\n");
+ irq_init();
+ serial_early_puts("Environment init\n");
+ env_init();
+ serial_early_puts("Baudrate init\n");
+ init_baudrate();
+ serial_early_puts("Serial init\n");
+ serial_init();
+ serial_early_puts("Console init flash\n");
console_init_f();
-#ifdef CONFIG_ICACHE_ON
- icache_enable();
-#endif
-#ifdef CONFIG_DCACHE_ON
- dcache_enable();
-#endif
- display_banner(); /* say that we are here */
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- debug
- ("data (%02i)= 0x%08x : 0x%08x intr = 0x%08x : 0x%08x\n",
- i, dcplb_table[i][0], dcplb_table[i][1], icplb_table[i][0],
- icplb_table[i][1]);
- }
+ serial_early_puts("End of early debugging\n");
+ display_banner();
checkboard();
-#if defined(CONFIG_RTC_BF533) && defined(CONFIG_CMD_DATE)
+#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE)
rtc_init();
#endif
timer_init();
+
printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n",
get_vco() / 1000000, get_cclk() / 1000000, get_sclk() / 1000000);
- printf("SDRAM: ");
+
+ printf("RAM: ");
print_size(initdram(0), "\n");
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+#if defined(CONFIG_POST)
post_init_f();
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
+
board_init_r((gd_t *) gd, 0x20000010);
}
void board_init_r(gd_t * id, ulong dest_addr)
{
- ulong size;
extern void malloc_bin_reloc(void);
- char *s, *e;
+ char *s;
bd_t *bd;
- int i;
gd = id;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bd = gd->bd;
-#if defined(CONFIG_BF537) && defined(CONFIG_POST)
+#if defined(CONFIG_POST)
post_output_backlog();
post_reloc();
#endif
-#if (CONFIG_STAMP || CONFIG_BF537 || CONFIG_EZKIT561) && !defined(CFG_NO_FLASH)
+#if !defined(CFG_NO_FLASH)
/* There are some other pointer constants we must deal with */
/* configure available FLASH banks */
- size = flash_init();
- display_flash_config(size);
+ extern flash_info_t flash_info[];
+ ulong size = flash_init();
+ puts("Flash: ");
+ print_size(size, "\n");
flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
bd->bi_flashstart = CFG_FLASH_BASE;
/* relocate environment function pointers etc. */
env_relocate();
+#ifdef CONFIG_CMD_NET
/* board MAC address */
s = getenv("ethaddr");
- for (i = 0; i < 6; ++i) {
- bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
+ if (s == NULL) {
+# ifndef CONFIG_ETHADDR
+# if 0
+ if (!board_get_enetaddr(bd->bi_enetaddr)) {
+ char nid[20];
+ sprintf(nid, "%02X:%02X:%02X:%02X:%02X:%02X",
+ bd->bi_enetaddr[0], bd->bi_enetaddr[1],
+ bd->bi_enetaddr[2], bd->bi_enetaddr[3],
+ bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
+ setenv("ethaddr", nid);
+ }
+# endif
+# endif
+ } else {
+ int i;
+ char *e;
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enetaddr[i] = simple_strtoul(s, &e, 16);
s = (*e) ? e + 1 : e;
+ }
}
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+#endif
/* Initialize devices */
devices_init();
console_init_r();
/* Initialize from environment */
- if ((s = getenv("loadaddr")) != NULL) {
+ if ((s = getenv("loadaddr")) != NULL)
load_addr = simple_strtoul(s, NULL, 16);
- }
-#if defined(CONFIG_CMD_NET)
- if ((s = getenv("bootfile")) != NULL) {
+#ifdef CONFIG_CMD_NET
+ if ((s = getenv("bootfile")) != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
- }
#endif
-#if defined(CONFIG_CMD_NAND)
+#ifdef CONFIG_CMD_NAND
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#endif
#ifdef CONFIG_CMD_NET
- printf("Net: ");
- eth_initialize(bd);
-#endif
-
-#ifdef CONFIG_DRIVER_SMC91111
-#ifdef SHARED_RESOURCES
- /* Switch to Ethernet */
- swap_to(ETHERNET);
+ printf("Net: ");
+ eth_initialize(gd->bd);
+ if (getenv("ethaddr"))
+ printf("MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2],
+ bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
#endif
- if ((SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT) {
- printf("ERROR: Can't find SMC91111 at address %x\n",
- SMC_BASE_ADDRESS);
- } else {
- printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
- }
-#ifdef SHARED_RESOURCES
- swap_to(FLASH);
-#endif
-#endif
#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C)
init_func_i2c();
#endif
-#ifdef DEBUG
display_global_data();
-#endif
-#if defined(CONFIG_BF537) && defined(CONFIG_POST)
+#if defined(CONFIG_POST)
if (post_flag)
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;) {
+ for (;;)
main_loop();
- }
}
void hang(void)
{
puts("### ERROR ### Please RESET the board ###\n");
- for (;;) ;
+ while (1)
+ /* If a JTAG emulator is hooked up, we'll automatically trigger
+ * a breakpoint in it. If one isn't, this is just a NOP.
+ */
+ asm("emuexcpt;");
}
/*
- * U-boot - bf533_linux.c
+ * U-boot - bootm.c - misc boot helper functions
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
-/* Dummy functions, currently not in Use */
-
#include <common.h>
#include <command.h>
#include <image.h>
-#include <zlib.h>
-#include <asm/byteorder.h>
+#include <asm/blackfin.h>
-#define LINUX_MAX_ENVS 256
-#define LINUX_MAX_ARGS 256
-
-#define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#ifdef SHARED_RESOURCES
extern void swap_to(int device_id);
#endif
-extern void flush_instruction_cache(void);
-extern void flush_data_cache(void);
-static char *make_command_line(void);
+static char *make_command_line(void)
+{
+ char *dest = (char *)CMD_LINE_ADDR;
+ char *bootargs = getenv("bootargs");
+
+ if (bootargs == NULL)
+ return NULL;
+
+ strncpy(dest, bootargs, 0x1000);
+ dest[0xfff] = 0;
+ return dest;
+}
-void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
+void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
bootm_headers_t *images)
{
int (*appl) (char *cmdline);
ulong ep = 0;
if (!images->autostart)
- return ;
+ return;
#ifdef SHARED_RESOURCES
swap_to(FLASH);
printf("Starting Kernel at = %x\n", appl);
cmdline = make_command_line();
- if (icache_status()) {
- flush_instruction_cache();
- icache_disable();
- }
- if (dcache_status()) {
- flush_data_cache();
- dcache_disable();
- }
+ icache_disable();
+ dcache_disable();
(*appl) (cmdline);
/* does not return */
return;
-error:
+ error:
if (images->autostart)
do_reset (cmdtp, flag, argc, argv);
- return;
-}
-
-char *make_command_line(void)
-{
- char *dest = (char *)CMD_LINE_ADDR;
- char *bootargs;
-
- if ((bootargs = getenv("bootargs")) == NULL)
- return NULL;
-
- strncpy(dest, bootargs, 0x1000);
- dest[0xfff] = 0;
- return dest;
}
/*
* U-boot - cache.c
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
-/* for now: just dummy functions to satisfy the linker */
-#include <config.h>
#include <common.h>
#include <asm/blackfin.h>
-#include "cache.h"
-void flush_cache(unsigned long dummy1, unsigned long dummy2)
+void flush_cache(unsigned long addr, unsigned long size)
{
- if (dummy1 >= 0xE0000000)
+ /* no need to flush stuff in on chip memory (L1/L2/etc...) */
+ if (addr >= 0xE0000000)
return;
if (icache_status())
- blackfin_icache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2));
- if (dcache_status())
- blackfin_dcache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2));
+ blackfin_icache_flush_range((void *)addr, (void *)(addr + size));
- return;
+ if (dcache_status())
+ blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
}
+++ /dev/null
-/*
- * U-boot - prototypes for cache handling functions.
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _LIB_BLACKFIN_CACHE_H_
-#define _LIB_BLACKFIN_CACHE_H_
-
-extern void blackfin_icache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_invalidate_range(const void *, const void *);
-
-#endif
--- /dev/null
+/*
+ * U-boot - string.c Contains library routines.
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/dma.h>
+
+char *strcpy(char *dest, const char *src)
+{
+ char *xdest = dest;
+ char temp = 0;
+
+ __asm__ __volatile__ (
+ "1:\t%2 = B [%1++] (Z);\n\t"
+ "B [%0++] = %2;\n\t"
+ "CC = %2;\n\t"
+ "if cc jump 1b (bp);\n"
+ : "=a"(dest), "=a"(src), "=d"(temp)
+ : "0"(dest), "1"(src), "2"(temp)
+ : "memory");
+
+ return xdest;
+}
+
+char *strncpy(char *dest, const char *src, size_t n)
+{
+ char *xdest = dest;
+ char temp = 0;
+
+ if (n == 0)
+ return xdest;
+
+ __asm__ __volatile__ (
+ "1:\t%3 = B [%1++] (Z);\n\t"
+ "B [%0++] = %3;\n\t"
+ "CC = %3;\n\t"
+ "if ! cc jump 2f;\n\t"
+ "%2 += -1;\n\t"
+ "CC = %2 == 0;\n\t"
+ "if ! cc jump 1b (bp);\n"
+ "2:\n"
+ : "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+ : "0"(dest), "1"(src), "2"(n), "3"(temp)
+ : "memory");
+
+ return xdest;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+ char __res1, __res2;
+
+ __asm__ (
+ "1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
+ "%3 = B[%1++] (Z);\n\t" /* get *ct */
+ "CC = %2 == %3;\n\t" /* compare a byte */
+ "if ! cc jump 2f;\n\t" /* not equal, break out */
+ "CC = %2;\n\t" /* at end of cs? */
+ "if cc jump 1b (bp);\n\t" /* no, keep going */
+ "jump.s 3f;\n" /* strings are equal */
+ "2:\t%2 = %2 - %3;\n" /* *cs - *ct */
+ "3:\n"
+ : "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
+ : "0"(cs), "1"(ct));
+
+ return __res1;
+}
+
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+ char __res1, __res2;
+
+ if (!count)
+ return 0;
+
+ __asm__(
+ "1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
+ "%4 = B[%1++] (Z);\n\t" /* get *ct */
+ "CC = %3 == %4;\n\t" /* compare a byte */
+ "if ! cc jump 3f;\n\t" /* not equal, break out */
+ "CC = %3;\n\t" /* at end of cs? */
+ "if ! cc jump 4f;\n\t" /* yes, all done */
+ "%2 += -1;\n\t" /* no, adjust count */
+ "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n" /* more to do, keep going */
+ "2:\t%3 = 0;\n\t" /* strings are equal */
+ "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
+ "4:"
+ : "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
+ : "0"(cs), "1"(ct), "2"(count));
+
+ return __res1;
+}
+
+#ifdef bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR
+# define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA1_D0_X_COUNT
+# define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA1_D0_X_MODIFY
+# define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA1_D0_CONFIG
+# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR
+# define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA1_S0_X_COUNT
+# define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA1_S0_X_MODIFY
+# define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA1_S0_CONFIG
+# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS
+#endif
+static void *dma_memcpy(void *dst, const void *src, size_t count)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(src, src + count);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Copy sram functions from sdram to sram */
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst);
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(count);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(1);
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(src);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(count);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(1);
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN);
+ SSYNC();
+
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN)
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+ if (icache_status())
+ blackfin_icache_flush_range(dst, dst + count);
+
+ if (dcache_status())
+ blackfin_dcache_invalidate_range(dst, dst + count);
+
+ return dst;
+}
+
+/*
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * We need to have this wrapper in memcpy() as common code may call memcpy()
+ * to load up L1 regions. Consider loading an ELF which has sections with
+ * LMA's pointing to L1. The common code ELF loader will simply use memcpy()
+ * to move the ELF's sections into the right place. We need to catch that
+ * here and redirect to dma_memcpy().
+ */
+extern void *memcpy_ASM(void *dst, const void *src, size_t count);
+void *memcpy(void *dst, const void *src, size_t count)
+{
+ if (!count)
+ return dst;
+
+ if (addr_bfin_on_chip_mem(dst)) {
+ /* L1 is the destination */
+ return dma_memcpy(dst, src, count);
+
+ } else if (addr_bfin_on_chip_mem(src)) {
+ /* L1 is the source */
+ return dma_memcpy(dst, src, count);
+
+ } else
+ /* No L1 is involved, so just call regular memcpy */
+ return memcpy_ASM(dst, src, count);
+}
#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
#endif
+#if !defined(CFG_MEM_TOP_HIDE)
+#define CFG_MEM_TOP_HIDE 0
+#endif
+
+extern ulong _start;
extern ulong __init_end;
extern ulong _end;
ulong monitor_flash_len;
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
+ * - area that won't get touched by U-Boot and Linux (optional)
* - kernel log buffer
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
- len = (ulong)&_end - CFG_MONITOR_BASE;
+ len = (ulong)&_end - (ulong)&_start + EXC_OFF_SYS_RESET;
+
+ /*
+ * Subtract specified amount of memory to hide so that it won't
+ * get "touched" at all by U-Boot. By fixing up gd->ram_size
+ * the Linux kernel should now get passed the now "corrected"
+ * memory size and won't touch it either. This should work
+ * for arch/ppc and arch/powerpc. Only Linux board ports in
+ * arch/powerpc with bootwrapper support, that recalculate the
+ * memory size from the SDRAM controller setup will have to
+ * get fixed.
+ */
+ gd->ram_size -= CFG_MEM_TOP_HIDE;
#ifndef CONFIG_MAX_MEM_MAPPED
#define CONFIG_MAX_MEM_MAPPED (256 << 20)
sc3_read_eeprom();
#endif
-#ifdef CFG_ID_EEPROM
+#if defined (CFG_ID_EEPROM) || defined (CFG_I2C_MAC_OFFSET)
mac_read_from_eeprom();
#endif
/*
- * Copyright (C) 2007
+ * Copyright (C) 2007,2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
}
#endif /* (CONFIG_CMD_IDE) */
+#if defined(CONFIG_PCI)
+static int sh_pci_init(void)
+{
+ pci_init();
+ return 0;
+}
+#endif /* CONFIG_PCI */
+
static int sh_mem_env_init(void)
{
mem_malloc_init();
#if defined(CONFIG_CMD_NAND)
sh_nand_init, /* Flash memory (NAND) init */
#endif
+#if defined(CONFIG_PCI)
+ sh_pci_init, /* PCI Init */
+#endif
devices_init,
console_init_r,
interrupt_init,
iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
- debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
+ debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
+#ifdef CONFIG_BOOTP_DHCP_REQUEST_DELAY
+ udelay(CONFIG_BOOTP_DHCP_REQUEST_DELAY);
+#endif /* CONFIG_BOOTP_DHCP_REQUEST_DELAY */
NetSendPacket(NetTxPacket, pktlen);
}
extern int uec_initialize(int);
extern int bfin_EMAC_initialize(bd_t *);
extern int atstk1000_eth_initialize(bd_t *);
+extern int greth_initialize(bd_t *);
extern int atngw100_eth_initialize(bd_t *);
extern int mcffec_initialize(bd_t*);
extern int mcdmafec_initialize(bd_t*);
#if defined(CONFIG_ATSTK1000)
atstk1000_eth_initialize(bis);
#endif
+#if defined(CONFIG_GRETH)
+ greth_initialize(bis);
+#endif
#if defined(CONFIG_ATNGW100)
atngw100_eth_initialize(bis);
#endif
projects / platform / kernel / u-boot.git / commitdiff