[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand...

If SETUNE isn't legal, UO can use the NOT of the SETO expansion.

Removes some complex isel patterns. Most of the test changes are
from using XORI instead of SEQZ.

Differential Revision: https://reviews.llvm.org/D92008

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 361ab78..7342c66 100644 (file)
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1726,14 +1726,19 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode(
     unsigned Opc = 0;
     switch (CCCode) {
     default: llvm_unreachable("Don't know how to expand this condition!");
+    case ISD::SETUO:
+        if (TLI.isCondCodeLegal(ISD::SETUNE, OpVT)) {
+          CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;
+          break;
+        }
+        assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&
+               "If SETUE is expanded, SETOEQ or SETUNE must be legal!");
+        NeedInvert = true;
+        LLVM_FALLTHROUGH;
     case ISD::SETO:
         assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
             && "If SETO is expanded, SETOEQ must be legal!");
         CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
-    case ISD::SETUO:
-        assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
-            && "If SETUO is expanded, SETUNE must be legal!");
-        CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;  break;
     case ISD::SETOEQ:
     case ISD::SETOGT:
     case ISD::SETOGE:

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c58d447..78909b2 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -246,7 +246,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   ISD::CondCode FPCCToExpand[] = {
       ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
       ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
-      ISD::SETGE,  ISD::SETNE};
+      ISD::SETGE,  ISD::SETNE,  ISD::SETO,   ISD::SETUO};
 
   ISD::NodeType FPOpToExpand[] = {
       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 182c399..133599e 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -299,23 +299,6 @@ def : PatFpr64Fpr64<setolt, FLT_D>;
 def : PatFpr64Fpr64<setle, FLE_D>;
 def : PatFpr64Fpr64<setole, FLE_D>;
 
-// Define pattern expansions for setcc operations which aren't directly
-// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
-// Legalizer.
-
-def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
-          (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
-               (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
-def : Pat<(seto FPR64:$rs1, FPR64:$rs1),
-          (FEQ_D $rs1, $rs1)>;
-
-def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
-          (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
-                      (FEQ_D FPR64:$rs2, FPR64:$rs2)),
-                 1)>;
-def : Pat<(setuo FPR64:$rs1, FPR64:$rs1),
-          (SLTIU (FEQ_D $rs1, $rs1), 1)>;
-
 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
 
 /// Loads

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 7a069da..4529949 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -355,23 +355,6 @@ def : PatFpr32Fpr32<setolt, FLT_S>;
 def : PatFpr32Fpr32<setle, FLE_S>;
 def : PatFpr32Fpr32<setole, FLE_S>;
 
-// Define pattern expansions for setcc operations which aren't directly
-// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
-// Legalizer.
-
-def : Pat<(seto FPR32:$rs1, FPR32:$rs2),
-          (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
-               (FEQ_S FPR32:$rs2, FPR32:$rs2))>;
-def : Pat<(seto FPR32:$rs1, FPR32:$rs1),
-          (FEQ_S $rs1, $rs1)>;
-
-def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
-          (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
-                      (FEQ_S FPR32:$rs2, FPR32:$rs2)),
-                 1)>;
-def : Pat<(setuo FPR32:$rs1, FPR32:$rs1),
-          (SLTIU (FEQ_S $rs1, $rs1), 1)>;
-
 def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
 
 /// Loads

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 3a94de0..85ebe05 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -313,23 +313,6 @@ def : PatFpr16Fpr16<setolt, FLT_H>;
 def : PatFpr16Fpr16<setle, FLE_H>;
 def : PatFpr16Fpr16<setole, FLE_H>;
 
-// Define pattern expansions for setcc operations which aren't directly
-// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
-// Legalizer.
-
-def : Pat<(seto FPR16:$rs1, FPR16:$rs2),
-          (AND (FEQ_H FPR16:$rs1, FPR16:$rs1),
-               (FEQ_H FPR16:$rs2, FPR16:$rs2))>;
-def : Pat<(seto FPR16:$rs1, FPR16:$rs1),
-          (FEQ_H $rs1, $rs1)>;
-
-def : Pat<(setuo FPR16:$rs1, FPR16:$rs2),
-          (SLTIU (AND (FEQ_H FPR16:$rs1, FPR16:$rs1),
-                      (FEQ_H FPR16:$rs2, FPR16:$rs2)),
-                 1)>;
-def : Pat<(setuo FPR16:$rs1, FPR16:$rs1),
-          (SLTIU (FEQ_H $rs1, $rs1), 1)>;
-
 def Select_FPR16_Using_CC_GPR : SelectCC_rrirr<FPR16, GPR>;
 
 /// Loads

diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
index 3325835..e7cfa8d 100644 (file)
--- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
@@ -421,7 +421,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    feq.d a2, ft1, ft1
 ; RV32IFD-NEXT:    and a1, a2, a1
-; RV32IFD-NEXT:    seqz a1, a1
+; RV32IFD-NEXT:    xori a1, a1, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    bnez a0, .LBB9_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
@@ -441,7 +441,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV64IFD-NEXT:    feq.d a2, ft1, ft1
 ; RV64IFD-NEXT:    and a1, a2, a1
-; RV64IFD-NEXT:    seqz a1, a1
+; RV64IFD-NEXT:    xori a1, a1, 1
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    bnez a0, .LBB9_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
@@ -699,8 +699,8 @@ define void @br_fcmp_uno(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    bnez a0, .LBB15_2
+; RV32IFD-NEXT:    addi a1, zero, 1
+; RV32IFD-NEXT:    bne a0, a1, .LBB15_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
@@ -717,8 +717,8 @@ define void @br_fcmp_uno(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    seqz a0, a0
-; RV64IFD-NEXT:    bnez a0, .LBB15_2
+; RV64IFD-NEXT:    addi a1, zero, 1
+; RV64IFD-NEXT:    bne a0, a1, .LBB15_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
 ; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IFD-NEXT:    addi sp, sp, 16

diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 2887522..0613dc6 100644 (file)
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -222,7 +222,7 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    feq.d a2, ft1, ft1
 ; RV32IFD-NEXT:    and a1, a2, a1
-; RV32IFD-NEXT:    seqz a1, a1
+; RV32IFD-NEXT:    xori a1, a1, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
@@ -235,7 +235,7 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV64IFD-NEXT:    feq.d a2, ft1, ft1
 ; RV64IFD-NEXT:    and a1, a2, a1
-; RV64IFD-NEXT:    seqz a1, a1
+; RV64IFD-NEXT:    xori a1, a1, 1
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = fcmp ueq double %a, %b
@@ -391,7 +391,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
@@ -402,7 +402,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    seqz a0, a0
+; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
   %1 = fcmp uno double %a, %b
   %2 = zext i1 %1 to i32

diff --git a/llvm/test/CodeGen/RISCV/double-isnan.ll b/llvm/test/CodeGen/RISCV/double-isnan.ll
index 0258ab5..4729ca2 100644 (file)
--- a/llvm/test/CodeGen/RISCV/double-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/double-isnan.ll
@@ -8,13 +8,13 @@ define zeroext i1 @double_is_nan(double %a) nounwind {
 ; RV32IFD-LABEL: double_is_nan:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: double_is_nan:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    seqz a0, a0
+; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    ret
   %1 = fcmp uno double %a, 0.000000e+00
   ret i1 %1

diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 12789c0..3177175 100644 (file)
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -308,7 +308,7 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    feq.d a2, ft1, ft1
 ; RV32IFD-NEXT:    and a1, a2, a1
-; RV32IFD-NEXT:    seqz a1, a1
+; RV32IFD-NEXT:    xori a1, a1, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    bnez a0, .LBB8_2
 ; RV32IFD-NEXT:  # %bb.1:
@@ -328,7 +328,7 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a1, ft1, ft1
 ; RV64IFD-NEXT:    feq.d a2, ft0, ft0
 ; RV64IFD-NEXT:    and a1, a2, a1
-; RV64IFD-NEXT:    seqz a1, a1
+; RV64IFD-NEXT:    xori a1, a1, 1
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    bnez a0, .LBB8_2
 ; RV64IFD-NEXT:  # %bb.1:
@@ -550,7 +550,7 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
 ; RV32IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV32IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    bnez a0, .LBB14_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fmv.d ft0, ft1
@@ -568,7 +568,7 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
 ; RV64IFD-NEXT:    feq.d a0, ft1, ft1
 ; RV64IFD-NEXT:    feq.d a1, ft0, ft0
 ; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    seqz a0, a0
+; RV64IFD-NEXT:    xori a0, a0, 1
 ; RV64IFD-NEXT:    bnez a0, .LBB14_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fmv.d ft0, ft1

diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
index e30f930..b4a2783 100644 (file)
--- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -386,7 +386,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a1, ft0, ft0
 ; RV32IF-NEXT:    feq.s a2, ft1, ft1
 ; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    bnez a0, .LBB9_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
@@ -406,7 +406,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
 ; RV64IF-NEXT:    feq.s a2, ft1, ft1
 ; RV64IF-NEXT:    and a1, a2, a1
-; RV64IF-NEXT:    seqz a1, a1
+; RV64IF-NEXT:    xori a1, a1, 1
 ; RV64IF-NEXT:    or a0, a0, a1
 ; RV64IF-NEXT:    bnez a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
@@ -640,8 +640,8 @@ define void @br_fcmp_uno(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a0, ft1, ft1
 ; RV32IF-NEXT:    feq.s a1, ft0, ft0
 ; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    bnez a0, .LBB15_2
+; RV32IF-NEXT:    addi a1, zero, 1
+; RV32IF-NEXT:    bne a0, a1, .LBB15_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
@@ -658,8 +658,8 @@ define void @br_fcmp_uno(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a0, ft1, ft1
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
 ; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    seqz a0, a0
-; RV64IF-NEXT:    bnez a0, .LBB15_2
+; RV64IF-NEXT:    addi a1, zero, 1
+; RV64IF-NEXT:    bne a0, a1, .LBB15_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16

diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
index 3a44020..06dbb36 100644 (file)
--- a/llvm/test/CodeGen/RISCV/float-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -175,7 +175,7 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a1, ft0, ft0
 ; RV32IF-NEXT:    feq.s a2, ft1, ft1
 ; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
@@ -187,7 +187,7 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
 ; RV64IF-NEXT:    feq.s a2, ft1, ft1
 ; RV64IF-NEXT:    and a1, a2, a1
-; RV64IF-NEXT:    seqz a1, a1
+; RV64IF-NEXT:    xori a1, a1, 1
 ; RV64IF-NEXT:    or a0, a0, a1
 ; RV64IF-NEXT:    ret
   %1 = fcmp ueq float %a, %b
@@ -308,7 +308,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a0, ft1, ft1
 ; RV32IF-NEXT:    feq.s a1, ft0, ft0
 ; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcmp_uno:
@@ -318,7 +318,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a0, ft1, ft1
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
 ; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32

diff --git a/llvm/test/CodeGen/RISCV/float-isnan.ll b/llvm/test/CodeGen/RISCV/float-isnan.ll
index 211783d..c357f4f 100644 (file)
--- a/llvm/test/CodeGen/RISCV/float-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/float-isnan.ll
@@ -8,13 +8,13 @@ define zeroext i1 @float_is_nan(float %a) nounwind {
 ; RV32IF-LABEL: float_is_nan:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_is_nan:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
   %1 = fcmp uno float %a, 0.000000e+00
   ret i1 %1

diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 142e4f8..33d1d16 100644 (file)
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -246,7 +246,7 @@ define float @select_fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a1, ft1, ft1
 ; RV32IF-NEXT:    feq.s a2, ft0, ft0
 ; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    xori a1, a1, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    bnez a0, .LBB8_2
 ; RV32IF-NEXT:  # %bb.1:
@@ -263,7 +263,7 @@ define float @select_fcmp_ueq(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a1, ft1, ft1
 ; RV64IF-NEXT:    feq.s a2, ft0, ft0
 ; RV64IF-NEXT:    and a1, a2, a1
-; RV64IF-NEXT:    seqz a1, a1
+; RV64IF-NEXT:    xori a1, a1, 1
 ; RV64IF-NEXT:    or a0, a0, a1
 ; RV64IF-NEXT:    bnez a0, .LBB8_2
 ; RV64IF-NEXT:  # %bb.1:
@@ -440,7 +440,7 @@ define float @select_fcmp_uno(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a0, ft1, ft1
 ; RV32IF-NEXT:    feq.s a1, ft0, ft0
 ; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    bnez a0, .LBB14_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s ft0, ft1
@@ -455,7 +455,7 @@ define float @select_fcmp_uno(float %a, float %b) nounwind {
 ; RV64IF-NEXT:    feq.s a0, ft1, ft1
 ; RV64IF-NEXT:    feq.s a1, ft0, ft0
 ; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    bnez a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s ft0, ft1

diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
index c031567..f0c5ad4 100644 (file)
--- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll
@@ -352,7 +352,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV32IZFH-NEXT:    and a1, a2, a1
-; RV32IZFH-NEXT:    seqz a1, a1
+; RV32IZFH-NEXT:    xori a1, a1, 1
 ; RV32IZFH-NEXT:    or a0, a0, a1
 ; RV32IZFH-NEXT:    bnez a0, .LBB9_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
@@ -370,7 +370,7 @@ define void @br_fcmp_ueq(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV64IZFH-NEXT:    and a1, a2, a1
-; RV64IZFH-NEXT:    seqz a1, a1
+; RV64IZFH-NEXT:    xori a1, a1, 1
 ; RV64IZFH-NEXT:    or a0, a0, a1
 ; RV64IZFH-NEXT:    bnez a0, .LBB9_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
@@ -582,8 +582,8 @@ define void @br_fcmp_uno(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    seqz a0, a0
-; RV32IZFH-NEXT:    bnez a0, .LBB15_2
+; RV32IZFH-NEXT:    addi a1, zero, 1
+; RV32IZFH-NEXT:    bne a0, a1, .LBB15_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
@@ -598,8 +598,8 @@ define void @br_fcmp_uno(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    seqz a0, a0
-; RV64IZFH-NEXT:    bnez a0, .LBB15_2
+; RV64IZFH-NEXT:    addi a1, zero, 1
+; RV64IZFH-NEXT:    bne a0, a1, .LBB15_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16

diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll
index e2dcbd3..4d57047 100644 (file)
--- a/llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -145,7 +145,7 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV32IZFH-NEXT:    and a1, a2, a1
-; RV32IZFH-NEXT:    seqz a1, a1
+; RV32IZFH-NEXT:    xori a1, a1, 1
 ; RV32IZFH-NEXT:    or a0, a0, a1
 ; RV32IZFH-NEXT:    ret
 ;
@@ -155,7 +155,7 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV64IZFH-NEXT:    and a1, a2, a1
-; RV64IZFH-NEXT:    seqz a1, a1
+; RV64IZFH-NEXT:    xori a1, a1, 1
 ; RV64IZFH-NEXT:    or a0, a0, a1
 ; RV64IZFH-NEXT:    ret
   %1 = fcmp ueq half %a, %b
@@ -254,7 +254,7 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    seqz a0, a0
+; RV32IZFH-NEXT:    xori a0, a0, 1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcmp_uno:
@@ -262,7 +262,7 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    seqz a0, a0
+; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = zext i1 %1 to i32

diff --git a/llvm/test/CodeGen/RISCV/half-isnan.ll b/llvm/test/CodeGen/RISCV/half-isnan.ll
index 46c7e54..a68d4c4 100644 (file)
--- a/llvm/test/CodeGen/RISCV/half-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/half-isnan.ll
@@ -8,13 +8,13 @@ define zeroext i1 @half_is_nan(half %a) nounwind {
 ; RV32IZFH-LABEL: half_is_nan:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    seqz a0, a0
+; RV32IZFH-NEXT:    xori a0, a0, 1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: half_is_nan:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    seqz a0, a0
+; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    ret
   %1 = fcmp uno half %a, 0.000000e+00
   ret i1 %1

diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index a1b2ef1..1ef85f1 100644 (file)
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -202,7 +202,7 @@ define half @select_fcmp_ueq(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV32IZFH-NEXT:    and a1, a2, a1
-; RV32IZFH-NEXT:    seqz a1, a1
+; RV32IZFH-NEXT:    xori a1, a1, 1
 ; RV32IZFH-NEXT:    or a0, a0, a1
 ; RV32IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV32IZFH-NEXT:  # %bb.1:
@@ -216,7 +216,7 @@ define half @select_fcmp_ueq(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a1, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a2, fa0, fa0
 ; RV64IZFH-NEXT:    and a1, a2, a1
-; RV64IZFH-NEXT:    seqz a1, a1
+; RV64IZFH-NEXT:    xori a1, a1, 1
 ; RV64IZFH-NEXT:    or a0, a0, a1
 ; RV64IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV64IZFH-NEXT:  # %bb.1:
@@ -360,7 +360,7 @@ define half @select_fcmp_uno(half %a, half %b) nounwind {
 ; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    seqz a0, a0
+; RV32IZFH-NEXT:    xori a0, a0, 1
 ; RV32IZFH-NEXT:    bnez a0, .LBB14_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fmv.h fa0, fa1
@@ -372,7 +372,7 @@ define half @select_fcmp_uno(half %a, half %b) nounwind {
 ; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    seqz a0, a0
+; RV64IZFH-NEXT:    xori a0, a0, 1
 ; RV64IZFH-NEXT:    bnez a0, .LBB14_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fmv.h fa0, fa1