si_log_compute_state(sctx, sctx->log);
}
+ /* Mark displayable DCC as dirty for bound images. */
+ unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
+ BITFIELD_MASK(program->sel.info.base.num_images);
+ while (display_dcc_store_mask) {
+ struct si_texture *tex = (struct si_texture *)
+ sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
+
+ si_mark_display_dcc_dirty(sctx, tex);
+ }
+
+ /* TODO: Bindless images don't set displayable_dcc_dirty after image stores. */
+
sctx->compute_is_busy = true;
sctx->num_compute_calls++;
memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
images->enabled_mask &= ~(1u << slot);
+ images->display_dcc_store_mask &= ~(1u << slot);
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
}
}
if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
images->needs_color_decompress_mask &= ~(1 << slot);
+ images->display_dcc_store_mask &= ~(1u << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
struct si_texture *tex = (struct si_texture *)res;
images->needs_color_decompress_mask &= ~(1 << slot);
}
+ if (tex->surface.display_dcc_offset && view->access & PIPE_IMAGE_ACCESS_WRITE)
+ images->display_dcc_store_mask |= 1u << slot;
+ else
+ images->display_dcc_store_mask &= ~(1u << slot);
+
if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
ctx->need_check_render_feedback = true;
}