u16 offset;
u8 bitpos;
+ offset = rz_mtu3_get_tstr_offset(ch);
+ bitpos = rz_mtu3_get_tstr_bit_pos(ch);
+
/* start stop register shared by multiple timer channels */
raw_spin_lock_irqsave(&priv->lock, flags);
- offset = rz_mtu3_get_tstr_offset(ch);
- bitpos = rz_mtu3_get_tstr_bit_pos(ch);
tstr = rz_mtu3_shared_reg_read(ch, offset);
__assign_bit(bitpos, &tstr, start);
rz_mtu3_shared_reg_write(ch, offset, tstr);
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
unsigned long flags, tstr;
- bool ret = false;
u16 offset;
u8 bitpos;
- /* start stop register shared by multiple timer channels */
- raw_spin_lock_irqsave(&priv->lock, flags);
-
offset = rz_mtu3_get_tstr_offset(ch);
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
- tstr = rz_mtu3_shared_reg_read(ch, offset);
- ret = tstr & BIT(bitpos);
+ /* start stop register shared by multiple timer channels */
+ raw_spin_lock_irqsave(&priv->lock, flags);
+ tstr = rz_mtu3_shared_reg_read(ch, offset);
raw_spin_unlock_irqrestore(&priv->lock, flags);
- return ret;
+ return tstr & BIT(bitpos);
}
EXPORT_SYMBOL_GPL(rz_mtu3_is_enabled);