clk: starfive: jh7110-sys: Do not disable vdec clocks
authorSeung-Woo Kim <sw0312.kim@samsung.com>
Mon, 5 Feb 2024 07:21:53 +0000 (16:21 +0900)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 19 Feb 2024 00:14:02 +0000 (09:14 +0900)
As like vf2 v6.1, do not disable vdec clocks by setting as
CLK_IGNORE_UNUSED to use vdec hw codec.

Change-Id: I98ebc1bd2bc92fb3d0dd634305ac7e31ddf3be1e
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
drivers/clk/starfive/clk-starfive-jh7110-sys.c

index b6b9e96..750666d 100644 (file)
@@ -143,8 +143,8 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
        JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
        JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
        JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
-       JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
-       JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
+       JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", CLK_IGNORE_UNUSED, JH7110_SYSCLK_JPEGC_AXI),
+       JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", CLK_IGNORE_UNUSED, JH7110_SYSCLK_VDEC_AXI),
        JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
        /* venc */
        JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),