case POWERPC_MMU_32B:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
- case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_REAL_4xx:
case POWERPC_MMU_BOOKE:
ret = mmu40x_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "601 MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type);
env->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
else
env->spr[SPR_DSISR] = 0x40000000;
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- return -1;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- break;
case POWERPC_MMU_32B:
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
- case POWERPC_MMU_601:
- /* XXX: TODO */
- cpu_abort(env, "MMU model not implemented\n");
- break;
case POWERPC_MMU_32B:
/* tlbie invalidate TLBs for all segments */
addr &= ~((target_ulong)-1 << 28);
#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
-//#define POWERPC_MMU_601 (POWERPC_MMU_601)
+#define POWERPC_MMU_601 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
case POWERPC_MMU_32B:
mmu_model = "PowerPC 32";
break;
- case POWERPC_MMU_601:
- mmu_model = "PowerPC 601";
- break;
case POWERPC_MMU_SOFT_6xx:
mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
break;