{
struct mvebu_reset_data *data = dev_get_priv(dev);
- data->base = (void *)dev_read_addr(dev);
- if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
+ data->base = dev_read_addr_ptr(dev);
+ if (!data->base)
return -EINVAL;
return 0;
struct udevice *bus;
- i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+ i2c_bus->regs = dev_read_addr_ptr(dev);
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
The dev_read\_...() interface is more convenient and works with both the
#endif
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
- uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
+ uc_priv->mmio_base = dev_read_addr_ptr(dev);
/* initialize adapter */
ret = ahci_host_init(uc_priv);
{
u32 tag[3] = { 0, 0, 0 };
u32 saved_reg, prefetch;
- struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+ struct pl310_regs *regs = dev_read_addr_ptr(dev);
/* Disable the L2 Cache */
clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs;
- regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
+ regs = dev_read_addr_ptr(dev);
plat->regs = regs;
plat->iprefetch = -EINVAL;
debug("probe: gpios = %d, bit-count = %d\n",
uc_priv->gpio_count, priv->bitcount);
- priv->regs = (u32 __iomem *)dev_read_addr(dev);
+ priv->regs = dev_read_addr_ptr(dev);
uc_priv->bank_name = "sgpio";
sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
if (len < 0)
return len;
bank_count = len / 3 / sizeof(u32);
- ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
- if ((ulong)ctlr == FDT_ADDR_T_NONE)
+ ctlr = dev_read_addr_ptr(parent);
+ if (!ctlr)
return -EINVAL;
}
#endif
struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int is_dual;
- plat->regs = (struct gpio_regs *)dev_read_addr(dev);
+ plat->regs = dev_read_addr_ptr(dev);
plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
struct clk clk;
int ret;
- i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
+ i2c_bus->regs = dev_read_addr_ptr(dev);
if (!i2c_bus->regs)
- return -ENOMEM;
+ return -EINVAL;
if (pdata)
i2c_bus->quirks = pdata->quirks;
i2c_bus->id = dev_seq(dev);
i2c_bus->type = dev_get_driver_data(dev);
- i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
- if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+ i2c_bus->regs = dev_read_addr_ptr(dev);
+ if (!i2c_bus->regs) {
debug("%s: Cannot get regs address\n", __func__);
return -EINVAL;
}
int ret;
host->name = dev->name;
- host->ioaddr = (void *)dev_read_addr(dev);
+ host->ioaddr = dev_read_addr_ptr(dev);
plat->non_removable = dev_read_bool(dev, "non-removable");
if (plat->flags & DLL_PRESENT) {
struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
- plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+ plat->reg_base = dev_read_addr_ptr(dev);
cfg->f_min = 200000;
cfg->f_max = 25000000;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
struct mmc *mmc;
struct blk_desc *bdesc;
- priv->base_addr = (void *)dev_read_addr(dev);
+ priv->base_addr = dev_read_addr_ptr(dev);
cfg = &plat->cfg;
cfg->name = "PITON MMC";
cfg->host_caps = MMC_MODE_8BIT;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- priv->reg = (void *)dev_read_addr(dev);
+ priv->reg = dev_read_addr_ptr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
arasan_dt_parse_clk_phases(dev);
#endif
- priv->host->ioaddr = (void *)dev_read_addr(dev);
- if (IS_ERR(priv->host->ioaddr))
- return PTR_ERR(priv->host->ioaddr);
+ priv->host->ioaddr = dev_read_addr_ptr(dev);
+ if (!priv->host->ioaddr)
+ return -EINVAL;
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
ofnode child;
int err = -1;
- info->reg = (struct nand_regs *)dev_read_addr(dev);
+ info->reg = dev_read_addr_ptr(dev);
mtd = nand_to_mtd(nand_chip);
nand_set_controller_data(nand_chip, &arasan->nand_ctrl);
{
int ecc_strength;
- info->reg = (struct nand_ctlr *)dev_read_addr(dev);
+ info->reg = dev_read_addr_ptr(dev);
info->dma_glb = dev_read_addr_index_ptr(dev, 1);
info->dma_nand = dev_read_addr_index_ptr(dev, 2);
info->config.enabled = dev_read_enabled(dev);
ofnode child;
int err;
- nfc->regs = (void *)dev_read_addr(dev);
+ nfc->regs = dev_read_addr_ptr(dev);
nfc->send_clk = devm_clk_get(dev, "send");
if (IS_ERR(nfc->send_clk))
{
int err;
- config->reg = (struct nand_ctlr *)dev_read_addr(dev);
+ config->reg = dev_read_addr_ptr(dev);
config->enabled = dev_read_enabled(dev);
config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
int ondie_ecc_enabled = 0;
int is_16bit_bw;
- smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
+ smc->reg = dev_read_addr_ptr(dev);
of_nand = dev_read_subnode(dev, "nand-controller@0,0");
if (!ofnode_valid(of_nand)) {
of_nand = dev_read_subnode(dev, "flash@e1000000");
{
struct mvmdio_priv *priv = dev_get_priv(dev);
- priv->mdio_base = (void *)dev_read_addr(dev);
+ priv->mdio_base = dev_read_addr_ptr(dev);
priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
return 0;
u32 num = 0;
int ret = -ENODEV;
- priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
+ priv->base = dev_read_addr_ptr(dev);
base = (fdt_size_t)priv->base;
/*
struct pcie_advk *pcie = dev_get_priv(dev);
/* Get the register base address */
- pcie->base = (void *)dev_read_addr(dev);
- if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
+ pcie->base = dev_read_addr_ptr(dev);
+ if (!pcie->base)
return -EINVAL;
return 0;
return ret;
}
- priv->regs = (void __iomem *)dev_read_addr(dev);
- if (IS_ERR(priv->regs))
- return PTR_ERR(priv->regs);
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
return 0;
}
struct hsphy_priv *priv = dev_get_priv(dev);
int ret;
- priv->base = (void *)dev_read_addr(dev);
- if ((ulong)priv->base == FDT_ADDR_T_NONE)
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
return -EINVAL;
ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
struct ssphy_priv *priv = dev_get_priv(dev);
int ret;
- priv->base = (void *)dev_read_addr(dev);
- if ((ulong)priv->base == FDT_ADDR_T_NONE)
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
return -EINVAL;
ret = ssphy_clk_init(dev, priv);
struct udevice *syscon;
int ret;
- priv->mmio = (void __iomem *)dev_read_addr(dev);
- if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
+ priv->mmio = dev_read_addr_ptr(dev);
+ if (!priv->mmio)
return -EINVAL;
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
unsigned int reg;
int index, ret;
- priv->reg_base = (void __iomem *)dev_read_addr(dev);
- if (IS_ERR(priv->reg_base))
- return PTR_ERR(priv->reg_base);
+ priv->reg_base = dev_read_addr_ptr(dev);
+ if (!priv->reg_base)
+ return -EINVAL;
ret = dev_read_u32_index(dev, "reg", 1, ®);
if (ret) {
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
+ priv->regs = dev_read_addr_ptr(dev);
return 0;
}
{
struct zynq_uart_plat *plat = dev_get_plat(dev);
- plat->regs = (struct uart_zynq *)dev_read_addr(dev);
- if (IS_ERR(plat->regs))
- return PTR_ERR(plat->regs);
+ plat->regs = dev_read_addr_ptr(dev);
+ if (!plat->regs)
+ return -EINVAL;
return 0;
}
struct clk clk;
int ret;
- priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+ priv->spi = dev_read_addr_ptr(dev);
ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
debug("%s: loaded, priv %p\n", __func__, priv);
- priv->regs = (void __iomem *)dev_read_addr(bus);
+ priv->regs = dev_read_addr_ptr(bus);
priv->deactivate_delay_us =
dev_read_u32_default(bus, "spi-deactivate-delay", 0);
{
struct sh_qspi_slave *plat = dev_get_plat(dev);
- plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
+ plat->regs = dev_read_addr_ptr(dev);
return 0;
}
{
struct mxic_spi_priv *priv = dev_get_priv(bus);
- priv->regs = (void *)dev_read_addr(bus);
+ priv->regs = dev_read_addr_ptr(bus);
priv->send_clk = devm_clk_get(bus, "send_clk");
if (IS_ERR(priv->send_clk))
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs;
- regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+ regs = priv->regs = dev_read_addr_ptr(bus);
priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
writel(SPISSR_RESET_VALUE, ®s->srr);
hba->dev = ufs_dev;
hba->ops = hba_ops;
- hba->mmio_base = (void *)dev_read_addr(ufs_dev);
+ hba->mmio_base = dev_read_addr_ptr(ufs_dev);
/* Set descriptor lengths to specification defaults */
ufshcd_def_desc_sizes(hba);
{
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+ config->reg = dev_read_addr_ptr(dev);
debug("reg=%p\n", config->reg);
mode = dev_read_string(dev, "dr_mode");
if (mode) {
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
device->host = &dsi->dsi_host;
- dsi->base = (void *)dev_read_addr(device->dev);
- if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
+ dsi->base = dev_read_addr_ptr(device->dev);
+ if (!dsi->base) {
dev_err(device->dev, "dsi dt register address error\n");
return -EINVAL;
}
efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE);
#endif
- priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
+ priv->regs = dev_read_addr_ptr(dev);
/*
* Try all the ports until we find one that works. In practice this
device->dev = dev;
- priv->base = (void *)dev_read_addr(dev);
- if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base) {
dev_err(dev, "dsi dt register address error\n");
return -EINVAL;
}
ulong rate;
int ret;
- priv->regs = (void *)dev_read_addr(dev);
- if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
return ret;
}
- dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+ dc_ctlr = dev_read_addr_ptr(dev);
if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
/* Use the first display controller */
debug("%s\n", __func__);
- disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
+ disp_ctrl = dev_read_addr_ptr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
debug("%s\n", __func__);
/* Use the first display controller */
- disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
+ disp_ctrl = dev_read_addr_ptr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret;
- priv->base = (void *)dev_read_addr(dev);
+ priv->base = dev_read_addr_ptr(dev);
priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
if (IS_ERR(priv->pmc_base))
{
struct tilcdc_priv *priv = dev_get_priv(dev);
- priv->regs = (struct tilcdc_regs *)dev_read_addr(dev);
- if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
dev_err(dev, "failed to get base address\n");
return -EINVAL;
}
{
struct cdns_wdt_priv *priv = dev_get_priv(dev);
- priv->regs = (struct cdns_regs *)dev_read_addr(dev);
- if (IS_ERR(priv->regs))
- return PTR_ERR(priv->regs);
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
priv->rst = dev_read_bool(dev, "reset-on-timeout");
struct sp805_wdt_priv *priv = dev_get_priv(dev);
struct clk clk;
- priv->reg = (void __iomem *)dev_read_addr(dev);
- if (IS_ERR(priv->reg))
- return PTR_ERR(priv->reg);
+ priv->reg = dev_read_addr_ptr(dev);
+ if (!priv->reg)
+ return -EINVAL;
if (!clk_get_by_index(dev, 0, &clk))
priv->clk_rate = clk_get_rate(&clk);
{
struct xlnx_wdt_plat *plat = dev_get_plat(dev);
- plat->regs = (struct watchdog_regs *)dev_read_addr(dev);
- if (IS_ERR(plat->regs))
- return PTR_ERR(plat->regs);
+ plat->regs = dev_read_addr_ptr(dev);
+ if (!plat->regs)
+ return -EINVAL;
plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
0);