arm64: dts: imx8qxp-colibri: Align pin configuration group names with schema

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 75f17a2..f38acff 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -494,7 +494,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                0x06000041
                        IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                0x21
@@ -511,7 +511,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                0x06000041
                        IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                0x21
@@ -554,7 +554,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK              0x06000041      /* SODIMM  47 */
                        IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD              0x21            /* SODIMM 190 */
@@ -566,7 +566,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK              0x06000041      /* SODIMM  47 */
                        IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD              0x21            /* SODIMM 190 */