xilinx: Add CONFIG_DM_ETH_PHY config
authorT Karthik Reddy <t.karthik.reddy@xilinx.com>
Tue, 10 May 2022 11:26:11 +0000 (13:26 +0200)
committerMichal Simek <michal.simek@amd.com>
Fri, 24 Jun 2022 12:11:05 +0000 (14:11 +0200)
Enable CONFIG_DM_ETH_PHY to utilize shared MDIO bus support on all xilinx
platforms.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/965981eb324d13a98aad8bd88eb8b50bc5147a7e.1652181968.git.michal.simek@amd.com
configs/microblaze-generic_defconfig
configs/xilinx_versal_virt_defconfig
configs/xilinx_zynq_virt_defconfig
configs/xilinx_zynqmp_virt_defconfig

index 3142b46..7994110 100644 (file)
@@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
 CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
index 38747ff..c9ae018 100644 (file)
@@ -92,6 +92,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_XILINX_AXIMRMAC=y
index 1f3e6a4..120bc29 100644 (file)
@@ -111,6 +111,7 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_XILINX=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_MII=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ARM_DCC=y
index 3589407..abaebb8 100644 (file)
@@ -160,6 +160,7 @@ CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_XILINX_AXIEMAC=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DM_REGULATOR=y