arm64: dts: qcom: sc7180: Swap order of gpucc and sdhc_2

Devices are supposed to be sorted by unit address.  These two got
swapped when they landed.  Fix.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200331092832.1.Ic361058ca22d7439164ffea11421740462e14272@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index be5cb4a..62faac4 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1295,6 +1295,20 @@
                        };
                };
 
+               gpucc: clock-controller@5090000 {
+                       compatible = "qcom,sc7180-gpucc";
+                       reg = <0 0x05090000 0 0x9000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+                       clock-names = "bi_tcxo",
+                                     "gcc_gpu_gpll0_clk_src",
+                                     "gcc_gpu_gpll0_div_clk_src";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                sdhc_2: sdhci@8804000 {
                        compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
                        reg = <0 0x08804000 0 0x1000>;
@@ -1313,20 +1327,6 @@
                        status = "disabled";
                };
 
-               gpucc: clock-controller@5090000 {
-                       compatible = "qcom,sc7180-gpucc";
-                       reg = <0 0x05090000 0 0x9000>;
-                       clocks = <&rpmhcc RPMH_CXO_CLK>,
-                                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
-                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
-                       clock-names = "bi_tcxo",
-                                     "gcc_gpu_gpll0_clk_src",
-                                     "gcc_gpu_gpll0_div_clk_src";
-                       #clock-cells = <1>;
-                       #reset-cells = <1>;
-                       #power-domain-cells = <1>;
-               };
-
                qspi: spi@88dc000 {
                        compatible = "qcom,qspi-v1";
                        reg = <0 0x088dc000 0 0x600>;