clk: renesas: rzg2l: Fix computation formula

[ Upstream commit a2b23159499efd36b2d63b3c4534075d12ddc97a ]

According to the hardware manual for RZ/G2L
(r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate
is as follows:

    Fout = ((m + k/65536) * Fin) / (p * 2^s)

and k has values in the range [-32768, 32767].  Dividing k by 65536 with
integer arithmetic gives zero all the time, causing slight differences
b/w what has been set vs. what is displayed.  Thus, get rid of this and
decompose the formula before dividing k by 65536.

Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-6-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 917ce62..84767cf 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -43,7 +43,7 @@
 #define GET_SHIFT(val)         ((val >> 12) & 0xff)
 #define GET_WIDTH(val)         ((val >> 8) & 0xf)
 
-#define KDIV(val)              FIELD_GET(GENMASK(31, 16), val)
+#define KDIV(val)              ((s16)FIELD_GET(GENMASK(31, 16), val))
 #define MDIV(val)              FIELD_GET(GENMASK(15, 6), val)
 #define PDIV(val)              FIELD_GET(GENMASK(5, 0), val)
 #define SDIV(val)              FIELD_GET(GENMASK(2, 0), val)
@@ -699,18 +699,18 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
        struct pll_clk *pll_clk = to_pll(hw);
        struct rzg2l_cpg_priv *priv = pll_clk->priv;
        unsigned int val1, val2;
-       unsigned int mult = 1;
-       unsigned int div = 1;
+       u64 rate;
 
        if (pll_clk->type != CLK_TYPE_SAM_PLL)
                return parent_rate;
 
        val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
        val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
-       mult = MDIV(val1) + KDIV(val1) / 65536;
-       div = PDIV(val1) << SDIV(val2);
 
-       return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
+       rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),
+                              16 + SDIV(val2));
+
+       return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1));
 }
 
 static const struct clk_ops rzg2l_cpg_pll_ops = {