drm/amd/display: Disable pipe split for modes with borders

[Why]
For some special timing with border, like DMT 640*480 72Hz,
pipe split can't handle well. Thus, it will be black screen
for these special timing.

[How]
Disable pipe split for these timing with borders as W/A.

Signed-off-by: Dale Zhao <dale.zhao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index afa99f9..fb16739 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2666,6 +2666,23 @@ int dcn20_validate_apply_pipe_split_flags(
        if (plane_count > dc->res_pool->pipe_count / 2)
                avoid_split = true;
 
+       /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+               struct dc_crtc_timing timing;
+
+               if (!pipe->stream)
+                       continue;
+               else {
+                       timing = pipe->stream->timing;
+                       if (timing.h_border_left + timing.h_border_right
+                                       + timing.v_border_top + timing.v_border_bottom > 0) {
+                               avoid_split = true;
+                               break;
+                       }
+               }
+       }
+
        /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
        if (avoid_split) {
                for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {