void si_init_tess_factor_ring(struct si_context *sctx);
bool si_update_gs_ring_buffers(struct si_context *sctx);
bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes);
-unsigned si_calc_inst_pref_size(struct si_shader *shader);
+unsigned si_get_shader_prefetch_size(struct si_shader *shader);
bool si_set_tcs_to_fixed_func_shader(struct si_context *sctx);
/* si_state_draw.cpp */
return max;
}
-unsigned si_calc_inst_pref_size(struct si_shader *shader)
+unsigned si_get_shader_prefetch_size(struct si_shader *shader)
{
/* TODO: Disable for now. */
if (shader->selector->screen->info.gfx_level == GFX11)
if (sscreen->info.gfx_level >= GFX9) {
if (sscreen->info.gfx_level >= GFX11) {
ac_set_reg_cu_en(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
- S_00B404_INST_PREF_SIZE(si_calc_inst_pref_size(shader)) |
+ S_00B404_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)) |
S_00B404_CU_EN(0xffff),
C_00B404_CU_EN, 16, &sscreen->info,
(void (*)(void*, unsigned, uint32_t))si_pm4_set_reg_idx3);
if (sscreen->info.gfx_level >= GFX11) {
shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs =
S_00B204_CU_EN_GFX11(0x1) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64) |
- S_00B204_INST_PREF_SIZE(si_calc_inst_pref_size(shader));
+ S_00B204_INST_PREF_SIZE(si_get_shader_prefetch_size(shader));
} else {
shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs =
S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64);
unsigned cu_mask_ps = gfx103_get_cu_mask_ps(sscreen);
ac_set_reg_cu_en(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
- S_00B004_INST_PREF_SIZE(si_calc_inst_pref_size(shader)) |
+ S_00B004_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)) |
S_00B004_CU_EN(cu_mask_ps >> 16),
C_00B004_CU_EN, 16, &sscreen->info,
(void (*)(void*, unsigned, uint32_t))si_pm4_set_reg_idx3);