vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
&vpm_index);
}
+
+ /* GFXH-1684: VPM writes need to be complete by the end of the shader.
+ */
+ if (c->devinfo->ver >= 40 && c->devinfo->ver <= 41)
+ vir_VPMWT(c);
}
void
add_write_dep(state, &state->last_vpm, n);
break;
+ case V3D_QPU_A_VPMWT:
+ add_read_dep(state, state->last_vpm, n);
+ break;
+
case V3D_QPU_A_MSF:
add_read_dep(state, state->last_tlb, n);
break;
return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
}
+#define VIR_NODST_0(name, vir_inst, op) \
+static inline struct qinst * \
+vir_##name(struct v3d_compile *c) \
+{ \
+ return vir_emit_nondef(c, vir_inst(op, c->undef, \
+ c->undef, c->undef)); \
+}
+
#define VIR_NODST_1(name, vir_inst, op) \
static inline struct qinst * \
vir_##name(struct v3d_compile *c, struct qreg a) \
#define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
#define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
#define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
+#define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)
VIR_A_ALU0(MSF)
VIR_A_ALU0(REVF)
VIR_A_NODST_1(VPMSETUP)
+VIR_A_NODST_0(VPMWT)
VIR_A_ALU2(FCMP)
VIR_A_ALU2(VFMAX)