// In case we have str xA, [xA, #imm], this is two different uses
// of xA and we cannot fold, otherwise the xA stored may be wrong,
// even if #imm == 0.
- return MI.getOperandNo(&MO) == 1 &&
+ return MO.getOperandNo() == 1 &&
MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
}
}
// TODO: Scan implicit defs too?
for (const auto &Op : MI.defs()) {
unsigned Latency = SchedModel.computeOperandLatency(
- &MI, MI.getOperandNo(&Op), nullptr, 0);
+ &MI, Op.getOperandNo(), nullptr, 0);
for (MCRegUnitIterator UI(Op.getReg(), TRI); UI.isValid(); ++UI)
State[*UI] = DelayInfo(Type, Latency);
}
MaxWaitStates);
int NeedWaitStates = MFMAWritesAGPROverlappedSrcABWaitStates;
int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
- int OpNo = MI->getOperandNo(&Op);
+ int OpNo = Op.getOperandNo();
if (OpNo == SrcCIdx) {
NeedWaitStates = MFMAWritesAGPROverlappedSrcCWaitStates;
} else if (Opc == AMDGPU::V_ACCVGPR_READ_B32_e64) {
if (NumWaitStates == std::numeric_limits<int>::max())
continue;
- int OpNo = MI->getOperandNo(&Use);
+ int OpNo = Use.getOperandNo();
unsigned Opc1 = MI1->getOpcode();
int NeedWaitStates = 0;
if (OpNo == SrcCIdx) {
UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END)
return false;
- unsigned OpIdx = UseMI->getOperandNo(&MO);
+ unsigned OpIdx = MO.getOperandNo();
if (OpIdx >= UseMI->getDesc().getNumOperands() ||
!TII->isOperandLegal(*UseMI, OpIdx, &Src))
return false;
TRI->getEquivalentSGPRClass(SrcRC);
Register NewDst = MRI->createVirtualRegister(DestRC);
MachineBasicBlock *BlockToInsertCopy =
- MI.isPHI() ? MI.getOperand(MI.getOperandNo(&MO) + 1).getMBB()
+ MI.isPHI() ? MI.getOperand(MO.getOperandNo() + 1).getMBB()
: MBB;
MachineBasicBlock::iterator PointToInsertCopy =
MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I;
const MachineOperand &UseMO,
const MachineOperand &DefMO) const {
assert(UseMO.getParent() == &MI);
- int OpIdx = MI.getOperandNo(&UseMO);
+ int OpIdx = UseMO.getOperandNo();
if (OpIdx >= MI.getDesc().NumOperands)
return false;
}
bool isInlineConstant(const MachineOperand &MO) const {
- const MachineInstr *Parent = MO.getParent();
- return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
+ return isInlineConstant(*MO.getParent(), MO.getOperandNo());
}
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))
continue;
- unsigned I = MI.getOperandNo(&Op);
+ unsigned I = Op.getOperandNo();
if (Desc.operands()[I].RegClass == -1 ||
!TRI->isVSSuperClass(TRI->getRegClass(Desc.operands()[I].RegClass)))
continue;
bool SIShrinkInstructions::isKImmOperand(const MachineOperand &Src) const {
return isInt<16>(Src.getImm()) &&
- !TII->isInlineConstant(*Src.getParent(),
- Src.getParent()->getOperandNo(&Src));
+ !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo());
}
bool SIShrinkInstructions::isKUImmOperand(const MachineOperand &Src) const {
return isUInt<16>(Src.getImm()) &&
- !TII->isInlineConstant(*Src.getParent(),
- Src.getParent()->getOperandNo(&Src));
+ !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo());
}
bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src,
assert(Register::isVirtualRegister(VReg) && "Expected virtual register!");
- for (auto it = MRI->use_nodbg_begin(VReg), end = MRI->use_nodbg_end();
- it != end; ++it) {
- MachineInstr *User = it->getParent();
+ for (const MachineOperand &Use : MRI->use_nodbg_operands(VReg)) {
+ const MachineInstr *User = Use.getParent();
if (User->isPHI()) {
- unsigned BBOperandIdx = User->getOperandNo(&*it) + 1;
+ unsigned BBOperandIdx = Use.getOperandNo() + 1;
MachineBasicBlock *MBB = User->getOperand(BBOperandIdx).getMBB();
if (MBB->empty()) {
const MachineBasicBlock *InstBB = MI->getParent();
continue;
// Skip the lr predicate reg
int PIdx = llvm::findFirstVPTPredOperandIdx(MI);
- if (PIdx != -1 && (int)MI.getOperandNo(&MO) == PIdx + 2)
+ if (PIdx != -1 && (int)MO.getOperandNo() == PIdx + 2)
continue;
// Check that this instruction will produce zeros in its false lanes:
const MachineInstr *MI = MO.getParent();
const unsigned NameIndices = M68kInstrNameIndices[MI->getOpcode()];
StringRef InstrName(&M68kInstrNameData[NameIndices]);
- const unsigned OperandNo = MI->getOperandNo(&MO);
+ const unsigned OperandNo = MO.getOperandNo();
// If this machine operand is the 2nd operand, then check
// whether the instruction has destination addressing mode 'k'.
for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
const MachineInstr *UserMI = UserOp.getParent();
- unsigned OpIdx = UserMI->getOperandNo(&UserOp);
+ unsigned OpIdx = UserOp.getOperandNo();
switch (UserMI->getOpcode()) {
default:
for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
const MachineInstr &MI = *MO.getParent();
- unsigned OpIdx = MI.getOperandNo(&MO);
+ unsigned OpIdx = MO.getOperandNo();
bool NeedGPRC;
if (isCompressible(MI, NeedGPRC)) {
if (OpIdx == 0 && MI.getOperand(1).isReg()) {
unsigned LocalId = getLocalId(Reg2Local, MFI, CurLocal, OldReg);
// If this register operand is tied to another operand, we can't
// change it to an immediate. Untie it first.
- MI.untieRegOperand(MI.getOperandNo(&MO));
+ MI.untieRegOperand(MO.getOperandNo());
MO.ChangeToImmediate(LocalId);
continue;
}
if (MI.isInlineAsm()) {
unsigned LocalId = getLocalId(Reg2Local, MFI, CurLocal, OldReg);
// Untie it first if this reg operand is tied to another operand.
- MI.untieRegOperand(MI.getOperandNo(&MO));
+ MI.untieRegOperand(MO.getOperandNo());
MO.ChangeToImmediate(LocalId);
continue;
}