hdmirx: modify recovery flow for aud_pll error [1/1]
authorLei Yang <lei.yang@amlogic.com>
Sun, 29 Sep 2019 07:18:06 +0000 (15:18 +0800)
committerTao Zeng <tao.zeng@amlogic.com>
Wed, 9 Oct 2019 11:15:52 +0000 (04:15 -0700)
PD#SWPL-14776

Problem:
aud pll is zero. need to reset aud bandgap

Solution:
modify related recovery flow

Verify:
TXLX

Change-Id: If8ba596cb7bec81165a0b2f80aa388579cc68411
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c

index 0140204..8d5b1d8 100644 (file)
@@ -312,8 +312,7 @@ int hdmirx_dec_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
        devp->param.port = port;
 
        /* should enable the adc ref signal for audio pll */
-       vdac_enable(1, 0x10);
-
+       /* vdac_enable(1, 0x10); */
        hdmirx_open_port(port);
        rx.open_fg = 1;
        rx_pr("%s port:%x ok nosignal:%d\n", __func__, port, rx.no_signal);
index f492c77..3627135 100644 (file)
@@ -34,7 +34,7 @@
 #include "hdmi_rx_edid.h"
 
 
-#define RX_VER0 "ver.2019-09-26"
+#define RX_VER0 "ver.2019-09-27"
 /*
  *
  *
@@ -366,6 +366,7 @@ struct aud_info_s {
        int real_channel_num;
        int real_sample_size;
        int real_sr;
+       u32 aud_clk;
 };
 
 struct phy_sts {
index 3afba29..c1fc51b 100644 (file)
@@ -972,6 +972,8 @@ void rx_get_audinfo(struct aud_info_s *audio_info)
                        audio_info->n/128;
        } else
                audio_info->arc = 0;
+
+       audio_info->aud_clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
 }
 
 /*
@@ -2399,9 +2401,26 @@ void hdmirx_load_firm_reset(int type)
  */
 void rx_audio_bandgap_rst(void)
 {
-       vdac_enable(0, 0x10);
-       udelay(20);
-       vdac_enable(1, 0x10);
+       if (rx.chip_id >= CHIP_ID_TL1)
+               return;
+
+       wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 1);
+       udelay(10);
+       wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 0);
+       if (log_level & AUDIO_LOG)
+               rx_pr("%s\n", __func__);
+}
+
+void rx_audio_bandgap_en(void)
+{
+       if (rx.chip_id >= CHIP_ID_TL1)
+               return;
+
+       wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(9), 1);
+       wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 1);
+       udelay(10);
+       wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 0);
+
        if (log_level & AUDIO_LOG)
                rx_pr("%s\n", __func__);
 }
@@ -2538,7 +2557,7 @@ bool is_afifo_error(void)
 bool is_aud_pll_error(void)
 {
        bool ret = true;
-       int32_t clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
+       u32 clk = rx.aud_info.aud_clk;
        int32_t aud_128fs = rx.aud_info.real_sr * 128;
        int32_t aud_512fs = rx.aud_info.real_sr * 512;
 
@@ -2595,6 +2614,7 @@ void rx_aud_pll_ctl(bool en)
                }
        } else {
                if (en) {
+                       rx_audio_bandgap_en();
                        tmp = hdmirx_rd_phy(PHY_MAINFSM_STATUS1);
                        wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000);
                        /* audio pll div depends on input freq */
@@ -3332,7 +3352,7 @@ int rx_get_aud_pll_err_sts(void)
 {
        int ret = E_AUDPLL_OK;
        int32_t req_clk = rx_measure_clock(MEASURE_CLK_MPLL);
-       int32_t aud_clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
+       u32 aud_clk = rx.aud_info.aud_clk;
        uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
        uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
 
index 18c7047..f3c6359 100644 (file)
@@ -53,7 +53,7 @@
 /* TXLX */
 /* unified_register.h by wujun */
 #define HHI_AUDPLL_CLK_OUT_CNTL (0x8c << 2)
-
+#define HHI_VDAC_CNTL0_TXLX            (0xBD * 4)
 #define PREG_PAD_GPIO0_EN_N            (0x0c * 4)
 #define PREG_PAD_GPIO0_O               (0x0d * 4)
 #define PREG_PAD_GPIO0_I               (0x0e * 4)
@@ -1221,8 +1221,8 @@ extern void cec_hw_reset(unsigned int cec_sel);
 extern void rx_force_hpd_cfg(uint8_t hpd_level);
 extern void rx_force_rxsense_cfg(uint8_t level);
 extern void rx_force_hpd_rxsense_cfg(uint8_t level);
-extern void rx_audio_bandgap_rst(void);
-extern void rx_audio_bandgap_rst(void);
+void rx_audio_bandgap_rst(void);
+void rx_audio_bandgap_en(void);
 extern void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2, bool en);
 extern void rx_phy_power_on(unsigned int onoff);
 
index 637afbc..9dc04ac 100644 (file)
@@ -96,7 +96,7 @@ int force_vic;
 uint32_t fsm_log_en;
 uint32_t err_chk_en;
 
-static int aud_sr_stb_max = 20;
+static int aud_sr_stb_max = 30;
 
 /* used in other module */
 static int audio_sample_rate;
@@ -2417,16 +2417,14 @@ void rx_main_state_machine(void)
                                        rx_pr("reqclk err->wait_clk\n");
                                } else if (aud_sts == E_PLLRATE_CHG)
                                        rx_aud_pll_ctl(1);
-                               else if (aud_sts == E_AUDCLK_ERR) {
+                               else if (aud_sts == E_AUDCLK_ERR)
                                        rx_audio_bandgap_rst();
-                                       rx.aud_sr_stable_cnt = 0;
-                               } else {
+                               else {
                                        rx_acr_info_sw_update();
                                        rx_audio_pll_sw_update();
-                                       if (log_level & AUDIO_LOG)
-                                               rx_pr("update audio-err\n");
                                }
-
+                               if (log_level & AUDIO_LOG)
+                                       rx_pr("update audio-err:%d\n, aud_sts");
                                rx.aud_sr_unstable_cnt = 0;
                        }
                } else