devp->param.port = port;
/* should enable the adc ref signal for audio pll */
- vdac_enable(1, 0x10);
-
+ /* vdac_enable(1, 0x10); */
hdmirx_open_port(port);
rx.open_fg = 1;
rx_pr("%s port:%x ok nosignal:%d\n", __func__, port, rx.no_signal);
#include "hdmi_rx_edid.h"
-#define RX_VER0 "ver.2019-09-26"
+#define RX_VER0 "ver.2019-09-27"
/*
*
*
int real_channel_num;
int real_sample_size;
int real_sr;
+ u32 aud_clk;
};
struct phy_sts {
audio_info->n/128;
} else
audio_info->arc = 0;
+
+ audio_info->aud_clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
}
/*
*/
void rx_audio_bandgap_rst(void)
{
- vdac_enable(0, 0x10);
- udelay(20);
- vdac_enable(1, 0x10);
+ if (rx.chip_id >= CHIP_ID_TL1)
+ return;
+
+ wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 1);
+ udelay(10);
+ wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 0);
+ if (log_level & AUDIO_LOG)
+ rx_pr("%s\n", __func__);
+}
+
+void rx_audio_bandgap_en(void)
+{
+ if (rx.chip_id >= CHIP_ID_TL1)
+ return;
+
+ wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(9), 1);
+ wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 1);
+ udelay(10);
+ wr_reg_hhi_bits(HHI_VDAC_CNTL0_TXLX, _BIT(13), 0);
+
if (log_level & AUDIO_LOG)
rx_pr("%s\n", __func__);
}
bool is_aud_pll_error(void)
{
bool ret = true;
- int32_t clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
+ u32 clk = rx.aud_info.aud_clk;
int32_t aud_128fs = rx.aud_info.real_sr * 128;
int32_t aud_512fs = rx.aud_info.real_sr * 512;
}
} else {
if (en) {
+ rx_audio_bandgap_en();
tmp = hdmirx_rd_phy(PHY_MAINFSM_STATUS1);
wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000);
/* audio pll div depends on input freq */
{
int ret = E_AUDPLL_OK;
int32_t req_clk = rx_measure_clock(MEASURE_CLK_MPLL);
- int32_t aud_clk = rx_measure_clock(MEASURE_CLK_AUD_PLL);
+ u32 aud_clk = rx.aud_info.aud_clk;
uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
/* TXLX */
/* unified_register.h by wujun */
#define HHI_AUDPLL_CLK_OUT_CNTL (0x8c << 2)
-
+#define HHI_VDAC_CNTL0_TXLX (0xBD * 4)
#define PREG_PAD_GPIO0_EN_N (0x0c * 4)
#define PREG_PAD_GPIO0_O (0x0d * 4)
#define PREG_PAD_GPIO0_I (0x0e * 4)
extern void rx_force_hpd_cfg(uint8_t hpd_level);
extern void rx_force_rxsense_cfg(uint8_t level);
extern void rx_force_hpd_rxsense_cfg(uint8_t level);
-extern void rx_audio_bandgap_rst(void);
-extern void rx_audio_bandgap_rst(void);
+void rx_audio_bandgap_rst(void);
+void rx_audio_bandgap_en(void);
extern void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2, bool en);
extern void rx_phy_power_on(unsigned int onoff);
uint32_t fsm_log_en;
uint32_t err_chk_en;
-static int aud_sr_stb_max = 20;
+static int aud_sr_stb_max = 30;
/* used in other module */
static int audio_sample_rate;
rx_pr("reqclk err->wait_clk\n");
} else if (aud_sts == E_PLLRATE_CHG)
rx_aud_pll_ctl(1);
- else if (aud_sts == E_AUDCLK_ERR) {
+ else if (aud_sts == E_AUDCLK_ERR)
rx_audio_bandgap_rst();
- rx.aud_sr_stable_cnt = 0;
- } else {
+ else {
rx_acr_info_sw_update();
rx_audio_pll_sw_update();
- if (log_level & AUDIO_LOG)
- rx_pr("update audio-err\n");
}
-
+ if (log_level & AUDIO_LOG)
+ rx_pr("update audio-err:%d\n, aud_sts");
rx.aud_sr_unstable_cnt = 0;
}
} else