platform/x86: intel_pmc_core: Remove slp_s0 attributes from tgl_reg_map
authorGayatri Kammela <gayatri.kammela@intel.com>
Tue, 4 Feb 2020 23:01:57 +0000 (15:01 -0800)
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Mon, 10 Feb 2020 15:47:38 +0000 (17:47 +0200)
If platforms such as Tiger Lake has sub-states of S0ix, then both
slp_s0_debug_status and slp_s0_dbg_latch entries become invalid. Thus,
remove slp_s0_offset and slp_s0_dbg_maps attributes from tgl_reg_map, so
that both the entries are not created.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Suggested-by: David Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
drivers/platform/x86/intel_pmc_core.c

index 8792b46..97511a7 100644 (file)
@@ -556,8 +556,6 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = {
 
 static const struct pmc_reg_map tgl_reg_map = {
        .pfear_sts = ext_tgl_pfear_map,
-       .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
-       .slps0_dbg_maps = cnp_slps0_dbg_maps,
        .ltr_show_sts = cnp_ltr_show_map,
        .msr_sts = msr_map,
        .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,