}
if (RB.getID() == AArch64::FPRRegBankID) {
- if (Ty.getSizeInBits() <= 16)
+ switch (Ty.getSizeInBits()) {
+ case 8:
+ return &AArch64::FPR8RegClass;
+ case 16:
return &AArch64::FPR16RegClass;
- if (Ty.getSizeInBits() == 32)
+ case 32:
return &AArch64::FPR32RegClass;
- if (Ty.getSizeInBits() == 64)
+ case 64:
return &AArch64::FPR64RegClass;
- if (Ty.getSizeInBits() == 128)
+ case 128:
return &AArch64::FPR128RegClass;
+ }
return nullptr;
}
RET_ReallyLR implicit $h0
...
---
+name: v16s8
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+ - { reg: '$q0' }
+body: |
+ bb.1:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: v16s8
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.bsub
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK: $w0 = COPY [[COPY2]]
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:fpr(<16 x s8>) = COPY $q0
+ %2:gpr(s64) = G_CONSTANT i64 0
+ %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)
+ %4:gpr(s8) = COPY %1(s8)
+ %3:gpr(s32) = G_ANYEXT %4(s8)
+ $w0 = COPY %3(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
name: v2p0
alignment: 4
legalized: true