assert(MBBI->getOpcode() == XCore::RETSP_u6
|| MBBI->getOpcode() == XCore::RETSP_lu6);
int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
- BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
+ for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
+ MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
MBB.erase(MBBI);
} else {
int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
; RUN: llc < %s -march=xcore | FileCheck %s
-; CHECK: f1
+; CHECK-LABEL: f1
; CHECK: stw lr, sp[0]
; CHECK: ldw lr, sp[0]
; CHECK-NEXT: retsp 0
tail call void asm sideeffect "", "~{lr}"() nounwind
ret void
}
+
+; CHECK-LABEL: f3
+; CHECK: entsp 2
+; CHECK: stw [[REG:r[4-9]+]], sp[1]
+; CHECK: mov [[REG]], r0
+; CHECK: bl f2
+; CHECK: mov r0, [[REG]]
+; CHECK: ldw [[REG]], sp[1]
+; CHECK: retsp 2
+declare void @f2()
+define i32 @f3(i32 %i) nounwind {
+entry:
+ call void @f2()
+ ret i32 %i
+}