arm64: dts: rockchip: set num-cs property for spi on px30

[ Upstream commit 334bf0710c98d391f4067b72f535d6c4c84dfb6f ]

The px30 has two spi controllers with two chip-selects each.
The num-cs property is specified as the total number of chip
selects a controllers has and is used since 2020 to find uses
of chipselects outside that range in the Rockchip spi driver.

Without the property set, the default is 1, so spi devices
using the second chipselect will not be created.

Fixes: eb1262e3cc8b ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods")
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20240119101656.965744-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 42ce78beb4134d15bdbbe80bcde366ab32b50c11..20955556b624d037cb49720926ff720aa54ec507 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -632,6 +632,7 @@
                clock-names = "spiclk", "apb_pclk";
                dmas = <&dmac 12>, <&dmac 13>;
                dma-names = "tx", "rx";
+               num-cs = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
                #address-cells = <1>;
@@ -647,6 +648,7 @@
                clock-names = "spiclk", "apb_pclk";
                dmas = <&dmac 14>, <&dmac 15>;
                dma-names = "tx", "rx";
+               num-cs = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
                #address-cells = <1>;