drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointers

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/491921/
Link: https://lore.kernel.org/r/20220629225331.357308-10-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index e10ba1b..1a85535 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -764,14 +764,14 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
 
 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
                                                const char *name,
-                                               const char *parent_name,
+                                               const struct clk_hw *parent_hw,
                                                unsigned long flags,
                                                u8 shift)
 {
        struct dsi_pll_14nm_postdiv *pll_postdiv;
        struct device *dev = &pll_14nm->phy->pdev->dev;
        struct clk_init_data postdiv_init = {
-               .parent_names = (const char *[]) { parent_name },
+               .parent_hws = (const struct clk_hw *[]) { parent_hw },
                .num_parents = 1,
                .name = name,
                .flags = flags,
@@ -800,23 +800,23 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
 
 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
 {
-       char clk_name[32], parent[32], vco_name[32];
+       char clk_name[32];
        struct clk_init_data vco_init = {
                .parent_data = &(const struct clk_parent_data) {
                        .fw_name = "ref",
                },
                .num_parents = 1,
-               .name = vco_name,
+               .name = clk_name,
                .flags = CLK_IGNORE_UNUSED,
                .ops = &clk_ops_dsi_pll_14nm_vco,
        };
        struct device *dev = &pll_14nm->phy->pdev->dev;
-       struct clk_hw *hw;
+       struct clk_hw *hw, *n1_postdiv, *n1_postdivby2;
        int ret;
 
        DBG("DSI%d", pll_14nm->phy->id);
 
-       snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_14nm->phy->id);
+       snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id);
        pll_14nm->clk_hw.init = &vco_init;
 
        ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
@@ -824,48 +824,46 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
                return ret;
 
        snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
-       snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_14nm->phy->id);
 
        /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
-       hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
-                                      CLK_SET_RATE_PARENT, 0);
-       if (IS_ERR(hw))
-               return PTR_ERR(hw);
+       n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name,
+                       &pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0);
+       if (IS_ERR(n1_postdiv))
+               return PTR_ERR(n1_postdiv);
 
        snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id);
-       snprintf(parent, sizeof(parent), "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
 
        /* DSI Byte clock = VCO_CLK / N1 / 8 */
-       hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-                                              CLK_SET_RATE_PARENT, 1, 8);
+       hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
+                       n1_postdiv, CLK_SET_RATE_PARENT, 1, 8);
        if (IS_ERR(hw))
                return PTR_ERR(hw);
 
        provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
        snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
-       snprintf(parent, sizeof(parent), "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
 
        /*
         * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
         * on the way. Don't let it set parent.
         */
-       hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
-       if (IS_ERR(hw))
-               return PTR_ERR(hw);
+       n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+                       clk_name, n1_postdiv, 0, 1, 2);
+       if (IS_ERR(n1_postdivby2))
+               return PTR_ERR(n1_postdivby2);
 
        snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id);
-       snprintf(parent, sizeof(parent), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
 
        /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
         * This is the output of N2 post-divider, bits 4-7 in
         * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
         */
-       hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
+       hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2,
+                       0, 4);
        if (IS_ERR(hw))
                return PTR_ERR(hw);
 
-       provided_clocks[DSI_PIXEL_PLL_CLK]      = hw;
+       provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
 
        return 0;
 }