clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent

The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
rate change requests to its parent, so that DVFS for the GPU can work
properly.

Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index f578b39..730c9ae 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = {
        .sta_ofs = 0x0,
 };
 
-#define GATE_MFG(_id, _name, _parent, _shift)                  \
-       GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift,     \
-               &mtk_clk_gate_ops_setclr)
+#define GATE_MFG(_id, _name, _parent, _shift)                          \
+       GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift,       \
+                      &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
 
 static const struct mtk_gate mfg_clks[] = {
        GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)