ARM: mx5: Add LCD IPU pinctrl data

This patch adds pinmux for IPU LCD 1 and IPU LVDS.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index c132481..b298025 100644 (file)
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -508,6 +508,62 @@
                                        };
                                };
 
+                               ipu_disp1 {
+                                       pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                               fsl,pins = <
+                                                       MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
+                                                       MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
+                                                       MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
+                                                       MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
+                                                       MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
+                                                       MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
+                                                       MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
+                                                       MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
+                                                       MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
+                                                       MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
+                                                       MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
+                                                       MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
+                                                       MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
+                                                       MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
+                                                       MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
+                                                       MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
+                                                       MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
+                                                       MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
+                                                       MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
+                                                       MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
+                                                       MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
+                                                       MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
+                                                       MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
+                                                       MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
+                                                       MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
+                                                       MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
+                                                       MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
+                                                       MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
+                                                       MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
+                                                       MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
+                                                       MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
+                                                       MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
+                                               >;
+                                       };
+                               };
+
+                               ipu_disp2 {
+                                       pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                               fsl,pins = <
+                                                       MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
+                                                       MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
+                                                       MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
+                                                       MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
+                                                       MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
+                                                       MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
+                                                       MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
+                                                       MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
+                                                       MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
+                                                       MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
+                                               >;
+                                       };
+                               };
+
                                nand {
                                        pinctrl_nand_1: nandgrp-1 {
                                                fsl,pins = <