+2007-02-03 Kazu Hirata <kazu@codesourcery.com>
+
+ * c-decl.c, config/avr/avr.c, config/avr/avr.h,
+ config/m68k/m68k.c, config/m68k/netbsd-elf.h,
+ config/mn10300/mn10300.c, config/pdp11/pdp11.h,
+ config/rs6000/cell.md, config/rs6000/darwin.h,
+ config/sh/sh.md, config/sh/sh4-300.md, config/spu/spu.c,
+ config/spu/spu.md, cselib.c, expr.c, haifa-sched.c, hwint.h,
+ jump.c, reload.c, sched-deps.c, sched-int.h, tree-inline.c,
+ tree-profile.c, tree-ssa-live.h, tree-vrp.c: Fix comment
+ typos. Follow spelling conventions.
+ * doc/invoke.texi: Follow spelling conventions.
+
2007-02-03 Roger Sayle <roger@eyesopen.com>
* simplify-rtx.c (simplify_relational_operation_1): Implement some
/* Set this to 1 if you want the standard ISO C99 semantics of 'inline'
when you specify -std=c99 or -std=gnu99, and to 0 if you want
- behaviour compatible with the nonstandard semantics implemented by
+ behavior compatible with the nonstandard semantics implemented by
GCC 2.95 through 4.2. */
#define WANT_C99_INLINE_SEMANTICS 1
return 24;
}
-/* Ceate an RTX representing the place where a
+/* Create an RTX representing the place where a
library function returns a value of mode MODE. */
rtx
#define CC1PLUS_SPEC "%{!frtti:-fno-rtti} \
%{!fenforce-eh-specs:-fno-enforce-eh-specs} \
%{!fexceptions:-fno-exceptions}"
-/* A C string constant that tells the GCC drvier program options to
+/* A C string constant that tells the GCC driver program options to
pass to `cc1plus'. */
#define ASM_SPEC "%{mmcu=avr25:-mmcu=avr2;\
implementing architecture ARCH. -mcpu=CPU should override -march
and should generate code that runs on processor CPU, making free
use of any instructions that CPU understands. -mtune=UARCH applies
- on top of -mcpu or -march and optimises the code for UARCH. It does
+ on top of -mcpu or -march and optimizes the code for UARCH. It does
not change the target architecture. */
if (m68k_cpu_entry)
{
/* Provide an ASM_SPEC appropriate for NetBSD m68k ELF targets. We need
- to passn PIC code generation options. */
+ to pass PIC code generation options. */
#undef ASM_SPEC
#define ASM_SPEC "%(asm_cpu_spec) %{fpic|fpie:-k} %{fPIC|fPIE:-k -K}"
/* Print a set of registers in the format required by "movm" and "ret".
Register K is saved if bit K of MASK is set. The data and address
registers can be stored individually, but the extended registers cannot.
- We assume that the mask alread takes that into account. For instance,
+ We assume that the mask already takes that into account. For instance,
bits 14 to 17 must have the same value. */
void
For the pdp11, this is nonzero to account for the return address.
1 - return address
2 - frame pointer (always saved, even when not used!!!!)
- -- chnage some day !!!:q!
+ -- change some day !!!:q!
*/
#define FIRST_PARM_OFFSET(FNDECL) 4
;; This file simulate PPU processor unit backend of pipeline, maualP24.
;; manual P27, stall and flush points
;; IU, XU, VSU, dispatcher decodes and dispatch 2 insns per cycle in program
-;; order, the grouped adress are aligned by 8
+;; order, the grouped address are aligned by 8
;; This file only simulate one thread situation
;; XU executes all fixed point insns(3 units, a simple alu, a complex unit,
;; and load/store unit)
macro in the Apple version of GCC, except that version supports
'mac68k' alignment, and that version uses the computed alignment
always for the first field of a structure. The first-field
- behaviour is dealt with by
+ behavior is dealt with by
darwin_rs6000_special_round_type_align. */
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
(TARGET_ALIGN_NATURAL ? (COMPUTED) \
; N.B. This should agree with LOAD_EXTEND_OP and movqi.
; Because we use zero extension, we can't provide signed QImode compares
-; using a simple compare or conditional banch insn.
+; using a simple compare or conditional branch insn.
(define_insn "truncdiqi2"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
(truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
;; Scheduling runs before reorg, so we approximate this by saying that we
;; want the call to be paired with a preceding insn.
;; In most cases, the insn that loads the address of the call should have
-;; a non-zero latency (mov rn,rm doesn't make sense since we could use rn
+;; a nonzero latency (mov rn,rm doesn't make sense since we could use rn
;; for the address then). Thus, a preceding insn that can be paired with
;; a call should be eligible for the delay slot.
;;
return NULL_TREE;
}
-/* Return non-zero if FUNC is a naked function. */
+/* Return nonzero if FUNC is a naked function. */
static int
spu_naked_function_p (tree func)
{
(define_insn_reservation "FP7" 7 (eq_attr "type" "fp7")
"pipe0, fp, nothing*5")
-;; The behaviour of the double precision is that both pipes stall
+;; The behavior of the double precision is that both pipes stall
;; for 6 cycles and the the rest of the operation pipelines for
;; 7 cycles. The simplest way to model this is to simply ignore
;; the 6 cyle stall.
if (n_useless_values > MAX_USELESS_VALUES
/* remove_useless_values is linear in the hash table size. Avoid
- quadratic behaviour for very large hashtables with very few
+ quadratic behavior for very large hashtables with very few
useless elements. */
&& (unsigned int)n_useless_values > cselib_hash_table->n_elements / 4)
remove_useless_values ();
on load and link times of a DSO as it massively reduces the size of the
dynamic export table when the library makes heavy use of templates.
-The behaviour of this switch is not quite the same as marking the
+The behavior of this switch is not quite the same as marking the
methods as hidden directly, because it does not affect static variables
local to the function or cause the compiler to deduce that
the function is defined in only one shared object.
&& TREE_CODE (array) != VAR_DECL)
return 0;
- /* Check if the array has a non-zero lower bound. */
+ /* Check if the array has a nonzero lower bound. */
lower_bound = array_ref_low_bound (TREE_OPERAND (arg, 0));
if (!integer_zerop (lower_bound))
{
rtx dep_cost_rtx_link = alloc_INSN_LIST (NULL_RTX, NULL_RTX);
/* Make it self-cycled, so that if some tries to walk over this
- incomplete list he/she will be cought in an endless loop. */
+ incomplete list he/she will be caught in an endless loop. */
XEXP (dep_cost_rtx_link, 1) = dep_cost_rtx_link;
/* Targets use only REG_NOTE_KIND of the link. */
efficiently in hardware. (That is, the widest integer type that fits
in a hardware register.) Normally this is "long" but on some hosts it
should be "long long" or "__int64". This is no convenient way to
- autodect this, so such systems must set a flag in config.host; see there
+ autodetect this, so such systems must set a flag in config.host; see there
for details. */
#ifdef USE_LONG_LONG_FOR_WIDEST_FAST_INT
{
rtx note;
- /* negative DELETE_UNUSED used to be used to signalize behaviour on
+ /* Negative DELETE_UNUSED used to be used to signalize behavior on
moving FUNCTION_END note. Just sanity check that no user still worry
about this. */
gcc_assert (delete_unused >= 0);
return;
/* If there is a reload for part of the address of this operand, we would
- need to chnage it to RELOAD_FOR_OTHER_ADDRESS. But that would extend
+ need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend
its life to the point where doing this combine would not lower the
number of spill registers needed. */
for (i = 0; i < n_reloads; i++)
/* Init DEP with the arguments.
While most of the scheduler (including targets) only need the major type
- of the dependency, it is convinient to hide full dep_status from them. */
+ of the dependency, it is convenient to hide full dep_status from them. */
void
init_dep (dep_t dep, rtx pro, rtx con, enum reg_note kind)
{
gcc_assert (deps_list_consistent_p (INSN_BACK_DEPS (insn)));
}
-/* Remove a dependency refered by L. */
+/* Remove a dependency referred to by L. */
void
delete_back_forw_dep (dep_link_t l)
{
void move_dep_link (dep_link_t, deps_list_t);
-/* Suppose we have a depedence Y between insn pro1 and con1, where pro1 has
- additional dependants con0 and con2, and con1 is dependant on additional
+/* Suppose we have a dependence Y between insn pro1 and con1, where pro1 has
+ additional dependents con0 and con2, and con1 is dependent on additional
insns pro0 and pro1:
.con0 pro0
}
/* Estimate number of instructions that will be created by expanding EXPR.
- WEIGHTS contains weigths attributed to various constructs. */
+ WEIGHTS contains weights attributed to various constructs. */
int
estimate_num_insns (tree expr, eni_weights *weights)
/* Add code:
static gcov* __gcov_indirect_call_counters; // pointer to actual counter
- static void* __gcov_indirect_call_callee; // actual callee address
+ static void* __gcov_indirect_call_callee; // actual callee addres
*/
static void
tree_init_ic_make_global_vars (void)
change. (ie, it is truly a view since it doesn't change anything)
The final component of the data structure is the basevar map. This provides
- a list of all the different base variables which occue in a partition view,
+ a list of all the different base variables which occur in a partition view,
and a unique index for each one. Routines are provided to quickly produce
the base variable of a partition.
/* Checks one ARRAY_REF in REF, located at LOCUS. Ignores flexible arrays
and "struct" hacks. If VRP can determine that the
- array subscript is a contant, check if it is outside valid
+ array subscript is a constant, check if it is outside valid
range. If the array subscript is a RANGE, warn if it is
non-overlapping with valid range.
IGNORE_OFF_BY_ONE is true if the ARRAY_REF is inside a ADDR_EXPR. */
projects / platform / upstream / gcc.git / commitdiff