i965: Add brw_store_register_mem32
authorJordan Justen <jordan.l.justen@intel.com>
Fri, 15 Apr 2016 02:43:45 +0000 (19:43 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Wed, 4 May 2016 18:23:17 +0000 (11:23 -0700)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/intel_batchbuffer.c

index 948b082..efe7730 100644 (file)
@@ -1448,6 +1448,8 @@ void brw_load_register_mem64(struct brw_context *brw,
                              drm_intel_bo *bo,
                              uint32_t read_domains, uint32_t write_domain,
                              uint32_t offset);
+void brw_store_register_mem32(struct brw_context *brw,
+                              drm_intel_bo *bo, uint32_t reg, uint32_t offset);
 void brw_store_register_mem64(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, uint32_t offset);
 
index cd5d301..03a31b6 100644 (file)
@@ -539,6 +539,32 @@ brw_load_register_mem64(struct brw_context *brw,
 }
 
 /*
+ * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
+ */
+void
+brw_store_register_mem32(struct brw_context *brw,
+                         drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+{
+   assert(brw->gen >= 6);
+
+   if (brw->gen >= 8) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+      OUT_BATCH(reg);
+      OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                  offset);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(3);
+      OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+      OUT_BATCH(reg);
+      OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                offset);
+      ADVANCE_BATCH();
+   }
+}
+
+/*
  * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
  */
 void