return regmap;
}
-static void csi2_ctx_config(struct cal_ctx *ctx)
+/* ------------------------------------------------------------------
+ * Context Management
+ * ------------------------------------------------------------------
+ */
+
+static void cal_ctx_csi2_config(struct cal_ctx *ctx)
{
u32 val;
reg_read(ctx->cal, CAL_CSI2_CTX0(ctx->csi2_port)));
}
-static void pix_proc_config(struct cal_ctx *ctx)
+static void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
{
u32 val, extract, pack;
reg_read(ctx->cal, CAL_PIX_PROC(ctx->csi2_port)));
}
-static void cal_wr_dma_config(struct cal_ctx *ctx,
- unsigned int width, unsigned int height)
+static void cal_ctx_wr_dma_config(struct cal_ctx *ctx,
+ unsigned int width, unsigned int height)
{
u32 val;
ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->cal, CAL_CTRL));
}
-static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
+static void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
{
reg_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->csi2_port), dmaaddr);
}
list_del(&buf->list);
addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
- cal_wr_dma_addr(ctx, addr);
+ cal_ctx_wr_dma_addr(ctx, addr);
}
static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
pm_runtime_get_sync(&ctx->cal->pdev->dev);
- csi2_ctx_config(ctx);
- pix_proc_config(ctx);
- cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline,
- ctx->v_fmt.fmt.pix.height);
+ cal_ctx_csi2_config(ctx);
+ cal_ctx_pix_proc_config(ctx);
+ cal_ctx_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline,
+ ctx->v_fmt.fmt.pix.height);
cal_camerarx_lane_config(ctx->phy);
cal_camerarx_enable_irqs(ctx->phy);
}
cal_camerarx_wait_ready(ctx->phy);
- cal_wr_dma_addr(ctx, addr);
+ cal_ctx_wr_dma_addr(ctx, addr);
cal_camerarx_ppi_enable(ctx->phy);
if (debug >= 4)