net: stmmac: Add EST errors into ethtool statistic
authorOng Boon Leong <boon.leong.ong@intel.com>
Thu, 18 Mar 2021 00:50:53 +0000 (08:50 +0800)
committerDavid S. Miller <davem@davemloft.net>
Thu, 18 Mar 2021 21:34:07 +0000 (14:34 -0700)
Below EST errors are added into ethtool statistic:
1) Constant Gate Control Error (CGCE):
   The counter "mtl_est_cgce" increases everytime CGCE interrupt is
   triggered.

2) Head-of-Line Blocking due to Scheduling (HLBS):
   The counter "mtl_est_hlbs" increases everytime HLBS interrupt is
   triggered.

3) Head-of-Line Blocking due to Frame Size (HLBF):
   The counter "mtl_est_hlbf" increases everytime HLBF interrupt is
   triggered.

4) Base Time Register error (BTRE):
   The counter "mtl_est_btre" increases everytime BTRE interrupt is
   triggered but BTRL not reaches maximum value of 15.

5) Base Time Register Error Loop Count (BTRL) reaches maximum value:
   The counter "mtl_est_btrlm" increases everytime BTRE interrupt is
   triggered and BTRL value reaches maximum value of 15.

Please refer to MTL_EST_STATUS register in DesignWare Cores Ethernet
Quality-of-Service Databook for more detail explanation.

Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Co-developed-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
Signed-off-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
drivers/net/ethernet/stmicro/stmmac/dwmac5.h
drivers/net/ethernet/stmicro/stmmac/hwif.h
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

index 6f271c4..1c0c60b 100644 (file)
@@ -182,6 +182,12 @@ struct stmmac_extra_stats {
        /* TSO */
        unsigned long tx_tso_frames;
        unsigned long tx_tso_nfrags;
+       /* EST */
+       unsigned long mtl_est_cgce;
+       unsigned long mtl_est_hlbs;
+       unsigned long mtl_est_hlbf;
+       unsigned long mtl_est_btre;
+       unsigned long mtl_est_btrlm;
 };
 
 /* Safety Feature statistics exposed by ethtool */
index 809015f..0ae85f8 100644 (file)
@@ -608,7 +608,7 @@ int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
 }
 
 void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
-                         u32 txqcnt)
+                         struct stmmac_extra_stats *x, u32 txqcnt)
 {
        u32 status, value, feqn, hbfq, hbfs, btrl;
        u32 txqcnt_mask = (1 << txqcnt) - 1;
@@ -624,12 +624,16 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
        if (status & CGCE) {
                /* Clear Interrupt */
                writel(CGCE, ioaddr + MTL_EST_STATUS);
+
+               x->mtl_est_cgce++;
        }
 
        if (status & HLBS) {
                value = readl(ioaddr + MTL_EST_SCH_ERR);
                value &= txqcnt_mask;
 
+               x->mtl_est_hlbs++;
+
                /* Clear Interrupt */
                writel(value, ioaddr + MTL_EST_SCH_ERR);
 
@@ -649,6 +653,8 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
                hbfq = (value & SZ_CAP_HBFQ_MASK(txqcnt)) >> SZ_CAP_HBFQ_SHIFT;
                hbfs = value & SZ_CAP_HBFS_MASK;
 
+               x->mtl_est_hlbf++;
+
                /* Clear Interrupt */
                writel(feqn, ioaddr + MTL_EST_FRM_SZ_ERR);
 
@@ -658,6 +664,11 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
        }
 
        if (status & BTRE) {
+               if ((status & BTRL) == BTRL_MAX)
+                       x->mtl_est_btrlm++;
+               else
+                       x->mtl_est_btre++;
+
                btrl = (status & BTRL) >> BTRL_SHIFT;
 
                if (net_ratelimit())
index 7174f5e..709bbfc 100644 (file)
@@ -142,7 +142,7 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
 int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
                         unsigned int ptp_rate);
 void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
-                          u32 txqcnt);
+                          struct stmmac_extra_stats *x, u32 txqcnt);
 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
                          bool enable);
 
index 4bcdedf..692541c 100644 (file)
@@ -394,7 +394,7 @@ struct stmmac_ops {
        int (*est_configure)(void __iomem *ioaddr, struct stmmac_est *cfg,
                             unsigned int ptp_rate);
        void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev,
-                              u32 txqcnt);
+                              struct stmmac_extra_stats *x, u32 txqcnt);
        void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
                              bool enable);
 };
index a78d5b0..61b1163 100644 (file)
@@ -158,6 +158,12 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
        /* TSO */
        STMMAC_STAT(tx_tso_frames),
        STMMAC_STAT(tx_tso_nfrags),
+       /* EST */
+       STMMAC_STAT(mtl_est_cgce),
+       STMMAC_STAT(mtl_est_hlbs),
+       STMMAC_STAT(mtl_est_hlbf),
+       STMMAC_STAT(mtl_est_btre),
+       STMMAC_STAT(mtl_est_btrlm),
 };
 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
 
index 0d74d11..8d7015d 100644 (file)
@@ -4315,7 +4315,8 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
                return IRQ_HANDLED;
 
        if (priv->dma_cap.estsel)
-               stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, tx_cnt);
+               stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
+                                     &priv->xstats, tx_cnt);
 
        /* To handle GMAC own interrupts */
        if ((priv->plat->has_gmac) || xmac) {