(sctx)->context_roll = true; \
} while (0)
-#define radeon_emit_array(cs, values, num) do { \
+#define radeon_emit_array(values, num) do { \
unsigned __n = (num); \
memcpy(__cs_buf + __cs_num, (values), __n * 4); \
__cs_num += __n; \
#define radeon_set_context_reg_seq_array(cs, reg, num, values) do { \
radeon_set_context_reg_seq(cs, reg, num); \
- radeon_emit_array(cs, values, num); \
+ radeon_emit_array(values, num); \
} while (0)
#define radeon_set_context_reg_idx(cs, reg, idx, value) do { \
#define radeon_opt_set_context_regn(sctx, offset, value, saved_val, num) do { \
if (memcmp(value, saved_val, sizeof(uint32_t) * (num))) { \
radeon_set_context_reg_seq(&(sctx)->gfx_cs, offset, num); \
- radeon_emit_array(cs, value, num); \
+ radeon_emit_array(value, num); \
memcpy(saved_val, value, sizeof(uint32_t) * (num)); \
} \
} while (0)
if (sel->info.base.cs.user_data_components_amd) {
radeon_set_sh_reg_seq(cs, cs_user_data_reg, sel->info.base.cs.user_data_components_amd);
- radeon_emit_array(cs, sctx->cs_user_data, sel->info.base.cs.user_data_components_amd);
+ radeon_emit_array(sctx->cs_user_data, sel->info.base.cs.user_data_components_amd);
}
radeon_end();
}
radeon_emit(S_370_DST_SEL(dst_sel) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine));
radeon_emit(va);
radeon_emit(va >> 32);
- radeon_emit_array(cs, (const uint32_t *)data, size / 4);
+ radeon_emit_array((const uint32_t *)data, size / 4);
radeon_end();
}
{
radeon_begin(cs);
radeon_set_context_reg_seq(cs, reg, num);
- radeon_emit_array(cs, values, num);
+ radeon_emit_array(values, num);
radeon_end();
}
num_shaderbufs * 4);
for (unsigned i = 0; i < num_shaderbufs; i++)
- radeon_emit_array(cs, &desc->list[si_get_shaderbuf_slot(i) * 4], 4);
+ radeon_emit_array(&desc->list[si_get_shaderbuf_slot(i) * 4], 4);
sctx->compute_shaderbuf_sgprs_dirty = false;
}
num_sgprs = 4;
}
- radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs);
+ radeon_emit_array(&desc->list[desc_offset], num_sgprs);
}
sctx->compute_image_sgprs_dirty = false;
}
radeon_begin(cs);
- radeon_emit_array(cs, state->pm4, state->ndw);
+ radeon_emit_array(state->pm4, state->ndw);
radeon_end();
if (state->atom.emit)
* write on correctly. */
radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->chip_class >= GFX10);
- radeon_emit_array(cs, dwords, count);
+ radeon_emit_array(dwords, count);
dwords += count;
num_dwords -= count;
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
- radeon_emit_array(cs, (uint32_t *)sctx->blend_color.color, 4);
+ radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
radeon_end();
}
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4);
- radeon_emit_array(cs, (uint32_t *)sctx->clip_state.ucp, 6 * 4);
+ radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
radeon_end();
}
/* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
- radeon_emit_array(cs, sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs);
+ radeon_emit_array(sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs);
} else if (base_vertex != sctx->last_base_vertex ||
sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
(set_base_instance &&
unsigned num_sgprs = MIN2(count, num_vbos_in_user_sgprs) * 4;
radeon_set_sh_reg_seq(cs, sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs);
- radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_sgprs);
+ radeon_emit_array(sctx->vb_descriptor_user_sgprs, num_sgprs);
sctx->vertex_buffer_user_sgprs_dirty = false;
}
radeon_end();
radeon_emit(centroid_priority >> 32);
radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0,
num_samples == 8 ? 14 : 16);
- radeon_emit_array(cs, sample_locs, 4);
- radeon_emit_array(cs, sample_locs, 4);
- radeon_emit_array(cs, sample_locs, 4);
- radeon_emit_array(cs, sample_locs, num_samples == 8 ? 2 : 4);
+ radeon_emit_array(sample_locs, 4);
+ radeon_emit_array(sample_locs, 4);
+ radeon_emit_array(sample_locs, 4);
+ radeon_emit_array(sample_locs, num_samples == 8 ? 2 : 4);
radeon_end();
}