intel: emit 3DSTATE_INDEX_BUFFER directly on GEN7.5+
authorChia-I Wu <olvaffe@gmail.com>
Wed, 20 Aug 2014 07:39:56 +0000 (15:39 +0800)
committerChia-I Wu <olvaffe@gmail.com>
Thu, 21 Aug 2014 02:30:54 +0000 (10:30 +0800)
icd/intel/cmd_pipeline.c
icd/intel/cmd_priv.h

index 9464ca20dfb1111f5184ae74d27cdcce5f75e8a7..8a662c80f4e5e5fef3e8aa4a3cb3a5de451df977 100644 (file)
@@ -22,6 +22,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include "genhw/genhw.h"
 #include "dset.h"
 #include "mem.h"
 #include "state.h"
@@ -144,6 +145,59 @@ XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
     }
 }
 
+static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
+                                      struct intel_mem *mem,
+                                      XGL_GPU_SIZE offset,
+                                      XGL_INDEX_TYPE type,
+                                      bool enable_cut_index)
+{
+    const uint8_t cmd_len = 3;
+    uint32_t dw0, end_offset;
+    unsigned offset_align;
+
+    CMD_ASSERT(cmd, 6, 7.5);
+
+    dw0 = GEN_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
+
+    /* the bit is moved to 3DSTATE_VF */
+    if (cmd_gen(cmd) >= INTEL_GEN(7.5))
+        assert(!enable_cut_index);
+    if (enable_cut_index)
+        dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
+
+    switch (type) {
+    case XGL_INDEX_8:
+        dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
+        offset_align = 1;
+        break;
+    case XGL_INDEX_16:
+        dw0 |= GEN6_IB_DW0_FORMAT_WORD;
+        offset_align = 2;
+        break;
+    case XGL_INDEX_32:
+        dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
+        offset_align = 4;
+        break;
+    default:
+        cmd->result = XGL_ERROR_INVALID_VALUE;
+        return;
+        break;
+    }
+
+    if (offset % offset_align) {
+        cmd->result = XGL_ERROR_INVALID_VALUE;
+        return;
+    }
+
+    /* aligned and inclusive */
+    end_offset = mem->size - (mem->size % offset_align) - 1;
+
+    cmd_reserve(cmd, cmd_len);
+    cmd_write(cmd, dw0);
+    cmd_write_r(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
+    cmd_write_r(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
+}
+
 XGL_VOID XGLAPI intelCmdBindIndexData(
     XGL_CMD_BUFFER                              cmdBuffer,
     XGL_GPU_MEMORY                              mem_,
@@ -153,9 +207,13 @@ XGL_VOID XGLAPI intelCmdBindIndexData(
     struct intel_cmd *cmd = intel_cmd(cmdBuffer);
     struct intel_mem *mem = intel_mem(mem_);
 
-    cmd->bind.index.mem = mem;
-    cmd->bind.index.offset = offset;
-    cmd->bind.index.type = indexType;
+    if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
+        gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
+    } else {
+        cmd->bind.index.mem = mem;
+        cmd->bind.index.offset = offset;
+        cmd->bind.index.type = indexType;
+    }
 }
 
 XGL_VOID XGLAPI intelCmdBindAttachments(
index 1c1c2e20b3f18c23a0c08a3e129579ba7f499d18..e1e22df25dff435970e8a8404a243fb8fe7c37ea 100644 (file)
 #define CMD_ASSERT(cmd, min_gen, max_gen) \
     INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
 
+static inline int cmd_gen(const struct intel_cmd *cmd)
+{
+    return intel_gpu_gen(cmd->dev->gpu);
+}
+
 void cmd_grow(struct intel_cmd *cmd);
 
 /**