crypto: octeontx2 - disable DMA black hole on an DMA fault

When CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to
LLC/DRAM encounters a fault/poison, a rare case may result
in unpredictable data being delivered to a CPT engine.
So, this patch adds code to set FLT_DIS as a workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
index addc760..ede84ab 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
@@ -1144,6 +1144,7 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
        struct otx2_cpt_engines engs[OTX2_CPT_MAX_ETYPES_PER_GRP] = { {0} };
        struct pci_dev *pdev = cptpf->pdev;
        struct fw_info_t fw_info;
+       u64 reg_val;
        int ret = 0;
 
        mutex_lock(&eng_grps->lock);
@@ -1244,6 +1245,18 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
         */
        otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER,
                              CTX_FLUSH_TIMER_CNT, BLKADDR_CPT0);
+
+       /*
+        * Set CPT_AF_DIAG[FLT_DIS], as a workaround for HW errata, when
+        * CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to LLC/DRAM
+        * encounters a fault/poison, a rare case may result in
+        * unpredictable data being delivered to a CPT engine.
+        */
+       otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG, &reg_val,
+                            BLKADDR_CPT0);
+       otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,
+                             reg_val | BIT_ULL(24), BLKADDR_CPT0);
+
        mutex_unlock(&eng_grps->lock);
        return 0;
 

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index a73a801..a79201a 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -605,6 +605,7 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
        } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {
                /* Registers that can be accessed from PF */
                switch (offset) {
+               case CPT_AF_DIAG:
                case CPT_AF_CTL:
                case CPT_AF_PF_FUNC:
                case CPT_AF_BLK_RST: