case Intrinsic::launder_invariant_group:
case Intrinsic::strip_invariant_group:
case Intrinsic::masked_load:
+ case Intrinsic::smax:
+ case Intrinsic::smin:
+ case Intrinsic::umax:
+ case Intrinsic::umin:
case Intrinsic::sadd_with_overflow:
case Intrinsic::uadd_with_overflow:
case Intrinsic::ssub_with_overflow:
!getConstIntOrUndef(Operands[1], C1))
return nullptr;
+ unsigned BitWidth = Ty->getScalarSizeInBits();
switch (IntrinsicID) {
default: break;
+ case Intrinsic::smax:
+ if (!C0 && !C1)
+ return UndefValue::get(Ty);
+ if (!C0 || !C1)
+ return ConstantInt::get(Ty, APInt::getSignedMaxValue(BitWidth));
+ return ConstantInt::get(Ty, C0->sgt(*C1) ? *C0 : *C1);
+
+ case Intrinsic::smin:
+ if (!C0 && !C1)
+ return UndefValue::get(Ty);
+ if (!C0 || !C1)
+ return ConstantInt::get(Ty, APInt::getSignedMinValue(BitWidth));
+ return ConstantInt::get(Ty, C0->slt(*C1) ? *C0 : *C1);
+
+ case Intrinsic::umax:
+ if (!C0 && !C1)
+ return UndefValue::get(Ty);
+ if (!C0 || !C1)
+ return ConstantInt::get(Ty, APInt::getMaxValue(BitWidth));
+ return ConstantInt::get(Ty, C0->ugt(*C1) ? *C0 : *C1);
+
+ case Intrinsic::umin:
+ if (!C0 && !C1)
+ return UndefValue::get(Ty);
+ if (!C0 || !C1)
+ return ConstantInt::get(Ty, APInt::getMinValue(BitWidth));
+ return ConstantInt::get(Ty, C0->ult(*C1) ? *C0 : *C1);
+
case Intrinsic::usub_with_overflow:
case Intrinsic::ssub_with_overflow:
case Intrinsic::uadd_with_overflow:
define i8 @smax() {
; CHECK-LABEL: @smax(
-; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.smax.i8(i8 -128, i8 -127)
-; CHECK-NEXT: ret i8 [[R]]
+; CHECK-NEXT: ret i8 -127
;
%r = call i8 @llvm.smax.i8(i8 128, i8 129)
ret i8 %r
define <5 x i8> @smax_vec() {
; CHECK-LABEL: @smax_vec(
-; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
-; CHECK-NEXT: ret <5 x i8> [[R]]
+; CHECK-NEXT: ret <5 x i8> <i8 undef, i8 127, i8 127, i8 42, i8 127>
;
%r = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
ret <5 x i8> %r
define i8 @smin() {
; CHECK-LABEL: @smin(
-; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.smin.i8(i8 -128, i8 127)
-; CHECK-NEXT: ret i8 [[R]]
+; CHECK-NEXT: ret i8 -128
;
%r = call i8 @llvm.smin.i8(i8 128, i8 127)
ret i8 %r
define <5 x i8> @smin_vec() {
; CHECK-LABEL: @smin_vec(
-; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -127>)
-; CHECK-NEXT: ret <5 x i8> [[R]]
+; CHECK-NEXT: ret <5 x i8> <i8 undef, i8 -128, i8 -128, i8 42, i8 -127>
;
%r = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 129>)
ret <5 x i8> %r
define i8 @umax() {
; CHECK-LABEL: @umax(
-; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.umax.i8(i8 -128, i8 127)
-; CHECK-NEXT: ret i8 [[R]]
+; CHECK-NEXT: ret i8 -128
;
%r = call i8 @llvm.umax.i8(i8 128, i8 127)
ret i8 %r
define <5 x i8> @umax_vec() {
; CHECK-LABEL: @umax_vec(
-; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
-; CHECK-NEXT: ret <5 x i8> [[R]]
+; CHECK-NEXT: ret <5 x i8> <i8 undef, i8 -1, i8 -1, i8 42, i8 -128>
;
%r = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
ret <5 x i8> %r
define i8 @umin() {
; CHECK-LABEL: @umin(
-; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.umin.i8(i8 -128, i8 127)
-; CHECK-NEXT: ret i8 [[R]]
+; CHECK-NEXT: ret i8 127
;
%r = call i8 @llvm.umin.i8(i8 128, i8 127)
ret i8 %r
define <5 x i8> @umin_vec() {
; CHECK-LABEL: @umin_vec(
-; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
-; CHECK-NEXT: ret <5 x i8> [[R]]
+; CHECK-NEXT: ret <5 x i8> <i8 undef, i8 0, i8 0, i8 42, i8 42>
;
%r = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
ret <5 x i8> %r