rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I032641c782e915fa1f999a1e208dd915a22515f7

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index e8e0ff0eb4b3b7a1dcdea16daebbff2e37ab90c2..b4011ac96260164717002fcaec89f4039dfca6c8 100644 (file)
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
        select BCM2711
        select ARMV7_LPAE
        select CPU_V7A
+       select PHYS_64BIT
 
 config BCM2711_64B
        bool "Broadcom BCM2711 SoC 64-bit support"

diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae39852f159158c1a78fcd088d7049e62765b7..4ccaf69693db4dd5dcf4a7b58bdb607d395dd0a9 100644 (file)
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
 
 extern unsigned long rpi_bcm283x_base;
 
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
 #endif

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index f5e23a21913b24eb9c8feb3cbdd0ed6dcfa24658..59a0e6aa5a432ceca5c32a6af8917d642915540d 100644 (file)
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -144,6 +144,26 @@ int mach_cpu_init(void)
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT       0xff800000UL
+#include <addr_map.h>
+
+void init_addr_map(void)
+{
+       mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+                                            DCACHE_OFF);
+
+       /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+       /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+}
+#endif
+
 void enable_caches(void)
 {
        dcache_enable();

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index f88ab2d039eedf2c33953d84ce5c2a8cb92025b9..aa85e98762e8374453b20c4f98aeedcb7311e2eb 100644 (file)
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -66,6 +66,13 @@
 #define CONFIG_SYS_BOOTM_LEN           SZ_64M
 #endif
 
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 2
+#endif
+#endif
+
 /* Devices */
 /* GPIO */
 #define CONFIG_BCM2835_GPIO