--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Quad Serial Peripheral Interface (QuadSPI)
+
+maintainers:
+ - Han Xu <han.xu@nxp.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,vf610-qspi
+ - fsl,imx6sx-qspi
+ - fsl,imx7d-qspi
+ - fsl,imx6ul-qspi
+ - fsl,ls1021a-qspi
+ - fsl,ls2080a-qspi
+ - items:
+ - enum:
+ - fsl,ls1043a-qspi
+ - const: fsl,ls1021a-qspi
+ - items:
+ - enum:
+ - fsl,imx8mq-qspi
+ - const: fsl,imx7d-qspi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ reg-names:
+ items:
+ - const: QuadSPI
+ - const: QuadSPI-memory
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC SPI qspi_en clock
+ - description: SoC SPI qspi clock
+
+ clock-names:
+ items:
+ - const: qspi_en
+ - const: qspi
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spi@1550000 {
+ compatible = "fsl,ls1021a-qspi";
+ reg = <0x0 0x1550000 0x0 0x100000>,
+ <0x0 0x40000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "qspi_en", "qspi";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+ };
+ };
+++ /dev/null
-* Freescale Quad Serial Peripheral Interface(QuadSPI)
-
-Required properties:
- - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
- "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
- "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
- or
- "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
- - reg : the first contains the register location and length,
- the second contains the memory mapping address and length
- - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
- - interrupts : Should contain the interrupt for the device
- - clocks : The clocks needed by the QuadSPI controller
- - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
-
-Required SPI slave node properties:
- - reg: There are two buses (A and B) with two chip selects each.
- This encodes to which bus and CS the flash is connected:
- <0>: Bus A, CS 0
- <1>: Bus A, CS 1
- <2>: Bus B, CS 0
- <3>: Bus B, CS 1
-
-Example:
-
-qspi0: quadspi@40044000 {
- compatible = "fsl,vf610-qspi";
- reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks VF610_CLK_QSPI0_EN>,
- <&clks VF610_CLK_QSPI0>;
- clock-names = "qspi_en", "qspi";
-
- flash0: s25fl128s@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spansion,s25fl128s", "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-};
-
-Example showing the usage of two SPI NOR devices on bus A:
-
-&qspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi2>;
- status = "okay";
-
- flash0: n25q256a@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <0>;
- };
-
- flash1: n25q256a@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- reg = <1>;
- };
-};