freedreno/a6xx: Name TPL1_DBG_ECO_CNTL

This is a guess, but an informed guess, since every other block with a
known DBG_ECO_CNTL register has it at the very beginning immediately
followed by ADDR_MODE_CNTL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12929>

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index e4db088..1affb92 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -1675,7 +1675,7 @@ registers:
        deadbeef        0xae50: deadbeef
        deadbeef        0xae51: deadbeef
        deadbeef        0xae52: deadbeef
-       00000000        TPL1_UNKNOWN_B600: 0
+       00000000        TPL1_DBG_ECO_CNTL: 0
        00000001        TPL1_ADDR_MODE_CNTL: ADDR_64B
        00000004        TPL1_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 }
        00000000        TPL1_UNKNOWN_B605: 0

diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index cd11026..b9a579d 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -30,8 +30,8 @@ t4            write SP_PERFCTR_ENABLE (ae0f)
 t4             write TPL1_UNKNOWN_B605 (b605)
                        TPL1_UNKNOWN_B605: 68
 000000000105803c:              0000: 40b60501 00000044
-t4             write TPL1_UNKNOWN_B600 (b600)
-                       TPL1_UNKNOWN_B600: 0x100000
+t4             write TPL1_DBG_ECO_CNTL (b600)
+                       TPL1_DBG_ECO_CNTL: 0x100000
 0000000001058044:              0000: 40b60001 00100000
 t4             write HLSQ_UNKNOWN_BE00 (be00)
                        HLSQ_UNKNOWN_BE00: 0x80
@@ -359,7 +359,7 @@ t7          opcode: CP_BLIT (2c) (2 dwords)
 !+     01011000                SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
  +     00000000                SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
 !+     000000a2                SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
-!+     00100000                TPL1_UNKNOWN_B600: 0x100000
+!+     00100000                TPL1_DBG_ECO_CNTL: 0x100000
 !+     00000044                TPL1_UNKNOWN_B605: 68
 !+     000000fc                HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
 !+     000fffff                HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }

diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 1281664..0126894 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -27,8 +27,8 @@ t4            write SP_PERFCTR_ENABLE (ae0f)
 t4             write TPL1_UNKNOWN_B605 (b605)
                        TPL1_UNKNOWN_B605: 68
 0000000001d91034:              0000: 40b60501 00000044
-t4             write TPL1_UNKNOWN_B600 (b600)
-                       TPL1_UNKNOWN_B600: 0x100000
+t4             write TPL1_DBG_ECO_CNTL (b600)
+                       TPL1_DBG_ECO_CNTL: 0x100000
 0000000001d9103c:              0000: 40b60001 00100000
 t4             write HLSQ_UNKNOWN_BE00 (be00)
                        HLSQ_UNKNOWN_BE00: 0x80
@@ -1133,7 +1133,7 @@ t7                        opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +     00000000                        SP_TP_SAMPLE_CONFIG: { 0 }
  +     00000000                        SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
 !+     000000a2                        SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
-!+     00100000                        TPL1_UNKNOWN_B600: 0x100000
+!+     00100000                        TPL1_DBG_ECO_CNTL: 0x100000
 !+     00000044                        TPL1_UNKNOWN_B605: 68
 !+     00000100                        HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
  +     00000000                        HLSQ_HS_CNTL: { CONSTLEN = 0 }

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index a44ee52..e02052a 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3469,7 +3469,7 @@ to upconvert to 32b float internally?
        <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy"/>
 
        <!-- always 0x100000 or 0x1000000? -->
-       <reg32 offset="0xb600" name="TPL1_UNKNOWN_B600" low="0" high="25"/>
+       <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25"/>
        <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
        <reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint"/>
        <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index f6430fd..bbf916a 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -783,7 +783,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
    tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
-   tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B600, 0x100000);
+   tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL, 0x100000);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 95cdfa8..47a31e5 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1248,7 +1248,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
    WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
    WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
    WRITE(REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
-   WRITE(REG_A6XX_TPL1_UNKNOWN_B600, 0x100000);
+   WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, 0x100000);
    WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
    WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);