The gpio part2 map of exynos3 was incorrect. The gpio part2 is
started from 0x11000000 and the register map of gpk0 is
0x11000040. Thus, two gpio pads should be before gpk0.
The gpx0 is started from 0x11000c00 so we should fix the count
of res5 pad from 0x4a to 0x48.
Change-Id: I8ceae5009227daf0e4cff4d3d73aeb2318c640de
Reported-by: Jaeyoung Lee <jaeyoung2.lee@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
struct s5p_gpio_bank d0;
struct s5p_gpio_bank d1;
};
+
struct exynos3_gpio_part2 {
+ struct s5p_gpio_bank res0[2];
struct s5p_gpio_bank k0;
struct s5p_gpio_bank k1;
struct s5p_gpio_bank k2;
struct s5p_gpio_bank M2;
struct s5p_gpio_bank M3;
struct s5p_gpio_bank M4;
- struct s5p_gpio_bank res5[0x4a];
+ struct s5p_gpio_bank res5[0x48];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;