[PhaseOrdering] Add test for SimplifyCFG and LV interaction.

diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-required-for-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-required-for-vectorization.ll
new file mode 100644 (file)
index 0000000..23daafd
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-required-for-vectorization.ll
@@ -0,0 +1,114 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
+
+target triple = "arm64-apple-darwin"
+
+; Make sure we can vectorize a loop that uses a function to clamp a double to
+; be between a given minimum and maximum value.
+
+define internal double @clamp(double %v) {
+entry:
+  %retval = alloca double, align 8
+  %v.addr = alloca double, align 8
+  store double %v, double* %v.addr, align 8
+  %0 = load double, double* %v.addr, align 8
+  %cmp = fcmp olt double %0, 0.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store double 0.000000e+00, double* %retval, align 8
+  br label %return
+
+if.end:                                           ; preds = %entry
+  %1 = load double, double* %v.addr, align 8
+  %cmp1 = fcmp ogt double %1, 6.000000e+00
+  br i1 %cmp1, label %if.then2, label %if.end3
+
+if.then2:                                         ; preds = %if.end
+  store double 6.000000e+00, double* %retval, align 8
+  br label %return
+
+if.end3:                                          ; preds = %if.end
+  %2 = load double, double* %v.addr, align 8
+  store double %2, double* %retval, align 8
+  br label %return
+
+return:                                           ; preds = %if.end3, %if.then2, %if.then
+  %3 = load double, double* %retval, align 8
+  ret double %3
+}
+
+define void @loop(double* %X, double* %Y) {
+; CHECK-LABEL: @loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.cond.cleanup:
+; CHECK-NEXT:    ret void
+; CHECK:       for.body:
+; CHECK-NEXT:    [[I_05:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[CLAMP_EXIT:%.*]] ]
+; CHECK-NEXT:    [[IDXPROM:%.*]] = zext i32 [[I_05]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[Y:%.*]], i64 [[IDXPROM]]
+; CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[ARRAYIDX]], align 8
+; CHECK-NEXT:    [[CMP_I:%.*]] = fcmp olt double [[TMP0]], 0.000000e+00
+; CHECK-NEXT:    br i1 [[CMP_I]], label [[CLAMP_EXIT]], label [[IF_END_I:%.*]]
+; CHECK:       if.end.i:
+; CHECK-NEXT:    [[CMP1_I:%.*]] = fcmp ogt double [[TMP0]], 6.000000e+00
+; CHECK-NEXT:    br i1 [[CMP1_I]], label [[CLAMP_EXIT]], label [[IF_END3_I:%.*]]
+; CHECK:       if.end3.i:
+; CHECK-NEXT:    br label [[CLAMP_EXIT]]
+; CHECK:       clamp.exit:
+; CHECK-NEXT:    [[RETVAL_0_I:%.*]] = phi double [ [[TMP0]], [[IF_END3_I]] ], [ 0.000000e+00, [[FOR_BODY]] ], [ 6.000000e+00, [[IF_END_I]] ]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[X:%.*]], i64 [[IDXPROM]]
+; CHECK-NEXT:    store double [[RETVAL_0_I]], double* [[ARRAYIDX2]], align 8
+; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_05]], 1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[I_05]], 19999
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]]
+;
+entry:
+  %X.addr = alloca double*, align 8
+  %Y.addr = alloca double*, align 8
+  %i = alloca i32, align 4
+  store double* %X, double** %X.addr, align 8
+  store double* %Y, double** %Y.addr, align 8
+  %0 = bitcast i32* %i to i8*
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #2
+  store i32 0, i32* %i, align 4
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %1 = load i32, i32* %i, align 4
+  %cmp = icmp ult i32 %1, 20000
+  br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %for.cond
+  %2 = bitcast i32* %i to i8*
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #2
+  br label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %3 = load double*, double** %Y.addr, align 8
+  %4 = load i32, i32* %i, align 4
+  %idxprom = zext i32 %4 to i64
+  %arrayidx = getelementptr inbounds double, double* %3, i64 %idxprom
+  %5 = load double, double* %arrayidx, align 8
+  %call = call double @clamp(double %5)
+  %6 = load double*, double** %X.addr, align 8
+  %7 = load i32, i32* %i, align 4
+  %idxprom1 = zext i32 %7 to i64
+  %arrayidx2 = getelementptr inbounds double, double* %6, i64 %idxprom1
+  store double %call, double* %arrayidx2, align 8
+  br label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %8 = load i32, i32* %i, align 4
+  %inc = add i32 %8, 1
+  store i32 %inc, i32* %i, align 4
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond.cleanup
+  ret void
+}
+
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)

diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/lit.local.cfg b/llvm/test/Transforms/PhaseOrdering/AArch64/lit.local.cfg
new file mode 100644 (file)
index 0000000..7184443
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'AArch64' in config.root.targets:
+    config.unsupported = True