GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD

diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index a11c830..f284582 100644 (file)
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -496,6 +496,24 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
     unsigned InRegBits = TyBits - SrcBits + 1;
     return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1), InRegBits);
   }
+  case TargetOpcode::G_SEXTLOAD: {
+    // FIXME: We need an in-memory type representation.
+    if (DstTy.isVector())
+      return 1;
+
+    // e.g. i16->i32 = '17' bits known.
+    const MachineMemOperand *MMO = *MI.memoperands_begin();
+    return TyBits - MMO->getSizeInBits() + 1;
+  }
+  case TargetOpcode::G_ZEXTLOAD: {
+    // FIXME: We need an in-memory type representation.
+    if (DstTy.isVector())
+      return 1;
+
+    // e.g. i16->i32 = '16' bits known.
+    const MachineMemOperand *MMO = *MI.memoperands_begin();
+    return TyBits - MMO->getSizeInBits();
+  }
   case TargetOpcode::G_TRUNC: {
     Register Src = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(Src);

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
index cb18fe5..d900e6b 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
@@ -32,8 +32,7 @@ body:             |
     ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
     ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
-    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8
-    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
     %2:_(s32) = G_SEXT_INREG %1, 8
@@ -52,8 +51,7 @@ body:             |
     ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
     ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
-    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9
-    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
     %2:_(s32) = G_SEXT_INREG %1, 9
@@ -93,8 +91,7 @@ body:             |
     ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
     ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
-    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8
-    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
     %2:_(s32) = G_SEXT %1
@@ -114,8 +111,7 @@ body:             |
     ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
     ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
-    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9
-    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
     %2:_(s32) = G_SEXT %1
@@ -187,3 +183,62 @@ body:             |
     $vgpr0_vgpr1 = COPY %3
 
 ...
+
+---
+name: sext_inreg_s32_7_zextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_7_zextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 7
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 7
+    $vgpr0 = COPY %2
+
+...
+
+---
+name: sext_inreg_s32_8_zextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_8_zextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 8
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 8
+    $vgpr0 = COPY %2
+
+...
+
+---
+name: sext_inreg_s32_9_zextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_9_zextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 9
+    $vgpr0 = COPY %2
+
+...