phy: qcom-qmp-pcie: add support for pipediv2 clock

Some QMP PHYs have a second fixed-divider pipe clock that needs to be
enabled along with the pipe clock.

Add support for an optional "pipediv2" clock.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-15-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 0684455..d671b05 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1378,8 +1378,10 @@ struct qmp_pcie {
        void __iomem *tx2;
        void __iomem *rx2;
 
-       struct clk *pipe_clk;
        struct clk_bulk_data *clks;
+       struct clk_bulk_data pipe_clks[2];
+       int num_pipe_clks;
+
        struct reset_control_bulk_data *resets;
        struct regulator_bulk_data *vregs;
 
@@ -1923,11 +1925,9 @@ static int qmp_pcie_power_on(struct phy *phy)
        qmp_pcie_init_registers(qmp, &cfg->tbls);
        qmp_pcie_init_registers(qmp, mode_tbls);
 
-       ret = clk_prepare_enable(qmp->pipe_clk);
-       if (ret) {
-               dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
+       ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
+       if (ret)
                return ret;
-       }
 
        /* Pull PHY out of reset state */
        qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
@@ -1950,7 +1950,7 @@ static int qmp_pcie_power_on(struct phy *phy)
        return 0;
 
 err_disable_pipe_clk:
-       clk_disable_unprepare(qmp->pipe_clk);
+       clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
 
        return ret;
 }
@@ -1960,7 +1960,7 @@ static int qmp_pcie_power_off(struct phy *phy)
        struct qmp_pcie *qmp = phy_get_drvdata(phy);
        const struct qmp_phy_cfg *cfg = qmp->cfg;
 
-       clk_disable_unprepare(qmp->pipe_clk);
+       clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
 
        /* PHY reset */
        qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
@@ -2154,6 +2154,7 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np
        struct platform_device *pdev = to_platform_device(qmp->dev);
        const struct qmp_phy_cfg *cfg = qmp->cfg;
        struct device *dev = qmp->dev;
+       struct clk *clk;
 
        qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(qmp->serdes))
@@ -2206,12 +2207,16 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np
                }
        }
 
-       qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
-       if (IS_ERR(qmp->pipe_clk)) {
-               return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
+       clk = devm_get_clk_from_child(dev, np, NULL);
+       if (IS_ERR(clk)) {
+               return dev_err_probe(dev, PTR_ERR(clk),
                                     "failed to get pipe clock\n");
        }
 
+       qmp->num_pipe_clks = 1;
+       qmp->pipe_clks[0].id = "pipe";
+       qmp->pipe_clks[0].clk = clk;
+
        return 0;
 }