}
void PrintParameters(raw_ostream &OS) const {
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << LS;
if (Operands[i].isReg()) {
OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
} else if (Operands[i].isImm()) {
} else {
llvm_unreachable("Unknown operand kind!");
}
- if (i + 1 != e)
- OS << ", ";
}
}
void PrintArguments(raw_ostream &OS,
const std::vector<std::string> &PR) const {
assert(PR.size() == Operands.size());
- bool PrintedArg = false;
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (PR[i] != "")
// Implicit physical register operand.
continue;
- if (PrintedArg)
- OS << ", ";
+ OS << LS;
if (Operands[i].isReg()) {
OS << "Op" << i << ", Op" << i << "IsKill";
- PrintedArg = true;
} else if (Operands[i].isImm()) {
OS << "imm" << i;
- PrintedArg = true;
} else if (Operands[i].isFP()) {
OS << "f" << i;
- PrintedArg = true;
} else {
llvm_unreachable("Unknown operand kind!");
}
}
void PrintArguments(raw_ostream &OS) const {
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << LS;
if (Operands[i].isReg()) {
OS << "Op" << i << ", Op" << i << "IsKill";
} else if (Operands[i].isImm()) {
} else {
llvm_unreachable("Unknown operand kind!");
}
- if (i + 1 != e)
- OS << ", ";
}
}