altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL, 0);
} else {
altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL,
- BIT(spi->chip_select));
+ BIT(spi_get_chipselect(spi, 0)));
hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
}
case AMD_SPI_V1:
break;
case AMD_SPI_V2:
- amd_spi_clear_chip(amd_spi, message->spi->chip_select);
+ amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
break;
default:
return -ENODEV;
struct amd_spi *amd_spi = spi_master_get_devdata(master);
struct spi_device *spi = msg->spi;
- amd_spi_select_chip(amd_spi, spi->chip_select);
+ amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
/*
* Extract spi_transfers from the spi message and
iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
}
- reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
+ reg = AR934X_SPI_SHIFT_VAL(spi_get_chipselect(spi, 0), term,
trx_cur * 8);
iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
stat = readl_poll_timeout(
struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);
if (!enable)
- a3700_spi_activate_cs(a3700_spi, spi->chip_select);
+ a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0));
else
- a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
+ a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0));
}
static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
- struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
+ struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)];
u32 addr_mode, addr_mode_backup;
u32 ctl_val;
int ret = 0;
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
struct device *dev = aspi->dev;
- return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
+ return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
+ spi_get_chipselect(mem->spi, 0));
}
struct aspeed_spi_window {
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
- struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+ struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
struct spi_mem_op *op = &desc->info.op_tmpl;
u32 ctl_val;
int ret = 0;
u64 offset, size_t len, void *buf)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
- struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
+ struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
/* Switch to USER command mode if mapping window is too small */
if (chip->ahb_window_size < offset + len) {
{
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
const struct aspeed_spi_data *data = aspi->data;
- unsigned int cs = spi->chip_select;
+ unsigned int cs = spi_get_chipselect(spi, 0);
struct aspeed_spi_chip *chip = &aspi->chips[cs];
chip->aspi = aspi;
static void aspeed_spi_cleanup(struct spi_device *spi)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
- unsigned int cs = spi->chip_select;
+ unsigned int cs = spi_get_chipselect(spi, 0);
aspeed_spi_chip_enable(aspi, cs, false);
dev_dbg(&spi->dev,
"setup: bpw %u mode 0x%x -> mr %d %08x\n",
- spi->bits_per_word, spi->mode, spi->chip_select, mr);
+ spi->bits_per_word, spi->mode, spi_get_chipselect(spi, 0), mr);
return 0;
}
{
struct ath79_spi *sp = ath79_spidev_to_sp(spi);
int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
- u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
+ u32 cs_bit = AR71XX_SPI_IOC_CS(spi_get_chipselect(spi, 0));
if (cs_high)
sp->ioc_base |= cs_bit;
struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
/* Ensures that reading is performed on device connected to hardware cs0 */
- if (mem->spi->chip_select || mem->spi->cs_gpiod)
+ if (spi_get_chipselect(mem->spi, 0) || spi_get_csgpiod(mem->spi, 0))
return -ENOTSUPP;
/* Only use for fast-read op. */
int chip_select;
u32 mr;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
if (atmel_spi_is_v2(as)) {
spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
int chip_select;
u32 mr;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
/* only deactivate *this* device; sometimes transfers to
* another device may be active when this routine is called.
dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
spi_writel(as, CR, SPI_BIT(LASTXFER));
}
unsigned long bus_hz;
int chip_select;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
/* v1 chips start out at half the peripheral bus speed. */
bus_hz = as->spi_clk;
as = spi_controller_get_devdata(spi->controller);
/* see notes above re chipselect */
- if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
+ if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) {
dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
return -EINVAL;
}
*/
initialize_native_cs_for_gpio(as);
- if (spi->cs_gpiod && as->native_cs_free) {
+ if (spi_get_csgpiod(spi, 0) && as->native_cs_free) {
dev_err(&spi->dev,
"No native CS available to support this GPIO CS\n");
return -EBUSY;
}
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
csr = SPI_BF(BITS, bits - 8);
if (spi->mode & SPI_CPOL)
if (!(spi->mode & SPI_CPHA))
csr |= SPI_BIT(NCPHA);
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
csr |= SPI_BIT(CSAAT);
csr |= SPI_BF(DLYBS, 0);
dev_dbg(&spi->dev,
"setup: bpw %u mode 0x%x -> csr%d %08x\n",
- bits, spi->mode, spi->chip_select, csr);
+ bits, spi->mode, spi_get_chipselect(spi, 0), csr);
if (!atmel_spi_is_v2(as))
spi_writel(as, CSR0 + 4 * chip_select, csr);
switch (value) {
case BITBANG_CS_INACTIVE:
if (hw->pdata->deactivate_cs)
- hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
+ hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0),
cspol);
break;
} while ((stat & PSC_SPISTAT_DR) == 0);
if (hw->pdata->activate_cs)
- hw->pdata->activate_cs(hw->pdata, spi->chip_select,
+ hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0),
cspol);
break;
}
unsigned int mask = 0xff;
if (assert)
- mask ^= BIT(spi->chip_select);
+ mask ^= BIT(spi_get_chipselect(spi, 0));
spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
}
if (has_bspi(qspi))
mspi_cdram &= ~1;
else
- mspi_cdram |= (~(1 << spi->chip_select) &
+ mspi_cdram |= (~(1 << spi_get_chipselect(spi, 0)) &
MSPI_CDRAM_PCS);
write_cdram_slot(qspi, slot, mspi_cdram);
return -EIO;
from = op->addr.val;
- if (!spi->cs_gpiod)
- bcm_qspi_chip_select(qspi, spi->chip_select);
+ if (!spi_get_csgpiod(spi, 0))
+ bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
/*
int slots;
unsigned long timeo = msecs_to_jiffies(100);
- if (!spi->cs_gpiod)
- bcm_qspi_chip_select(qspi, spi->chip_select);
+ if (!spi_get_csgpiod(spi, 0))
+ bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
qspi->trans_pos.trans = trans;
qspi->trans_pos.byte = 0;
* The SPI core has successfully requested the CS GPIO line from the
* device tree, so we are done.
*/
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
return 0;
- if (spi->chip_select > 1) {
+ if (spi_get_chipselect(spi, 0) > 1) {
/* error in the case of native CS requested with CS > 1
* officially there is a CS2, but it is not documented
* which GPIO is connected with that...
if (!chip)
return 0;
- spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
- DRV_NAME,
- GPIO_LOOKUP_FLAGS_DEFAULT,
- GPIOD_OUT_LOW);
- if (IS_ERR(spi->cs_gpiod)) {
- ret = PTR_ERR(spi->cs_gpiod);
+ spi_set_csgpiod(spi, 0, gpiochip_request_own_desc(chip,
+ 8 - (spi_get_chipselect(spi, 0)),
+ DRV_NAME,
+ GPIO_LOOKUP_FLAGS_DEFAULT,
+ GPIOD_OUT_LOW));
+ if (IS_ERR(spi_get_csgpiod(spi, 0))) {
+ ret = PTR_ERR(spi_get_csgpiod(spi, 0));
goto err_cleanup;
}
/* and set up the "mode" and level */
dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
- spi->chip_select);
+ spi_get_chipselect(spi, 0));
return 0;
if (spi->mode & SPI_NO_CS)
return 0;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
return 0;
/* for dt-backwards compatibility: only support native on CS0
dev_warn(&spi->dev,
"Native CS is not supported - please configure cs-gpio in device-tree\n");
- if (spi->chip_select == 0)
+ if (spi_get_chipselect(spi, 0) == 0)
return 0;
dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
- unsigned int chip_select = spi->chip_select;
+ unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
const u8 *tx = t->tx_buf;
u8 *rx = t->rx_buf;
static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
struct spi_device *spi, int hz)
{
- unsigned int profile = spi->chip_select;
+ unsigned int profile = spi_get_chipselect(spi, 0);
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
- unsigned int chip_select = spi->chip_select;
+ unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
if (!t->cs_off)
- bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
+ bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
if (tx && rx)
opcode = HSSPI_OP_READ_WRITE;
u32 reg;
reg = __raw_readl(bs->regs +
- HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
if (spi->mode & SPI_CPHA)
reg |= SIGNAL_CTRL_LAUNCH_RISING;
else
reg |= SIGNAL_CTRL_LATCH_RISING;
__raw_writel(reg, bs->regs +
- HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
/* only change actual polarities if there is no transfer */
if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
if (spi->mode & SPI_CS_HIGH)
- reg |= BIT(spi->chip_select);
+ reg |= BIT(spi_get_chipselect(spi, 0));
else
- reg &= ~BIT(spi->chip_select);
+ reg &= ~BIT(spi_get_chipselect(spi, 0));
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
}
if (spi->mode & SPI_CS_HIGH)
- bs->cs_polarity |= BIT(spi->chip_select);
+ bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
else
- bs->cs_polarity &= ~BIT(spi->chip_select);
+ bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
mutex_unlock(&bs->bus_mutex);
* e. At the end restore the polarities again to their default values.
*/
- dummy_cs = !spi->chip_select;
+ dummy_cs = !spi_get_chipselect(spi, 0);
bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
list_for_each_entry(t, &msg->transfers, transfer_list) {
keep_cs = true;
} else {
if (!t->cs_off)
- bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
+ bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
spi_transfer_cs_change_delay_exec(msg, t);
if (!list_next_entry(t, transfer_list)->cs_off)
- bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
+ bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
}
} else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
- bcm63xx_hsspi_set_cs(bs, spi->chip_select, t->cs_off);
+ bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
}
}
bcm63xx_hsspi_set_cs(bs, dummy_cs, false);
if (status || !keep_cs)
- bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
+ bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
return status;
}
/* Issue the transfer */
cmd = SPI_CMD_START_IMMEDIATE;
cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
- cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
+ cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT);
bcm_spi_writew(bs, cmd, SPI_CMD);
/* Enable the CMD_DONE interrupt */
static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs,
struct spi_device *spi, int hz)
{
- unsigned int profile = spi->chip_select;
+ unsigned int profile = spi_get_chipselect(spi, 0);
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
struct spi_message *msg)
{
struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master);
- unsigned int chip_select = spi->chip_select;
+ unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
PINGPONG_COMMAND_START_NOW;
__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
- if (bcmbca_hsspi_wait_cmd(bs, spi->chip_select))
+ if (bcmbca_hsspi_wait_cmd(bs, spi_get_chipselect(spi, 0)))
return -ETIMEDOUT;
pending -= curr_step;
u32 reg;
reg = __raw_readl(bs->regs +
- HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
if (spi->mode & SPI_CPHA)
reg |= SIGNAL_CTRL_LAUNCH_RISING;
else
reg |= SIGNAL_CTRL_LATCH_RISING;
__raw_writel(reg, bs->regs +
- HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
if (spi->mode & SPI_CS_HIGH)
- reg |= BIT(spi->chip_select);
+ reg |= BIT(spi_get_chipselect(spi, 0));
else
- reg &= ~BIT(spi->chip_select);
+ reg &= ~BIT(spi_get_chipselect(spi, 0));
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
if (spi->mode & SPI_CS_HIGH)
- bs->cs_polarity |= BIT(spi->chip_select);
+ bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
else
- bs->cs_polarity &= ~BIT(spi->chip_select);
+ bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
reg = __raw_readl(bs->spim_ctrl);
- reg &= ~BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
+ reg &= ~BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
if (spi->mode & SPI_CS_HIGH)
- reg |= BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
+ reg |= BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
__raw_writel(reg, bs->spim_ctrl);
mutex_unlock(&bs->bus_mutex);
keep_cs = true;
} else {
if (!t->cs_off)
- bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
+ bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
spi_transfer_cs_change_delay_exec(msg, t);
if (!list_next_entry(t, transfer_list)->cs_off)
- bcmbca_hsspi_set_cs(bs, spi->chip_select, true);
+ bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
}
} else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
- bcmbca_hsspi_set_cs(bs, spi->chip_select, t->cs_off);
+ bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
}
msg->actual_length += t->len;
mutex_unlock(&bs->msg_mutex);
if (status || !keep_cs)
- bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
+ bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
msg->status = status;
spi_finalize_current_message(master);
struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
struct cqspi_flash_pdata *f_pdata;
- f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
+ f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
cqspi_configure(f_pdata, mem->spi->max_speed_hz);
if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
struct device *dev = &cqspi->pdev->dev;
- return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
+ return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
+ spi_get_chipselect(mem->spi, 0));
}
static const struct spi_controller_mem_ops cqspi_mem_ops = {
{
enum spi_mem_data_dir dir = op->data.dir;
- if (cdns_xspi->cur_cs != mem->spi->chip_select)
- cdns_xspi->cur_cs = mem->spi->chip_select;
+ if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0))
+ cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);
return cdns_xspi_send_stig_command(cdns_xspi, op,
(dir != SPI_MEM_NO_DATA));
/* Select the slave */
ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
if (!(xspi->is_decoded_cs))
- ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
+ ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL;
else
- ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
+ ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL;
}
mpi_cfg.s.cslate = cpha ? 1 : 0;
mpi_cfg.s.enable = 1;
- if (spi->chip_select < 4)
- p->cs_enax |= 1ull << (12 + spi->chip_select);
+ if (spi_get_chipselect(spi, 0) < 4)
+ p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0));
mpi_cfg.u64 |= p->cs_enax;
if (mpi_cfg.u64 != p->last_cfg) {
writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
}
mpi_tx.u64 = 0;
- mpi_tx.s.csid = spi->chip_select;
+ mpi_tx.s.csid = spi_get_chipselect(spi, 0);
mpi_tx.s.leavecs = 1;
mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
}
mpi_tx.u64 = 0;
- mpi_tx.s.csid = spi->chip_select;
+ mpi_tx.s.csid = spi_get_chipselect(spi, 0);
if (last_xfer)
mpi_tx.s.leavecs = xfer->cs_change;
else
bool cs_high = spi->mode & SPI_CS_HIGH;
if (enable)
- mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
+ mcfqspi_cs_select(mcfqspi, spi_get_chipselect(spi, 0), cs_high);
else
- mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
+ mcfqspi_cs_deselect(mcfqspi, spi_get_chipselect(spi, 0), cs_high);
}
static int mcfqspi_transfer_one(struct spi_master *master,
static int mcfqspi_setup(struct spi_device *spi)
{
mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
- spi->chip_select, spi->mode & SPI_CS_HIGH);
+ spi_get_chipselect(spi, 0), spi->mode & SPI_CS_HIGH);
dev_dbg(&spi->dev,
"bits per word %d, chip select %d, speed %d KHz\n",
- spi->bits_per_word, spi->chip_select,
+ spi->bits_per_word, spi_get_chipselect(spi, 0),
(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
/ 1000);
{
struct davinci_spi *dspi;
struct davinci_spi_config *spicfg = spi->controller_data;
- u8 chip_sel = spi->chip_select;
+ u8 chip_sel = spi_get_chipselect(spi, 0);
u16 spidat1 = CS_DEFAULT;
dspi = spi_master_get_devdata(spi->master);
* Board specific chip select logic decides the polarity and cs
* line for the controller
*/
- if (spi->cs_gpiod) {
+ if (spi_get_csgpiod(spi, 0)) {
if (value == BITBANG_CS_ACTIVE)
- gpiod_set_value(spi->cs_gpiod, 1);
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
else
- gpiod_set_value(spi->cs_gpiod, 0);
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
} else {
if (value == BITBANG_CS_ACTIVE) {
if (!(spi->mode & SPI_CS_WORD))
if (bits_per_word <= 8) {
dspi->get_rx = davinci_spi_rx_buf_u8;
dspi->get_tx = davinci_spi_tx_buf_u8;
- dspi->bytes_per_word[spi->chip_select] = 1;
+ dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 1;
} else {
dspi->get_rx = davinci_spi_rx_buf_u16;
dspi->get_tx = davinci_spi_tx_buf_u16;
- dspi->bytes_per_word[spi->chip_select] = 2;
+ dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 2;
}
if (!hz)
dspi = spi_master_get_devdata(spi->master);
if (!(spi->mode & SPI_NO_CS)) {
- if (np && spi->cs_gpiod)
+ if (np && spi_get_csgpiod(spi, 0))
internal_cs = false;
if (internal_cs)
- set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
+ set_io_bits(dspi->base + SPIPC0, 1 << spi_get_chipselect(spi, 0));
}
if (spi->mode & SPI_READY)
spicfg = &davinci_spi_default_cfg;
/* convert len to words based on bits_per_word */
- data_type = dspi->bytes_per_word[spi->chip_select];
+ data_type = dspi->bytes_per_word[spi_get_chipselect(spi, 0)];
dspi->tx = t->tx_buf;
dspi->rx = t->rx_buf;
struct dln2_spi *dln2 = spi_master_get_devdata(master);
struct spi_device *spi = message->spi;
- if (dln2->cs != spi->chip_select) {
- ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
+ if (dln2->cs != spi_get_chipselect(spi, 0)) {
+ ret = dln2_spi_cs_set_one(dln2, spi_get_chipselect(spi, 0));
if (ret < 0)
return ret;
- dln2->cs = spi->chip_select;
+ dln2->cs = spi_get_chipselect(spi, 0);
}
return 0;
* support active-high or active-low CS level.
*/
if (cs_high == enable)
- dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
+ dw_writel(dws, DW_SPI_SER, BIT(spi_get_chipselect(spi, 0)));
else
dw_writel(dws, DW_SPI_SER, 0);
}
struct dw_spi *dws = spi_master_get_devdata(spi->master);
struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
- u32 cs = spi->chip_select;
+ u32 cs = spi_get_chipselect(spi, 0);
if (cs < 4) {
u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
struct dw_spi *dws = spi_master_get_devdata(spi->master);
struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
- u8 cs = spi->chip_select;
+ u8 cs = spi_get_chipselect(spi, 0);
if (!enable) {
/* CS override drive enable */
* especially alen and dumlen.
*/
- priv->sfcmd = ((spi->chip_select
+ priv->sfcmd = ((spi_get_chipselect(spi, 0)
<< SFCMD_CS_OFFSET)
& SFCMD_CS_MASK);
priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
struct spi_message *mesg)
{
int rc;
- u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
+ u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(spi_get_chipselect(mesg->spi, 0) + 1);
unsigned int len;
struct spi_transfer *transfer;
struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
static void dspi_assert_cs(struct spi_device *spi, bool *cs)
{
- if (!spi->cs_gpiod || *cs)
+ if (!spi_get_csgpiod(spi, 0) || *cs)
return;
- gpiod_set_value_cansleep(spi->cs_gpiod, true);
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);
*cs = true;
}
static void dspi_deassert_cs(struct spi_device *spi, bool *cs)
{
- if (!spi->cs_gpiod || !*cs)
+ if (!spi_get_csgpiod(spi, 0) || !*cs)
return;
- gpiod_set_value_cansleep(spi->cs_gpiod, false);
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);
*cs = false;
}
/* Prepare command word for CMD FIFO */
dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0);
- if (!spi->cs_gpiod)
- dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi->chip_select);
+ if (!spi_get_csgpiod(spi, 0))
+ dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi_get_chipselect(spi, 0));
if (list_is_last(&dspi->cur_transfer->transfer_list,
&dspi->cur_msg->transfers)) {
chip->ctar_val |= SPI_CTAR_LSBFE;
}
- gpiod_direction_output(spi->cs_gpiod, false);
+ gpiod_direction_output(spi_get_csgpiod(spi, 0), false);
dspi_deassert_cs(spi, &cs);
spi_set_ctldata(spi, chip);
struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
- spi->controller->bus_num, spi->chip_select);
+ spi->controller->bus_num, spi_get_chipselect(spi, 0));
kfree(chip);
}
/* don't write the mode register if the mode doesn't change */
if (cs->hw_mode != hw_mode_old)
- fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
+ fsl_espi_write_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0)),
cs->hw_mode);
}
reinit_completion(&espi->done);
/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
- spcom = SPCOM_CS(spi->chip_select);
+ spcom = SPCOM_CS(spi_get_chipselect(spi, 0));
spcom |= SPCOM_TRANLEN(t->len - 1);
/* configure RXSKIP mode */
pm_runtime_get_sync(espi->dev);
- cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
+ cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0)));
/* mask out bits we are going to set */
cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
| CSMODE_REV);
if (fsl_lpspi->is_only_cs1)
fsl_lpspi->config.chip_select = 1;
else
- fsl_lpspi->config.chip_select = spi->chip_select;
+ fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
if (!fsl_lpspi->config.speed_hz)
fsl_lpspi->config.speed_hz = spi->max_speed_hz;
unsigned long rate = spi->max_speed_hz;
int ret;
- if (q->selected == spi->chip_select)
+ if (q->selected == spi_get_chipselect(spi, 0))
return;
if (needs_4x_clock(q))
if (ret)
return;
- q->selected = spi->chip_select;
+ q->selected = spi_get_chipselect(spi, 0);
fsl_qspi_invalidate(q);
}
name = devm_kasprintf(dev, GFP_KERNEL,
"%s-%d", dev_name(q->dev),
- mem->spi->chip_select);
+ spi_get_chipselect(mem->spi, 0));
if (!name) {
dev_err(dev, "failed to get memory for custom flash name\n");
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
u32 slvsel;
- u16 cs = spi->chip_select;
+ u16 cs = spi_get_chipselect(spi, 0);
if (cs < mpc8xxx_spi->native_chipselects) {
slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
cpha = CPHA;
if (spi_slv->mode & SPI_CS_HIGH)
- demux_output_inv = BIT(spi_slv->chip_select);
+ demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0));
- demux_sel = spi_slv->chip_select;
+ demux_sel = spi_get_chipselect(spi_slv, 0);
mas->cur_bits_per_word = spi_slv->bits_per_word;
spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
- peripheral.cs = spi_slv->chip_select;
+ peripheral.cs = spi_get_chipselect(spi_slv, 0);
peripheral.pack_en = true;
peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
/* Drive chip select line, if we have one */
if (spi_gpio->cs_gpios) {
- struct gpio_desc *cs = spi_gpio->cs_gpios[spi->chip_select];
+ struct gpio_desc *cs = spi_gpio->cs_gpios[spi_get_chipselect(spi, 0)];
/* SPI chip selects are normally active-low */
gpiod_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
* initialized from the descriptor lookup.
*/
if (spi_gpio->cs_gpios) {
- cs = spi_gpio->cs_gpios[spi->chip_select];
+ cs = spi_gpio->cs_gpios[spi_get_chipselect(spi, 0)];
if (!spi->controller_state && cs)
status = gpiod_direction_output(cs,
!(spi->mode & SPI_CS_HIGH));
static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master);
- struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select];
+ struct gxp_spi_chip *chip = &spifi->chips[spi_get_chipselect(mem->spi, 0)];
int ret;
if (op->data.dir == SPI_MEM_DATA_IN) {
static int gxp_spi_setup(struct spi_device *spi)
{
struct gxp_spi *spifi = spi_controller_get_devdata(spi->master);
- unsigned int cs = spi->chip_select;
+ unsigned int cs = spi_get_chipselect(spi, 0);
struct gxp_spi_chip *chip = &spifi->chips[cs];
chip->spifi = spifi;
{
struct hisi_sfc_v3xx_host *host;
struct spi_device *spi = mem->spi;
- u8 chip_select = spi->chip_select;
+ u8 chip_select = spi_get_chipselect(spi, 0);
host = spi_controller_get_devdata(spi->master);
val = spfi_readl(spfi, SPFI_PORT_STATE);
val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK <<
SPFI_PORT_STATE_DEV_SEL_SHIFT);
- val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
+ val |= spi_get_chipselect(msg->spi, 0) << SPFI_PORT_STATE_DEV_SEL_SHIFT;
if (msg->spi->mode & SPI_CPHA)
- val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
+ val |= SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0));
else
- val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
+ val &= ~SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0));
if (msg->spi->mode & SPI_CPOL)
- val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
+ val |= SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0));
else
- val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
+ val &= ~SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0));
spfi_writel(spfi, val, SPFI_PORT_STATE);
return 0;
div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
div = clamp(512 / (1 << get_count_order(div)), 1, 128);
- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
+ val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0)));
val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
+ spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0)));
spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
SPFI_TRANSACTION);
ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
/* set chip select to use */
- ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
+ ctrl |= MX51_ECSPI_CTRL_CS(spi_get_chipselect(spi, 0));
/*
* The ctrl register must be written first, with the EN bit set other
* BURST_LENGTH + 1 bits are received
*/
if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
- cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
+ cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0));
else
- cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
+ cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0));
if (spi->mode & SPI_CPOL) {
- cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
- cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
+ cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0));
+ cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0));
} else {
- cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
- cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
+ cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0));
+ cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0));
}
if (spi->mode & SPI_CS_HIGH)
- cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
+ cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0));
else
- cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
+ cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0));
if (cfg == current_cfg)
return 0;
cpha ^= flip_cpha;
if (cpha)
- cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
+ cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0));
else
- cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
+ cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0));
writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
}
reg |= MX31_CSPICTRL_POL;
if (spi->mode & SPI_CS_HIGH)
reg |= MX31_CSPICTRL_SSPOL;
- if (!spi->cs_gpiod)
- reg |= (spi->chip_select) <<
+ if (!spi_get_csgpiod(spi, 0))
+ reg |= (spi_get_chipselect(spi, 0)) <<
(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
MX31_CSPICTRL_CS_SHIFT);
reg |= MX21_CSPICTRL_POL;
if (spi->mode & SPI_CS_HIGH)
reg |= MX21_CSPICTRL_SSPOL;
- if (!spi->cs_gpiod)
- reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
+ if (!spi_get_csgpiod(spi, 0))
+ reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
writel(reg, spi_imx->base + MXC_CSPICTRL);
{
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
struct spi_device *spi = message->spi;
- unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select;
+ unsigned int cs = REG_SSICR1_FRMHL << spi_get_chipselect(spi, 0);
unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL;
unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs;
unsigned int ssicr0 = 0, ssicr1 = 0;
if (spi->mode & SPI_LOOP)
ssicr0 |= REG_SSICR0_LOOP;
- if (spi->chip_select)
+ if (spi_get_chipselect(spi, 0))
ssicr0 |= REG_SSICR0_FSEL;
if (spi->mode & SPI_CPHA)
/* Pick up the correct start address */
if (!mem)
return 0;
- return mem->spi->chip_select == 1 ? ispi->chip0_size : 0;
+ return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;
}
static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,
static void jcore_spi_chipsel(struct spi_device *spi, bool value)
{
struct jcore_spi *hw = spi_master_get_devdata(spi->master);
- u32 csbit = 1U << (2 * spi->chip_select);
+ u32 csbit = 1U << (2 * spi_get_chipselect(spi, 0));
- dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);
+ dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi_get_chipselect(spi, 0));
if (value)
hw->cs_reg |= csbit;
{
struct spi_master *master = spidev->master;
struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
- unsigned int cs = spidev->chip_select;
+ unsigned int cs = spi_get_chipselect(spidev, 0);
u32 gpocon;
/* GPIOs are used for CS */
- if (spidev->cs_gpiod)
+ if (spi_get_csgpiod(spidev, 0))
return 0;
dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
{
struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
- unsigned int cs = spidev->chip_select;
+ unsigned int cs = spi_get_chipselect(spidev, 0);
u32 fgpo;
if (!!(spidev->mode & SPI_CS_HIGH) == enable)
if (!spi_mem_internal_supports_op(mem, op))
return -ENOTSUPP;
- if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !mem->spi->cs_gpiod) {
+ if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !spi_get_csgpiod(mem->spi, 0)) {
ret = spi_mem_access_start(mem);
if (ret)
return ret;
op->data.dir != SPI_MEM_DATA_IN)
return -EINVAL;
- if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !mem->spi->cs_gpiod) {
+ if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !spi_get_csgpiod(mem->spi, 0)) {
ret = spi_mem_access_start(mem);
if (ret)
return ret;
conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
/* Select CS */
- conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
+ conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));
/* Default 8bit word */
conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);
reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
- reg &= ~BIT(spi->chip_select);
- reg |= !disable << spi->chip_select;
+ reg &= ~BIT(spi_get_chipselect(spi, 0));
+ reg |= !disable << spi_get_chipselect(spi, 0);
mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
}
*/
if (spi->mode & SPI_CS_HIGH) {
reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
- reg |= BIT(spi->chip_select);
+ reg |= BIT(spi_get_chipselect(spi, 0));
mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
}
return 0;
out_be32(psc_addr(mps, ccr), ccr);
mps->bits_per_word = cs->bits_per_word;
- if (spi->cs_gpiod) {
+ if (spi_get_csgpiod(spi, 0)) {
/* gpiolib will deal with the inversion */
- gpiod_set_value(spi->cs_gpiod, 1);
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
}
}
static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
{
- if (spi->cs_gpiod) {
+ if (spi_get_csgpiod(spi, 0)) {
/* gpiolib will deal with the inversion */
- gpiod_set_value(spi->cs_gpiod, 0);
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
}
}
int cs;
if (ms->gpio_cs_count > 0) {
- cs = ms->message->spi->chip_select;
+ cs = spi_get_chipselect(ms->message->spi, 0);
gpiod_set_value(ms->gpio_cs[cs], value);
} else {
out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
/* pad select */
if (mdata->dev_comp->need_pad_sel)
- writel(mdata->pad_sel[spi->chip_select],
+ writel(mdata->pad_sel[spi_get_chipselect(spi, 0)],
mdata->base + SPI_PAD_SEL_REG);
/* tick delay */
if (!spi->controller_data)
spi->controller_data = (void *)&mtk_default_chip_info;
- if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
+ if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
/* CS de-asserted, gpiolib will handle inversion */
- gpiod_direction_output(spi->cs_gpiod, 0);
+ gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
return 0;
}
static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
{
struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
- int cs = spi->chip_select;
+ int cs = spi_get_chipselect(spi, 0);
u32 polar = 0;
u32 master;
struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller);
int ret;
- ret = mux_control_select(priv->mux, spi->chip_select);
+ ret = mux_control_select(priv->mux, spi_get_chipselect(spi, 0));
if (ret)
return ret;
- if (priv->current_cs == spi->chip_select)
+ if (priv->current_cs == spi_get_chipselect(spi, 0))
return 0;
dev_dbg(&priv->spi->dev, "setting up the mux for cs %d\n",
- spi->chip_select);
+ spi_get_chipselect(spi, 0));
/* copy the child device's settings except for the cs */
priv->spi->max_speed_hz = spi->max_speed_hz;
priv->spi->mode = spi->mode;
priv->spi->bits_per_word = spi->bits_per_word;
- priv->current_cs = spi->chip_select;
+ priv->current_cs = spi_get_chipselect(spi, 0);
return 0;
}
nio = 2;
return flags | HC_CFG_NIO(nio) |
- HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
- HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1);
+ HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |
+ HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1);
}
static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op,
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LRD_RANGE);
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
- LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LRD_CTRL);
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LWR_RANGE);
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
- LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LWR_CTRL);
writel(HC_EN_BIT, mxic->regs + HC_EN);
writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes),
- mxic->regs + SS_CTRL(mem->spi->chip_select));
+ mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0)));
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
mxic->regs + HC_CFG);
/* Program CS register bits here, it will be used for all transfers. */
writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
- writel(mxs_spi_cs_to_reg(m->spi->chip_select),
+ writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
list_for_each_entry(t, &m->transfers, transfer_list) {
{
struct npcm_fiu_spi *fiu =
spi_controller_get_devdata(desc->mem->spi->master);
- struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
+ struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr +
offs);
u8 *buf_rx = buf;
{
struct npcm_fiu_spi *fiu =
spi_controller_get_devdata(desc->mem->spi->master);
- struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
+ struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr +
offs);
const u8 *buf_tx = buf;
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
NPCM_FIU_UMA_CTS_DEV_NUM,
- (mem->spi->chip_select <<
+ (spi_get_chipselect(mem->spi, 0) <<
NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode);
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
NPCM_FIU_UMA_CTS_DEV_NUM,
- (mem->spi->chip_select <<
+ (spi_get_chipselect(mem->spi, 0) <<
NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
NPCM_FIU_UMA_CTS_DEV_NUM,
- (mem->spi->chip_select <<
+ (spi_get_chipselect(mem->spi, 0) <<
NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
NPCM_FIU_UMA_CTS_SW_CS, 0);
{
struct npcm_fiu_spi *fiu =
spi_controller_get_devdata(mem->spi->master);
- struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];
+ struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(mem->spi, 0)];
int ret = 0;
u8 *buf;
{
struct npcm_fiu_spi *fiu =
spi_controller_get_devdata(desc->mem->spi->master);
- struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
+ struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
struct regmap *gcr_regmap;
if (!fiu->res_mem) {
chip->flash_region_mapped_ptr =
devm_ioremap(fiu->dev, (fiu->res_mem->start +
(fiu->info->max_map_size *
- desc->mem->spi->chip_select)),
+ spi_get_chipselect(desc->mem->spi, 0))),
(u32)desc->info.length);
if (!chip->flash_region_mapped_ptr) {
dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");
struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
struct npcm_fiu_chip *chip;
- chip = &fiu->chip[spi->chip_select];
+ chip = &fiu->chip[spi_get_chipselect(spi, 0)];
chip->fiu = fiu;
- chip->chipselect = spi->chip_select;
+ chip->chipselect = spi_get_chipselect(spi, 0);
chip->clkrate = spi->max_speed_hz;
fiu->clkrate = clk_get_rate(fiu->clk);
* Return, if previously selected slave device is same as current
* requested slave device.
*/
- if (f->selected == spi->chip_select)
+ if (f->selected == spi_get_chipselect(spi, 0))
return;
/* Reset FLSHxxCR0 registers */
size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
- 4 * spi->chip_select);
+ 4 * spi_get_chipselect(spi, 0));
- dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select);
+ dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
nxp_fspi_clk_disable_unprep(f);
if (ret)
return;
- f->selected = spi->chip_select;
+ f->selected = spi_get_chipselect(spi, 0);
}
static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
name = devm_kasprintf(dev, GFP_KERNEL,
"%s-%d", dev_name(f->dev),
- mem->spi->chip_select);
+ spi_get_chipselect(mem->spi, 0));
if (!name) {
dev_err(dev, "failed to get memory for custom flash name\n");
w = uwire_read_reg(UWIRE_CSR);
old_cs = (w >> 10) & 0x03;
- if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
+ if (value == BITBANG_CS_INACTIVE || old_cs != spi_get_chipselect(spi, 0)) {
/* Deselect this CS, or the previous CS */
w &= ~CS_CMD;
uwire_write_reg(UWIRE_CSR, w);
else
uwire_write_reg(UWIRE_SR4, 0);
- w = spi->chip_select << 10;
+ w = spi_get_chipselect(spi, 0) << 10;
w |= CS_CMD;
uwire_write_reg(UWIRE_CSR, w);
}
if (!t->tx_buf && !t->rx_buf)
return 0;
- w = spi->chip_select << 10;
+ w = spi_get_chipselect(spi, 0) << 10;
w |= CS_CMD;
if (t->tx_buf) {
rate /= 8;
break;
}
- omap_uwire_configure_mode(spi->chip_select, flags);
+ omap_uwire_configure_mode(spi_get_chipselect(spi, 0), flags);
pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
__func__, flags,
clk_get_rate(uwire->ck) / 1000,
{
struct spi_device *spi = data;
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
- struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
/* We must disable the DMA RX request */
omap2_mcspi_set_dma_req(spi, 1, 0);
{
struct spi_device *spi = data;
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
- struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
/* We must disable the DMA TX request */
omap2_mcspi_set_dma_req(spi, 0, 0);
struct dma_async_tx_descriptor *tx;
mcspi = spi_master_get_devdata(spi->master);
- mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
struct dma_async_tx_descriptor *tx;
mcspi = spi_master_get_devdata(spi->master);
- mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
count = xfer->len;
/*
int wait_res;
mcspi = spi_master_get_devdata(spi->master);
- mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
if (cs->word_len <= 8) {
width = DMA_SLAVE_BUSWIDTH_1_BYTE;
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
if (!cs)
return -ENOMEM;
- cs->base = mcspi->base + spi->chip_select * 0x14;
- cs->phys = mcspi->phys + spi->chip_select * 0x14;
+ cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
+ cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
cs->mode = 0;
cs->chconf0 = 0;
cs->chctrl0 = 0;
u32 chconf;
mcspi = spi_master_get_devdata(master);
- mcspi_dma = mcspi->dma_channels + spi->chip_select;
+ mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0);
cs = spi->controller_state;
cd = spi->controller_data;
omap2_mcspi_set_enable(spi, 0);
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
if (par_override ||
omap2_mcspi_set_enable(spi, 0);
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
if (mcspi->fifo_depth > 0 && t)
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
struct omap2_mcspi_dma *mcspi_dma =
- &mcspi->dma_channels[spi->chip_select];
+ &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
return false;
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
struct omap2_mcspi_dma *mcspi_dma =
- &mcspi->dma_channels[spi->chip_select];
+ &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
return mcspi->max_xfer_len;
* as it is handled by a GPIO, but that doesn't matter. What we need
* is to deassert the old chip select and assert some other chip select.
*/
- val |= ORION_SPI_CS(spi->chip_select);
+ val |= ORION_SPI_CS(spi_get_chipselect(spi, 0));
/*
* Chip select logic is inverted from spi_set_cs(). For lines using a
unsigned int count;
int word_len;
struct orion_spi *orion_spi;
- int cs = spi->chip_select;
+ int cs = spi_get_chipselect(spi, 0);
void __iomem *vaddr;
word_len = spi->bits_per_word;
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
if (enable) {
regval &= ~SPI_MST_CTL_DEVSEL_MASK;
- regval |= (spi->chip_select << 25);
+ regval |= (spi_get_chipselect(spi, 0) << 25);
writel(regval,
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
} else {
- regval &= ~(spi->chip_select << 25);
+ regval &= ~(spi_get_chipselect(spi, 0) << 25);
writel(regval,
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
u32 nbits;
/* Device selection */
- bd_ctrl = spi->chip_select << BD_DEVSEL_SHIFT;
+ bd_ctrl = spi_get_chipselect(spi, 0) << BD_DEVSEL_SHIFT;
/* half-duplex: select transfer buffer, direction and lane */
if (xfer->rx_buf) {
* unreliable/erroneous SPI transactions.
* To avoid that we will always handle /CS by toggling GPIO.
*/
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
return -EINVAL;
return 0;
static void pic32_spi_cleanup(struct spi_device *spi)
{
/* de-activate cs-gpio, gpiolib will handle inversion */
- gpiod_direction_output(spi->cs_gpiod, 0);
+ gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
}
static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
/* Setup the SPI using the per chip configuration */
pl022->cur_chip = spi_get_ctldata(msg->spi);
- pl022->cur_cs = msg->spi->chip_select;
+ pl022->cur_cs = spi_get_chipselect(msg->spi, 0);
/* This is always available but may be set to -ENOENT */
- pl022->cur_gpiod = msg->spi->cs_gpiod;
+ pl022->cur_gpiod = spi_get_csgpiod(msg->spi, 0);
restore_state(pl022);
flush(pl022);
value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
- cs = spi->chip_select;
+ cs = spi_get_chipselect(spi, 0);
cs <<= config->cs_sel_shift;
if (cs != (value & config->cs_sel_mask)) {
/*
spi_controller_get_devdata(spi->controller);
if (drv_data->ssp_type == CE4100_SSP) {
- pxa2xx_spi_write(drv_data, SSSR, spi->chip_select);
+ pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
return;
}
return -ENOMEM;
if (drv_data->ssp_type == CE4100_SSP) {
- if (spi->chip_select > 4) {
+ if (spi_get_chipselect(spi, 0) > 4) {
dev_err(&spi->dev,
"failed setup: cs number must not be > 4.\n");
kfree(chip);
mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
mstr_cfg &= ~CHIP_SELECT_NUM;
- if (message->spi->chip_select)
+ if (spi_get_chipselect(message->spi, 0))
mstr_cfg |= CHIP_SELECT_NUM;
mstr_cfg |= FB_CLK_EN | PIN_WPN | PIN_HOLDN | SBL_EN | FULL_CYCLE_MODE;
* command set was designed to almost not clash with that of the
* boot flash.
*/
- if (spi->chip_select == 2)
+ if (spi_get_chipselect(spi, 0) == 2)
/* MMC */
spi_ioc = AR71XX_SPI_IOC_CS0;
else
/* set the Controller */
ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
- cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT;
+ cmd |= spi_get_chipselect(mem->spi, 0) << SFC_CMD_CS_SHIFT;
dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
op->addr.nbytes, op->addr.buswidth,
bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
/* Return immediately for no-op */
- if (cs_asserted == rs->cs_asserted[spi->chip_select])
+ if (cs_asserted == rs->cs_asserted[spi_get_chipselect(spi, 0)])
return;
if (cs_asserted) {
/* Keep things powered as long as CS is asserted */
pm_runtime_get_sync(rs->dev);
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
else
- ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
+ ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
+ BIT(spi_get_chipselect(spi, 0)));
} else {
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
else
- ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
+ ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
+ BIT(spi_get_chipselect(spi, 0)));
/* Drop reference from when we first asserted CS */
pm_runtime_put(rs->dev);
}
- rs->cs_asserted[spi->chip_select] = cs_asserted;
+ rs->cs_asserted[spi_get_chipselect(spi, 0)] = cs_asserted;
}
static void rockchip_spi_handle_err(struct spi_controller *ctlr,
if (spi->mode & SPI_LSB_FIRST)
cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
if (spi->mode & SPI_CS_HIGH)
- cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
+ cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
if (xfer->rx_buf && xfer->tx_buf)
cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
u32 cr0;
- if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
+ if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
return -EINVAL;
}
cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
- if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
- cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
- else if (spi->chip_select <= 1)
- cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
+ if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1)
+ cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
+ else if (spi_get_chipselect(spi, 0) <= 1)
+ cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET);
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
u8 sslp;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
return 0;
pm_runtime_get_sync(&rspi->pdev->dev);
sslp = rspi_read8(rspi, RSPI_SSLP);
if (spi->mode & SPI_CS_HIGH)
- sslp |= SSLP_SSLP(spi->chip_select);
+ sslp |= SSLP_SSLP(spi_get_chipselect(spi, 0));
else
- sslp &= ~SSLP_SSLP(spi->chip_select);
+ sslp &= ~SSLP_SSLP(spi_get_chipselect(spi, 0));
rspi_write8(rspi, sslp, RSPI_SSLP);
spin_unlock_irq(&rspi->lock);
rspi->spcmd |= SPCMD_LSBF;
/* Configure slave signal to assert */
- rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
- : spi->chip_select);
+ rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs
+ : spi_get_chipselect(spi, 0));
/* CMOS output mode and MOSI signal from previous transfer */
rspi->sppcr = 0;
/* NULL is fine, we just avoid using the FB delay (=0) */
if (IS_ERR(cs)) {
- dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
+ dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
return -ENODEV;
}
if (hw->tlen == 0) {
/* First byte (I2C command) is chip select */
- hw->buffer[0] = 1 << msg->spi->chip_select;
+ hw->buffer[0] = 1 << spi_get_chipselect(msg->spi, 0);
hw->tlen = 1;
hw->rindex = 0;
}
struct sc18is602 *hw = spi_master_get_devdata(spi->master);
/* SC18IS602 does not support CS2 */
- if (hw->id == sc18is602 && spi->chip_select == 2)
+ if (hw->id == sc18is602 && (spi_get_chipselect(spi, 0) == 2))
return -ENXIO;
return 0;
spi_controller_get_devdata(spi->controller);
u32 clr, set, tmp;
- if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
+ if (spi_get_csgpiod(spi, 0) || spi_controller_is_slave(p->ctlr))
return 0;
if (p->native_cs_inited &&
u32 ss, cs_high;
/* Configure pins before asserting CS */
- if (spi->cs_gpiod) {
+ if (spi_get_csgpiod((struct spi_device *)spi, 0)) {
ss = ctlr->unused_native_cs;
cs_high = p->native_cs_high;
} else {
- ss = spi->chip_select;
+ ss = spi_get_chipselect((struct spi_device *)spi, 0);
cs_high = !!(spi->mode & SPI_CS_HIGH);
}
sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
struct sh_sci_spi *sp = spi_master_get_devdata(dev->master);
if (sp->info->chip_select)
- (sp->info->chip_select)(sp->info, dev->chip_select, value);
+ (sp->info->chip_select)(sp->info, spi_get_chipselect(dev, 0), value);
}
static int sh_sci_spi_probe(struct platform_device *dev)
/* Update the chip select polarity */
if (device->mode & SPI_CS_HIGH)
- spi->cs_inactive &= ~BIT(device->chip_select);
+ spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0));
else
- spi->cs_inactive |= BIT(device->chip_select);
+ spi->cs_inactive |= BIT(spi_get_chipselect(device, 0));
sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
/* Select the correct device */
- sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, spi_get_chipselect(device, 0));
/* Set clock mode */
sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
int unit;
/* Set one chip select */
- writel(BIT(spi->chip_select), ospi->base + OSPI_SSEL);
+ writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL);
mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1);
prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode);
return -EINVAL;
}
- if (!spi->cs_gpiod) {
+ if (!spi_get_csgpiod(spi, 0)) {
dev_err(&spi->dev, "no valid gpio assigned\n");
return -EINVAL;
}
static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op)
{
struct stm32_qspi *qspi = spi_controller_get_devdata(spi->master);
- struct stm32_qspi_flash *flash = &qspi->flash[spi->chip_select];
+ struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)];
u32 ccr, cr;
int timeout, err = 0, err_poll_status = 0;
struct spi_mem_op op;
int ret = 0;
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
return -EOPNOTSUPP;
ret = pm_runtime_resume_and_get(qspi->dev);
mutex_lock(&qspi->lock);
- gpiod_set_value_cansleep(spi->cs_gpiod, true);
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
u8 dummy_bytes = 0;
}
end_of_transfer:
- gpiod_set_value_cansleep(spi->cs_gpiod, false);
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);
mutex_unlock(&qspi->lock);
presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
- flash = &qspi->flash[spi->chip_select];
- flash->cs = spi->chip_select;
+ flash = &qspi->flash[spi_get_chipselect(spi, 0)];
+ flash->cs = spi_get_chipselect(spi, 0);
flash->presc = presc;
mutex_lock(&qspi->lock);
reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
reg &= ~SUN4I_CTL_CS_MASK;
- reg |= SUN4I_CTL_CS(spi->chip_select);
+ reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0));
/* We want to control the chip select manually */
reg |= SUN4I_CTL_CS_MANUAL;
reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
reg &= ~SUN6I_TFR_CTL_CS_MASK;
- reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
+ reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));
if (enable)
reg |= SUN6I_TFR_CTL_CS_LEVEL;
}
mode = spi->mode;
- cs = spi->chip_select;
+ cs = spi_get_chipselect(spi, 0);
speed = xfer->speed_hz;
bpw = xfer->bits_per_word;
sspi->bpw = bpw;
sspi->mode = mode;
sspi->speed = speed;
- sspi->cs = spi->chip_select;
+ sspi->cs = spi_get_chipselect(spi, 0);
sspi->bus_width = bus_width;
return 0;
val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK <<
SYNQUACER_HSSPI_DMPSEL_CS_SHIFT);
- val |= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT;
+ val |= spi_get_chipselect(spi, 0) << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT;
if (!enable)
val |= SYNQUACER_HSSPI_DMSTOP_STOP;
if (setup_dly && hold_dly) {
setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
- spi->chip_select,
+ spi_get_chipselect(spi, 0),
setup_hold);
if (tspi->spi_cs_timing1 != spi_cs_timing) {
tspi->spi_cs_timing1 = spi_cs_timing;
inactive_cycles--;
cs_state = inactive_cycles ? 0 : 1;
spi_cs_timing = tspi->spi_cs_timing2;
- SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+ SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
cs_state);
- SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
+ SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
inactive_cycles);
if (tspi->spi_cs_timing2 != spi_cs_timing) {
tspi->spi_cs_timing2 = spi_cs_timing;
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
/* GPIO based chip select control */
- if (spi->cs_gpiod)
- gpiod_set_value(spi->cs_gpiod, 1);
+ if (spi_get_csgpiod(spi, 0))
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
if (is_single_xfer && !(t->cs_change)) {
tspi->use_hw_based_cs = true;
command1 &= ~SPI_CS_SW_VAL;
}
- if (tspi->last_used_cs != spi->chip_select) {
+ if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) {
if (cdata && cdata->tx_clk_tap_delay)
tx_tap = cdata->tx_clk_tap_delay;
if (cdata && cdata->rx_clk_tap_delay)
SPI_RX_TAP_DELAY(rx_tap);
if (command2 != tspi->def_command2_reg)
tegra_spi_writel(tspi, command2, SPI_COMMAND2);
- tspi->last_used_cs = spi->chip_select;
+ tspi->last_used_cs = spi_get_chipselect(spi, 0);
}
} else {
command1 |= SPI_TX_EN;
tspi->cur_direction |= DATA_DIR_TX;
}
- command1 |= SPI_CS_SEL(spi->chip_select);
+ command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0));
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
tspi->command1_reg = command1;
spin_lock_irqsave(&tspi->lock, flags);
/* GPIO based chip select control */
- if (spi->cs_gpiod)
- gpiod_set_value(spi->cs_gpiod, 0);
+ if (spi_get_csgpiod(spi, 0))
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
val = tspi->def_command1_reg;
if (spi->mode & SPI_CS_HIGH)
- val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
+ val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
else
- val |= SPI_CS_POL_INACTIVE(spi->chip_select);
+ val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
tspi->def_command1_reg = val;
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
spin_unlock_irqrestore(&tspi->lock, flags);
int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
/* GPIO based chip select control */
- if (spi->cs_gpiod)
- gpiod_set_value(spi->cs_gpiod, 0);
+ if (spi_get_csgpiod(spi, 0))
+ gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
if (!tspi->use_hw_based_cs) {
if (cs_val)
command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
else
command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
- command |= SPI_CS0_EN << spi->chip_select;
+ command |= SPI_CS0_EN << spi_get_chipselect(spi, 0);
} else {
command = tsd->command_reg;
command &= ~SPI_BIT_LENGTH(~0);
spin_lock_irqsave(&tspi->lock, flags);
val = tspi->def_command_reg;
if (spi->mode & SPI_CS_HIGH)
- val |= cs_pol_bit[spi->chip_select];
+ val |= cs_pol_bit[spi_get_chipselect(spi, 0)];
else
- val &= ~cs_pol_bit[spi->chip_select];
+ val &= ~cs_pol_bit[spi_get_chipselect(spi, 0)];
tspi->def_command_reg = val;
tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
spin_unlock_irqrestore(&tspi->lock, flags);
tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
tspi->command2_reg = tspi->def_command2_reg;
- tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
+ tspi->command2_reg |= SLINK_SS_EN_CS(spi_get_chipselect(spi, 0));
tspi->command_reg &= ~SLINK_MODES;
if (spi->mode & SPI_CPHA)
tegra_qspi_mask_clear_irq(tqspi);
command1 = tqspi->def_command1_reg;
- command1 |= QSPI_CS_SEL(spi->chip_select);
+ command1 |= QSPI_CS_SEL(spi_get_chipselect(spi, 0));
command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
command1 &= ~QSPI_CONTROL_MODE_MASK;
/* keep default cs state to inactive */
val = tqspi->def_command1_reg;
- val |= QSPI_CS_SEL(spi->chip_select);
+ val |= QSPI_CS_SEL(spi_get_chipselect(spi, 0));
if (spi->mode & SPI_CS_HIGH)
- val &= ~QSPI_CS_POL_INACTIVE(spi->chip_select);
+ val &= ~QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
else
- val |= QSPI_CS_POL_INACTIVE(spi->chip_select);
+ val |= QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
tqspi->def_command1_reg = val;
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
if (qspi->ctrl_base) {
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
MEM_CS_MASK,
- MEM_CS_EN(spi->chip_select));
+ MEM_CS_EN(spi_get_chipselect(spi, 0)));
}
qspi->mmap_enabled = true;
- qspi->current_cs = spi->chip_select;
+ qspi->current_cs = spi_get_chipselect(spi, 0);
}
static void ti_qspi_disable_memory_map(struct spi_device *spi)
memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
ti_qspi_write(qspi, memval,
- QSPI_SPI_SETUP_REG(spi->chip_select));
+ QSPI_SPI_SETUP_REG(spi_get_chipselect(spi, 0)));
}
static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
mutex_lock(&qspi->list_lock);
- if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) {
+ if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) {
ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz);
ti_qspi_enable_memory_map(mem->spi);
}
qspi->dc = 0;
if (spi->mode & SPI_CPHA)
- qspi->dc |= QSPI_CKPHA(spi->chip_select);
+ qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0));
if (spi->mode & SPI_CPOL)
- qspi->dc |= QSPI_CKPOL(spi->chip_select);
+ qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0));
if (spi->mode & SPI_CS_HIGH)
- qspi->dc |= QSPI_CSPOL(spi->chip_select);
+ qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));
frame_len_words = 0;
list_for_each_entry(t, &m->transfers, transfer_list)
/* setup command reg */
qspi->cmd = 0;
- qspi->cmd |= QSPI_EN_CS(spi->chip_select);
+ qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0));
qspi->cmd |= QSPI_FLEN(frame_len_words);
ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
struct spi_device *pspi)
{
if (data->current_chip != NULL) {
- if (pspi->chip_select != data->n_curnt_chip) {
+ if (spi_get_chipselect(pspi, 0) != data->n_curnt_chip) {
dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
data->current_chip = NULL;
}
data->current_chip = pspi;
- data->n_curnt_chip = data->current_chip->chip_select;
+ data->n_curnt_chip = spi_get_chipselect(data->current_chip, 0);
dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
pch_spi_setup_transfer(pspi);
if (op->data.dir == SPI_MEM_DATA_OUT)
wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
- ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3,
+ ret = wpcm_fiu_do_uma(fiu, spi_get_chipselect(mem->spi, 0), op->addr.nbytes == 3,
op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
if (op->data.dir == SPI_MEM_DATA_IN)
static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
- int cs = mem->spi->chip_select;
+ int cs = spi_get_chipselect(mem->spi, 0);
wpcm_fiu_ects_assert(fiu, cs);
static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
- int cs = mem->spi->chip_select;
+ int cs = spi_get_chipselect(mem->spi, 0);
/* First transfer */
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
- int cs = mem->spi->chip_select;
+ int cs = spi_get_chipselect(mem->spi, 0);
wpcm_fiu_ects_assert(fiu, cs);
static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
- int cs = desc->mem->spi->chip_select;
+ int cs = spi_get_chipselect(desc->mem->spi, 0);
if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
return -ENOTSUPP;
static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf)
{
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
- int cs = desc->mem->spi->chip_select;
+ int cs = spi_get_chipselect(desc->mem->spi, 0);
if (offs >= MAX_MEMORY_SIZE_PER_CS)
return -ENOTSUPP;
static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm,
struct spi_device *spi, int is_active)
{
- unsigned long cs = spi->chip_select;
+ unsigned long cs = spi_get_chipselect(spi, 0);
uint16_t chipselect = spi_xcomm->chipselect;
if (is_active)
*/
cs = xspi->cs_inactive;
- cs ^= BIT(spi->chip_select);
+ cs ^= BIT(spi_get_chipselect(spi, 0));
/* Activate the chip select */
xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
if (spi->mode & SPI_CS_HIGH)
- xspi->cs_inactive &= ~BIT(spi->chip_select);
+ xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0));
else
- xspi->cs_inactive |= BIT(spi->chip_select);
+ xspi->cs_inactive |= BIT(spi_get_chipselect(spi, 0));
return 0;
}
int cs;
xspi = spi_master_get_devdata(spi->master);
- cs = spi->chip_select;
+ cs = spi_get_chipselect(spi, 0);
/*
* The value of fdiv must be between 4 and 65535.
*/
struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
int ret = 0;
- xspi->cs = spi->chip_select;
+ xspi->cs = spi_get_chipselect(spi, 0);
xspi->dev = spi->dev;
if (spi_transfer_is_last(master, t))
/* Select the lower (CS0) or upper (CS1) memory */
if (ctlr->num_chipselect > 1) {
config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);
- if (!spi->chip_select)
+ if (!spi_get_chipselect(spi, 0))
config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;
else
config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
if (!is_high) {
- if (!qspi->chip_select) {
+ if (!spi_get_chipselect(qspi, 0)) {
xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
} else {
struct spi_controller *ctlr = spi->controller;
if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
- ctlr->cs_gpiods[spi->chip_select])
+ ctlr->cs_gpiods[spi_get_chipselect(spi, 0)])
tmp &= ~SPI_CS_HIGH;
}
}
if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
- ctlr->cs_gpiods[spi->chip_select])
+ ctlr->cs_gpiods[spi_get_chipselect(spi, 0)])
tmp |= SPI_CS_HIGH;
tmp |= spi->mode & ~SPI_MODE_MASK;
spidev->devt = MKDEV(SPIDEV_MAJOR, minor);
dev = device_create(spidev_class, &spi->dev, spidev->devt,
spidev, "spidev%d.%d",
- spi->master->bus_num, spi->chip_select);
+ spi->master->bus_num, spi_get_chipselect(spi, 0));
status = PTR_ERR_OR_ZERO(dev);
} else {
dev_dbg(&spi->dev, "no minor number available!\n");
TP_fast_assign(
__entry->bus_num = spi->controller->bus_num;
- __entry->chip_select = spi->chip_select;
+ __entry->chip_select = spi_get_chipselect(spi, 0);
__entry->mode = spi->mode;
__entry->bits_per_word = spi->bits_per_word;
__entry->max_speed_hz = spi->max_speed_hz;
TP_fast_assign(
__entry->bus_num = spi->controller->bus_num;
- __entry->chip_select = spi->chip_select;
+ __entry->chip_select = spi_get_chipselect(spi, 0);
__entry->mode = spi->mode;
__entry->enable = enable;
),
TP_fast_assign(
__entry->bus_num = msg->spi->controller->bus_num;
- __entry->chip_select = msg->spi->chip_select;
+ __entry->chip_select = spi_get_chipselect(msg->spi, 0);
__entry->msg = msg;
),
TP_fast_assign(
__entry->bus_num = msg->spi->controller->bus_num;
- __entry->chip_select = msg->spi->chip_select;
+ __entry->chip_select = spi_get_chipselect(msg->spi, 0);
__entry->msg = msg;
__entry->frame = msg->frame_length;
__entry->actual = msg->actual_length;
TP_fast_assign(
__entry->bus_num = msg->spi->controller->bus_num;
- __entry->chip_select = msg->spi->chip_select;
+ __entry->chip_select = spi_get_chipselect(msg->spi, 0);
__entry->xfer = xfer;
__entry->len = xfer->len;
projects / platform / kernel / linux-rpi.git / commitdiff