{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
{"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
+ {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@tab Enable the SME2.1 Extension.
@item @code{sve2p1} @tab N/A @tab No
@tab Enable the SVE2.1 Extension.
+@item @code{rcpc3} @tab Armv9.4-A @tab No
+ @tab Enable the rcpc3 additional Support for Release Consistency Model
+ Extension. This implies @code{rcpc2}.
@end multitable
@node AArch64 Syntax
AARCH64_FEATURE (SME2p1);
static const aarch64_feature_set aarch64_feature_sve2p1 =
AARCH64_FEATURE (SVE2p1);
+static const aarch64_feature_set aarch64_feature_rcpc3 =
+ AARCH64_FEATURE (RCPC3);
+
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
#define B16B16 &aarch64_feature_b16b16
#define SME2p1 &aarch64_feature_sme2p1
#define SVE2p1 &aarch64_feature_sve2p1
+#define RCPC3 &aarch64_feature_rcpc3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }